KR101622167B1 - Apparatus for packaging an electronic components - Google Patents

Apparatus for packaging an electronic components Download PDF

Info

Publication number
KR101622167B1
KR101622167B1 KR1020150034640A KR20150034640A KR101622167B1 KR 101622167 B1 KR101622167 B1 KR 101622167B1 KR 1020150034640 A KR1020150034640 A KR 1020150034640A KR 20150034640 A KR20150034640 A KR 20150034640A KR 101622167 B1 KR101622167 B1 KR 101622167B1
Authority
KR
South Korea
Prior art keywords
dielectric
dielectric sheet
sheets
conductive patterns
sheet
Prior art date
Application number
KR1020150034640A
Other languages
Korean (ko)
Inventor
이영철
Original Assignee
목포해양대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 목포해양대학교 산학협력단 filed Critical 목포해양대학교 산학협력단
Priority to KR1020150034640A priority Critical patent/KR101622167B1/en
Application granted granted Critical
Publication of KR101622167B1 publication Critical patent/KR101622167B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

An electronic component packaging apparatus according to an embodiment of the present invention includes a dielectric layer formed by stacking at least two dielectric sheets, a plurality of conductive patterns formed on a partial upper region of each of the dielectric sheets, and at least one dielectric sheet At least one mounting region capable of mounting at least one or more semiconductor chips by patterning the dielectric sheets; and a plurality of conductive patterns formed through patterning for each of the dielectric sheets and selectively interconnecting the plurality of conductive patterns, A plurality of vias for selectively connecting the conductive patterns to the semiconductor chip, a capacitor formed by using at least one or more dielectric sheets of the dielectric sheets and the plurality of conductive patterns, One of A resistor formed by forming a resistance pattern on an upper portion of the resistance pattern and connecting both sides of the resistance pattern to conductive patterns on a dielectric sheet on which the resistance pattern is formed, and conductive patterns formed on at least two of the dielectric sheets, And an inductor formed by interconnecting via vias formed in the sheets.

Description

[0001] APPARATUS FOR PACKAGING AN ELECTRONIC COMPONENTS [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component packaging apparatus capable of forming a semiconductor chip and elements necessary for driving the semiconductor chip on a multilayer substrate using a multilayer substrate technology.

BACKGROUND ART [0002] With the recent development of ultra-small wearable devices, the demand for ultra-small parts has been increasing. Thus, module technologies are being developed that incorporate resistors, capacitors, and inductors in chip-scale packaging or multi-layer PCBs.

Conventional modularization technology has a problem that the design and manufacture of electronic products and electronic devices are limited according to the size of the PCB board because the semiconductor chip and the driving elements for surface mounting such as resistors, capacitors, and inductors are all mounted on the PCB board, There is a limitation in miniaturization.

Resistors, inductors, and capacitors are integrated using multi-layer substrate technologies such as low-teperature co-fired ceramic (LTCC) to form various functional circuits such as filters, duplexers, And is manufactured as a module. However, it is mainly applied to microwave components and modules because it uses a ceramic substrate with a low relative dielectric constant of about 5 to 9.

In the case of a capacitor or an inductor having various capacitances or inductances required for driving various semiconductor chips including a digital semiconductor chip, a multilayer ceramic capacitor (hereinafter referred to as " multilayer ceramic capacitor ") using a ceramic substrate having a dielectric constant value as high as 30 to 100, MLCC ') and ferrite. The capacitors and inductors are fabricated individually using chip inductor technology using a magnetic substrate with a magnetic permeability as high as 100, and assembled on a PCB substrate.

Therefore, there is a problem that it is difficult to fabricate a capacitor and an inductor simultaneously on a single substrate.

Korean Patent Publication No. 2005-0096454 (October 10, 2005)

The present invention provides an electronic component packaging apparatus capable of implementing a semiconductor chip and resistors, inductors, and capacitors necessary for driving the semiconductor chip using conductive patterns and vias formed in the stacked dielectric sheets.

The present invention also provides a method of fabricating electronic components by stacking dielectric sheets using multilayer substrate technology such as LTCC, MLCC, or multilayer PCB, forming conductive patterns and vias in the stacked dielectric sheets, The present invention also provides an electronic component packaging apparatus capable of performing packaging.

The present invention provides an electronic component packaging apparatus capable of implementing an inductor having a high inductance value in a structure in which dielectric sheets are laminated by applying a magnetic material to an electronic component packaging.

The present invention also provides an electronic component packaging apparatus capable of realizing a capacitor having a high capacitance value by using a dielectric material having a high dielectric constant of dielectric sheets.

According to an embodiment of the present invention, there is provided a semiconductor device comprising: a dielectric layer formed by stacking at least two dielectric sheets; a plurality of conductive patterns formed on an upper partial area of each of the dielectric sheets; At least one mounting area capable of mounting one or more semiconductor chips; patterning for each of the dielectric sheets and selectively interconnecting the plurality of conductive patterns; interconnecting the dielectric sheets; A plurality of vias for selectively connecting the patterns to the semiconductor chip; a capacitor formed by using at least one or more dielectric sheets of the dielectric sheets and at least one of the plurality of conductive patterns; A resistance pattern A resistor formed by connecting both sides of the resistance pattern to the conductive patterns on the dielectric sheet on which the resistance pattern is formed and conductive patterns formed on at least two of the dielectric sheets by vias formed in the at least two dielectric sheets And an inductor formed by interconnecting the plurality of semiconductor devices with each other.

According to an embodiment of the present invention, the dielectric layer is formed by stacking dielectric sheets 1, 2, 3, 4, 5, 6, 7 and 8, in which some dielectric sheets are made of different materials or made of the same material, And is formed using conductive patterns and vias formed on the dielectric sheets 1 to 6.

According to an embodiment of the present invention, the capacitor interconnects the conductive patterns formed on the dielectric sheets 1, 3 and 5 using vias formed in the dielectric sheet 2 to the dielectric sheet 5, and the dielectric sheets 2, 4 And 6 are interconnected using vias formed in the dielectric sheet 3 to the dielectric sheet 5, and a conductive pattern formed on the dielectric sheet 1 is electrically connected to the dielectric sheet 1 via vias formed in the dielectric sheet 1, And is connected to a surface mounting pad formed on the lower surface of the sheet 1. Fig.

According to the embodiment of the present invention, the inductor is formed by interconnecting one end portions of the conductive patterns formed in the upper part of the dielectric sheet 1 to the dielectric sheet 4 with vias formed in the dielectric sheet 2 to the dielectric sheet 4 .

According to an embodiment of the present invention, the packaging apparatus includes a structure for wrapping the inside and the outside of another inductor, in which conductive patterns on at least two or more dielectric sheets of the dielectric sheets are interconnected using a plurality of vias, using a magnetic material And a magnetic body inductor.

According to an embodiment of the present invention, the magnetic inductor interconnects the one end portions of the conductive patterns formed in the upper part of the dielectric sheet 3 to the dielectric sheet 6 using vias formed in the dielectric sheet 4 to the dielectric sheet 6 First and second magnetic patterns formed on the dielectric sheet 2 and on the dielectric sheet 7, and first and second magnetic material vias formed through the dielectric sheets 2 to 7, And a structure that surrounds the conductive patterns connected to each other via the vias of the dielectric sheet 6.

According to an embodiment of the present invention, the capacitor may be formed by forming the magnetic material on the dielectric sheets through an LTCC or MLCC or PCB process to form the first and second magnetic material vias and the first and second magnetic patterns .

According to an embodiment of the present invention, the magnetic inductor further includes a magnetic pattern formed inside the conductive patterns formed on the upper portion of the dielectric sheet 3 to the dielectric sheet 6.

According to an embodiment of the present invention, the packaging apparatus includes a dielectric pattern having a higher dielectric constant than the dielectric sheets surrounding a part of the conductive pattern formed on the upper portion of the dielectric sheet 8, and a dielectric pattern And a capacitor.

According to an embodiment of the present invention, the packaging apparatus further comprises a parallel plate capacitor formed by using a conductive pattern formed on the dielectric sheet 8 having a high relative dielectric constant among the dielectric sheets and a conductive pattern formed on the dielectric sheet 7 .

According to an embodiment of the present invention, the dielectric sheets are formed through LTCC or MLCC or PCB processes.

According to an embodiment of the present invention, the dielectric sheets are formed of a material having a dielectric constant different from that of the capacitor according to the capacitance of the capacitor.

According to an embodiment of the present invention, a semiconductor chip mounted on the mounting region is connected to a conductive pattern formed on the dielectric sheet through wire bonding or solder bumps.

According to an embodiment of the present invention, the mounting area and the plurality of vias are formed by patterning the dielectric sheets by laser machining or mechanical punching.

According to an embodiment of the present invention, a buffer material is buried after the semiconductor chip is mounted on the mounting region.

According to an embodiment of the present invention, the resistance pattern is formed by overlapping the conductive patterns on the dielectric sheet on which the resistance pattern is formed.

According to an embodiment of the present invention, the dielectric layer further includes a solder bump or a surface mounting pad for inputting and outputting an electric signal to the lower surface.

According to the embodiments of the present invention, since the passive elements necessary for driving the semiconductor chip are three-dimensionally integrated in the package using a plurality of dielectric sheets, conductive patterns and vias, the size of the entire electronic component board can be reduced .

In addition, according to the embodiments of the present invention, since terminals of most semiconductor chips except for input and output of power and signals are used for connecting passive elements for driving, in the present invention, three- The number of electronic component package terminals can be reduced, which reduces the size of the package and facilitates assembly with electronic devices.

According to the embodiment of the present invention, by forming the electronic component packaging apparatus using the dielectric sheets formed through the LTCC, MLCC, or PCB process, the processes necessary for manufacturing and assembling electronic components can be omitted, Generation and energy can be reduced.

1 is a perspective view showing an electronic component packaging apparatus according to an embodiment of the present invention,
2 is a cross-sectional view of an electronic component packaging apparatus according to an embodiment of the present invention,
3A and 3B are plan views illustrating a process of forming first and second resistors in an electronic part packaging apparatus according to an embodiment of the present invention,
4 is a perspective view illustrating a process of forming an inductor in an electronic component packaging apparatus according to an embodiment of the present invention,
FIG. 5 is a cross-sectional view illustrating a process of forming an inductor in an electronic component packaging apparatus according to an embodiment of the present invention,
6 is a perspective view for explaining a structure of a magnetic body inductor according to an embodiment of the present invention,
7 is a layered exploded view for explaining a structure of a magnetic body inductor according to an embodiment of the present invention,
8 is a perspective view illustrating a structure of a capacitor according to an embodiment of the present invention,
9 is a plan view for explaining a structure of a capacitor according to an embodiment of the present invention,
10 is a sectional view for explaining a dielectric patterned capacitor of an electronic part packaging apparatus according to an embodiment of the present invention,
11 is a cross-sectional view illustrating a parallel plate capacitor of an electronic part packaging apparatus according to an embodiment of the present invention,
12 is a plan view showing a structure of a mounting region for mounting a semiconductor chip of an electronic component packaging apparatus according to an embodiment of the present invention.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. The following detailed description is provided to provide a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, this is merely an example and the present invention is not limited thereto.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intention or custom of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification. The terms used in the detailed description are intended only to describe embodiments of the invention and should in no way be limiting.

FIG. 1 is a perspective view showing an electronic component packaging apparatus according to an embodiment of the present invention, and FIG. 2 is a sectional view of an electronic component packaging apparatus according to an embodiment of the present invention.

1 and 2, an electronic component packaging apparatus includes a dielectric layer 100 composed of a plurality of dielectric sheets 101 to 108, a dielectric layer 102 formed on the dielectric sheets 101 to 108 inside the dielectric layer 100, Chip mounting regions 160 on which the first and second resistors 120 and 122, the inductor 130, the capacitor 140 and the semiconductor chips 150 can be mounted; a plurality of surfaces formed on the lower surface of the dielectric layer 100; A plurality of solder bumps 180 connected to the mounting pads 170 and the plurality of surface mounting pads 170, respectively.

The electronic component packaging apparatus may further include a magnetic body inductor 190, a dielectric patterned capacitor 192, and a parallel plate capacitor 194.

The dielectric sheets 101 to 108 of the dielectric layer 100 may be formed using a LTCC green sheet capable of low-temperature firing, a dielectric sheet used for MLCC, or a PCB substrate. In addition, the dielectric sheets 101 to 108 may have a structure in which they are stacked in parallel to each other in the upward direction.

The dielectric sheets 101 to 108 include a plurality of conductive patterns, for example, first to eighth conductive patterns 101a to 108a, which are formed in parallel to each other and formed in an upper partial region, The plurality of conductive patterns may be selectively connected to the first and second resistors 120 and 122, the inductor 130, the capacitor 140, the semiconductor chips 150 and 152, A plurality of vias connecting the magnetic inductor 190, the dielectric patterned capacitor 192, and the parallel plate capacitor 194. The conductive pattern and the via formed in the dielectric sheet 1 101 in the embodiment of the present invention are defined as the first conductive pattern 101a and the first via 101b and the conductive pattern formed in the dielectric sheet 101 The conductive patterns and vias formed in the dielectric sheet 8 (108) are defined as the eighth conductive pattern 108a and the eighth via 108b in such a manner that the first conductive pattern 102a and the second via 102b are defined as the second conductive pattern 102a and the second via 102b, respectively .

The first to eighth conductive patterns 101a to 108a may be formed on each surface of the dielectric sheets 101 to 108 and may be formed using a conductive material mixed with a metal material or a metal material.

The first to eighth vias 101b to 108b may be formed by filling a hole formed through at least a portion of the dielectric sheets 101 to 108 with a conductive material composed of a metal material, a metal mixture, or the like. Here, the holes for forming the first to eighth vias 101b to 108b may be formed through punching or laser machining of the dielectric sheets 101 to 108.

The first to eighth conductive patterns 101a to 108a formed on the dielectric sheets 101 to 108 and the first to eighth vias 101b to 108b are selectively connected to form the inductor 130 and the capacitor 140 . Specifically, the first to eighth conductive patterns 101a to 108a are used as a part of the structure for forming the first and second resistors 120 and 122, the inductor 130, and the capacitor 140, 1 and the second resistors 120 and 122 and the other elements or may be used as terminals for connecting the inductors 120, the capacitors 140, the magnetic inductors 190, the dielectric patterned capacitors 192 and the parallel plate capacitors 194) and the like.

The electronic component packaging apparatus according to the embodiment of the present invention includes a magnetic body inductor (not shown) electrically connected to the semiconductor chip 150 using the magnetic patterns 600 and 610, the magnetic via 620, and the dielectric pattern 710 190 and a dielectric-patterned capacitor 192. In this case,

The first and second resistors 120 and 122 may be formed through the formation of a resistive pattern on the top of the dielectric sheet 4 104 and the top of the dielectric sheet 8 108 of the dielectric layer 100. A fourth conductive pattern 104a and an eighth conductive pattern 108a formed on the dielectric sheet 4 (104) and the dielectric sheet 8 (108) may be connected to both ends of the resistance pattern.

A process of forming the first and second resistors 120 and 122 will be described with reference to FIGS. 3A and 3B.

FIGS. 3A and 3B are plan views illustrating a process of forming first and second resistors 120 and 122 in an electronic part packaging apparatus according to an embodiment of the present invention.

3A, the first resistor 120 and the second resistor 122 are electrically connected to the fourth conductive pattern 104a and the eighth conductive pattern 104a formed on the dielectric sheet 4 (104) and the dielectric sheet 8 (108) And may be formed using the conductive pattern 108a. Specifically, the second resist pattern 300 is formed between the fourth conductive patterns 104a after the fourth conductive pattern 104a is formed by using a resistive material, The resistor 120 can be formed. At this time, the first resistance pattern 300 may be formed so as to include an overlapping area with the fourth conductive patterns 104a. The fourth conductive pattern 104a formed at one end of the first resistance pattern 300 is electrically connected to the dielectric sheet 5 through the fifth and sixth vias 105b and 106b formed on the dielectric sheets 5 and 6 The fourth conductive pattern 104a formed on the other end is connected to the sixth conductive pattern 106a formed on the dielectric sheet 5 through the fifth via 105b formed on the dielectric sheet 5, May be electrically connected to a fifth conductive pattern 105a formed on an upper portion of the first conductive pattern 105.

In this manner, a second resistor 122 may also be formed on top of the dielectric sheet 8 (108), as shown in Figure 3B. The eighth conductive pattern 108a connected to one end of the second resistance pattern 310 for forming the second resistor 122 is connected to the seventh conductive pattern 108a formed on the dielectric sheet 7 107 and the dielectric sheet 8 And the sixth conductive pattern 106a connected to the dielectric sheet 6 106 through the eighth vias 107b and 108b.

The inductor 130 is connected to one end portion of the first to fourth conductive patterns 101a to 104a formed in the upper partial area of the dielectric sheets 1 to 101 through the dielectric sheet 1 May be formed by interconnecting via vias formed in the sheet 4 (104).

The process of forming such an inductor 130 will be described with reference to FIGS. 4 to 5. FIG.

FIG. 4 is a perspective view illustrating a process of forming an inductor 130 in an electronic part packaging apparatus according to an embodiment of the present invention. FIG. 5 is a cross- And FIG.

4 to 5, the inductor 130 includes the first to fourth conductive patterns 102a to 105a formed in the upper part of the dielectric sheet 1 (101) to 104 (104) of the dielectric layer 130, And second to fourth vias 102b to 104b interconnecting one end portion of the first to fourth conductive patterns 101a to 104a. At this time, the first to fourth conductive patterns 101a to 104a may be rectangular shapes having a predetermined width and a central portion opened at a portion, but the present invention is not limited thereto. In other words, the first to fourth conductive patterns 101a to 104a may have a circular or elliptical shape with a certain width and a central portion and a part thereof opened.

One end of the first conductive pattern 101a of the inductor 130 according to the embodiment of the present invention is connected to the surface mounting pad 170 through the first via 101b formed in the dielectric sheet 1 . A portion of the first conductive pattern 101a, that is, a portion where the first conductive pattern 101a and the second conductive pattern 102a are connected to each other for forming the inductor 130, The end portion of the semiconductor chip 150 is connected to the sixth via 106b through the fifth conductive pattern 105a formed on the upper portion of the dielectric sheet 5 through the second through fifth vias 102b to 105b, To the sixth conductive pattern 106a formed on the lower surface of the mounting area 160, that is, the upper portion of the dielectric sheet 6 (106).

The inductance value of the inductor 130 in the electronic part packaging apparatus according to the embodiment of the present invention is determined by the number of the dielectric sheets used for forming the inductor 130 or the shape of the first through fourth conductive patterns 101a through 104a . ≪ / RTI >

Meanwhile, the electronic component packaging apparatus according to the embodiment of the present invention may further include a magnetic body inductor 190 having a magnetic body. That is, the electronic component packaging apparatus may further include a magnetic body inductor 190 having a structure that surrounds the inside and the outside of the inductor formed in the manner shown in FIGS. 4 and 5 using a magnetic material. This will be described with reference to FIGS. 6 and 7. FIG.

FIG. 6 is a perspective view for explaining the structure of the magnetic body inductor 190 according to the embodiment of the present invention, and FIG. 7 is a layered exploded view for explaining the structure of the magnetic body inductor 190 according to the embodiment of the present invention.

6 and 7, the magnetic inductor 190 is formed of the third to sixth conductive patterns (not shown) formed in the dielectric sheets 3 to 103 in the manner described in Figs. 4 to 5, The first to sixth vias 104a to 106a and the fourth to sixth vias 104b to 106b that connect the inductors 190a to 106a. More specifically, the magnetic material patterns 600 and 610 are formed by using a magnetic material in a part of the upper part of the dielectric sheet 2 and the dielectric sheet 7 (107), and both end portions of the magnetic material patterns 600 and 610 The inductor 190a formed on the dielectric sheet 3 (103) to the dielectric sheet 6 (106) can be covered with the magnetic material by forming a plurality of magnetic material vias 620 that can be connected.

In addition, the third to sixth conductive patterns 103a to 106a may include magnetic patterns 630, 632, 634, and 636 formed at predetermined intervals. The magnetic pattern 630, 632, 634, and 636 may have a shape corresponding to the third to sixth conductive patterns 103a to 106a. For example, when the third to sixth conductive patterns 103a to 106a are rectangular, the magnetic patterns 630, 632, 634, and 636 may have a rectangular shape.

The inductor 190a formed on the dielectric sheets 3 to 103 in the embodiment of the present invention is preferably formed to be spaced apart from the magnetic patterns 600 and 610 and the magnetic via 620 .

In the embodiment of the present invention, the magnetic material may mean a material having a specific permeability of 1 or more.

As described above, by covering the inductor 190a with the magnetic material, the inductance of the inductor 190a can be greatly improved by increasing the magnetic field.

The other end portion of the third conductive pattern 103a formed on the dielectric sheet 3 103 in the magnetic body inductor 190 according to the embodiment of the present invention is formed on the dielectric sheet 1 101 to the dielectric sheet 3 103 And may be connected to the surface mounting pad 170 through the first to third vias 101b to 103b.

The sixth conductive pattern 106a formed on the dielectric sheet 6 106 in the magnetic body inductor 190 according to the embodiment of the present invention is extended on the dielectric sheet 6 106 and is mounted on the semiconductor chip 150 The sixth conductive pattern 106a formed on the lower surface of the region 160, that is, the upper portion of the dielectric sheet 6 (106).

The capacitor 140 may be formed using at least one of the dielectric sheets and a conductive pattern formed on the at least one dielectric sheet. This will be described with reference to Figs. 8 to 9. Fig.

FIG. 8 is a perspective view illustrating a structure of a capacitor 140 according to an embodiment of the present invention, and FIG. 9 is a plan view illustrating a structure of a capacitor 140 according to an embodiment of the present invention.

8 to 9, the capacitor 140 may be formed on the dielectric sheet 1 (101) to the dielectric sheet 6 (106). Specifically, the capacitor 140 includes second to sixth vias 102b to 106b for interconnecting the dielectric sheets 1 to 101 and a dielectric sheet 1 to 101 The first to sixth conductive patterns 101a to 106a formed in the upper part of the upper part of the first conductive pattern 101a.

More specifically, the capacitor 140 connects the other end portions of the first, third, and fifth conductive patterns 101a, 103a, and 105a using the second to fifth vias 102b to 105b, The first and second conductive patterns 102a, 104a, and 106a may be connected in parallel by using the third to sixth vias 103b to 106b. Here, one end portion of the first conductive pattern 101a may be connected to the surface mounting pad 170 through the first via 101a formed in the dielectric sheet 1, The sixth conductive pattern 106a formed on the dielectric sheet 6 is formed on the lower surface of the mounting area 160 on which the semiconductor chip 150 is mounted, .

The electronic component packaging apparatus according to the embodiment of the present invention may further include a dielectric patterned capacitor 192. [

The dielectric patterned capacitor 192 surrounds a part of the eighth conductive pattern 108a formed on the upper portion of the dielectric sheet 8 and forms a dielectric pattern 900 having a relatively high dielectric constant in the dielectric sheets of the dielectric layer 100 And a ninth conductive pattern 910 that surrounds a portion of the dielectric pattern 900. This will be described with reference to FIG.

10 is a cross-sectional view for explaining a dielectric patterned capacitor 192 of an electronic component packaging apparatus according to an embodiment of the present invention.

10, the dielectric patterned capacitor 192 is formed by forming an eighth conductive pattern 108a having a predetermined area in an upper portion of the dielectric sheet 8 (108), and then forming an eighth conductive pattern 108a A dielectric pattern 900 may be formed to cover a part of the upper surface and the side surface and a ninth conductive pattern 910 may be formed to cover the upper surface and the side surface of the dielectric pattern 900. Here, as the dielectric material for forming the dielectric pattern 900, a material having a dielectric constant higher than that of the dielectric sheets of the dielectric layer 100 may be used.

In an embodiment of the present invention, the dielectric pattern 900 may be formed by a screen printing process, an inkjet printing process, or a three-dimensional printing process.

One end of the ninth conductive pattern 910 of the dielectric patterned capacitor 192 is connected to the eighth via 108b formed in the dielectric sheet 8 and the eighth via 108b is connected to the dielectric sheet 7 < / RTI > (107).

The capacity of the dielectric patterned capacitor 192 is adjusted by adjusting the dielectric constant of the dielectric material and the area 920 where the eighth and ninth conductive patterns 108a and 910 formed on the upper and lower portions of the dielectric pattern 900 overlap with each other Lt; / RTI >

The electronic component packaging apparatus according to the embodiment of the present invention may further include a parallel plate capacitor 194 using any one of the dielectric sheets 101 to 108. This will be described with reference to FIG.

11 is a cross-sectional view illustrating a parallel plate capacitor 194 of an electronic component packaging apparatus according to an embodiment of the present invention.

As shown in Fig. 11, the parallel plate capacitor 194 may be formed using a dielectric sheet having a high dielectric constant, for example, the dielectric sheet 8 (108), among the dielectric sheets 101-108. Specifically, the parallel plate capacitor 194 includes an eighth conductive pattern 108a formed on the dielectric sheet 8 (108) having a high relative dielectric constant among the dielectric sheets 101 to 108, and an eighth conductive pattern 108a formed on the dielectric sheet 7 May be formed using the seventh conductive pattern 107a formed. Specifically, the parallel plate capacitor 192 is connected to the eighth conductive pattern 108a having a predetermined area in the upper part of the dielectric sheet 8 (108), that is, the eighth conductive pattern 108a used in the dielectric patterned capacitor 192 A seventh conductive pattern 108a formed in a region where an upper part of the dielectric sheet 7 107 is partially overlapped with the eighth conductive pattern 108a, 107a. The seventh conductive pattern 107a may be connected to the sixth conductive pattern 106a extending from the capacitor 140 through the seventh via 107b formed in the dielectric sheet 7 107. The seventh conductive pattern 107a may be connected to the sixth conductive pattern 106a, 108a may be connected to an eighth via 108b formed in the dielectric sheet 8 (108).

The capacitance of the parallel plate capacitor 194 can be adjusted by the area 930 where the seventh conductive pattern 107a and the eighth conductive pattern 108a formed on the upper and lower portions of the dielectric sheet 8 108 overlap with each other. The parallel plate capacitor 194 also includes elements integrated in another dielectric sheet such as a first resistor 120, a capacitor 140, a semiconductor chip 150 (not shown) via a seventh via 107b formed in the dielectric sheet 7 May be connected to the sixth conductive pattern 106a.

The dielectric layer 100 according to the embodiment of the present invention may further include a mounting region 160 on which the semiconductor chip 150 can be mounted. This will be described with reference to FIG.

12 is a plan view showing the structure of the mounting region 160 for mounting the semiconductor chip 150 of the electronic component packaging apparatus according to the embodiment of the present invention.

First, as shown in FIG. 12, a mounting region 150 can be formed by patterning a part of dielectric sheets of the dielectric layer 100, for example, the dielectric sheet 7 107 and the dielectric sheet 8 108. Specifically, the mounting region 160 can be formed by patterning the dielectric sheet 7 107 and the dielectric sheet 8 (108) such that a part of the upper surface of the dielectric sheet 6 (106) is opened through punching or laser processing.

A plurality of sixth conductive patterns 106a spaced apart from each other by a predetermined distance are formed in the mounting area 160, that is, above the dielectric sheet 6 (107). The plurality of sixth conductive patterns 107a formed in the mounting region 150 may be connected to a plurality of solder bumps 150a formed on the lower surface of the semiconductor chip 150. [

The size and shape of the sixth conductive pattern 106a formed in the mounting region 160 may be determined by the shape and size of the connection terminal pad 150b included in the semiconductor chip 150 mounted on the mounting region 160, It can be changed depending on the layout.

In addition, after the semiconductor chip 150 is mounted on the mounting region, the buffer material 160a may be embedded and filled.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, . Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by equivalents to the appended claims, as well as the appended claims.

100: dielectric layers 120 and 122; The first and second resistors
130: Inductor 140: Capacitor
150: semiconductor chip 160: chip mounting area
170: Surface mounting pad 180: Solder bump

Claims (18)

A dielectric layer formed by stacking at least two or more dielectric sheets,
A plurality of conductive patterns formed on an upper portion of each of the dielectric sheets,
At least one mounting region capable of mounting at least one semiconductor chip by patterning at least one dielectric sheet in the dielectric layer,
A plurality of vias formed through patterning for each of the dielectric sheets and selectively interconnecting the plurality of conductive patterns, interconnecting the dielectric sheets, selectively connecting the conductive patterns to the semiconductor chip,
A capacitor formed by using at least one or more dielectric sheets of the dielectric sheets and the plurality of conductive patterns,
A resistor formed by forming a resistance pattern on one of the dielectric sheets and connecting both sides of the resistance pattern to the conductive patterns on the dielectric sheet on which the resistance pattern is formed;
And an inductor formed by interconnecting conductive patterns formed on at least two of the dielectric sheets with vias formed in the at least two dielectric sheets,
The dielectric layer may be formed by stacking dielectric sheets 1, 2, 3, 4, 5, 6, 7, and 8 made of the same material,
The capacitors are formed using conductive patterns and vias formed on the dielectric sheets 1 to 6,
Further comprising a magnetic material inductor having a structure that surrounds the inside and outside of another inductor in which the conductive patterns on at least two dielectric sheets of the dielectric sheets are interconnected by using a plurality of vias using a magnetic material. Component packaging device.
delete The method according to claim 1,
The capacitor
The conductive patterns formed on the dielectric sheets 1, 3, and 5 are interconnected using vias formed in the dielectric sheet 2 to the dielectric sheet 5, and conductive patterns formed on the dielectric sheets 2, 4, And a conductive pattern formed on the dielectric sheet 1 is formed on the lower surface of the dielectric sheet 1 through vias formed in the dielectric sheet 1, To the electronic component packaging device.
The method according to claim 1,
The inductor includes:
Wherein one end portions of the conductive patterns formed in the upper part of the dielectric sheet 1 to the dielectric sheet 4 are interconnected by using vias formed in the dielectric sheet 2 to the dielectric sheet 4.
delete The method according to claim 1,
Wherein the magnetic body inductor comprises:
One ends of the conductive patterns formed in the upper part of the dielectric sheet 3 to the dielectric sheet 6 are interconnected by using vias formed in the dielectric sheet 4 to the dielectric sheet 6,
The first and second magnetic patterns formed on the dielectric sheet 2 and the dielectric sheet 7, and the first and second magnetic material vias formed through the dielectric sheet 2 to the dielectric sheet 7, Wherein the dielectric sheet (6) has a structure of wrapping with conductive patterns interconnected via vias of the dielectric sheet (6).
The method according to claim 6,
The capacitor
Wherein the magnetic material is formed on the dielectric sheets through an LTCC, an MLCC, or a PCB process to form the first and second magnetic material vias and the first and second magnetic patterns.
The method according to claim 6,
Wherein the magnetic body inductor comprises:
And a magnetic pattern formed inside the conductive patterns formed on the upper part of the dielectric sheet (3) to the dielectric sheet (6).
The method according to claim 1,
Further comprising a dielectric pattern having a dielectric constant higher than that of the dielectric sheets surrounding a part of the conductive pattern formed on an upper portion of the dielectric sheet and a dielectric pattern capacitor surrounding a part of the dielectric pattern. Device.
10. The method of claim 9,
The dielectric pattern may be formed,
A screen printing process, an inkjet printing process, or a three-dimensional printing process.
The method according to claim 1,
Further comprising a parallel plate capacitor formed by using a conductive pattern formed on an upper portion of the dielectric sheet (8) having a high dielectric constant and a conductive pattern formed on the dielectric sheet (7) among the dielectric sheets.
The method according to claim 1,
The dielectric sheets are,
Lt; RTI ID = 0.0 > LTCC < / RTI > or MLCC or PCB process.
The method according to claim 1,
The dielectric sheets are,
Wherein the capacitor is formed of a material having a different relative dielectric constant depending on the capacity of the capacitor.
The method according to claim 1,
And a semiconductor chip mounted on the mounting region,
Wherein the conductive pattern is connected to the conductive pattern formed on the dielectric sheet through wire bonding.
The method according to claim 1,
Wherein the mounting region and the plurality of vias are electrically connected,
Wherein the dielectric sheet is formed by patterning the dielectric sheets by laser processing or mechanical punching.
The method according to claim 1,
In the mounting region,
Wherein the cushioning material is embedded after the semiconductor chip is mounted.
The method according to claim 1,
The resistance pattern
Wherein the resistance pattern is formed to overlap with the conductive patterns on the dielectric sheet on which the resistance pattern is formed.
The method according to claim 1,
Wherein,
Further comprising a solder bump or a surface mounting pad for inputting and outputting an electric signal to the lower surface.
KR1020150034640A 2015-03-12 2015-03-12 Apparatus for packaging an electronic components KR101622167B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150034640A KR101622167B1 (en) 2015-03-12 2015-03-12 Apparatus for packaging an electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150034640A KR101622167B1 (en) 2015-03-12 2015-03-12 Apparatus for packaging an electronic components

Publications (1)

Publication Number Publication Date
KR101622167B1 true KR101622167B1 (en) 2016-05-18

Family

ID=56113619

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150034640A KR101622167B1 (en) 2015-03-12 2015-03-12 Apparatus for packaging an electronic components

Country Status (1)

Country Link
KR (1) KR101622167B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149992A (en) * 2005-11-28 2007-06-14 Kyocera Corp Multilayer printed circuit board
US20100046137A1 (en) * 2008-03-13 2010-02-25 Murata Manufacturing Co., Ltd. Glass ceramic composition, glass ceramic sintered body, and multilayer ceramic electronic device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149992A (en) * 2005-11-28 2007-06-14 Kyocera Corp Multilayer printed circuit board
US20100046137A1 (en) * 2008-03-13 2010-02-25 Murata Manufacturing Co., Ltd. Glass ceramic composition, glass ceramic sintered body, and multilayer ceramic electronic device

Similar Documents

Publication Publication Date Title
CN106328339B (en) Coil component
US7239525B2 (en) Circuit board structure with embedded selectable passive components and method for fabricating the same
US7100276B2 (en) Method for fabricating wiring board provided with passive element
KR101161971B1 (en) Multi-layerd circuit board and method for fabricating thereof
KR20010108329A (en) Apparatus and method for an integrated circuit having high q reactive components
WO2011083753A1 (en) Electronic component
US10645798B2 (en) Composite component-embedded circuit board and composite component
KR20170118503A (en) Coil Electronic Component
US20040018658A1 (en) Noise shield type multi-layered substrate and munufacturing method thereof
CN109922600B (en) Circuit board structure and manufacturing method thereof
US20090008134A1 (en) Module
KR101622167B1 (en) Apparatus for packaging an electronic components
JP2005167468A (en) Electronic apparatus and semiconductor device
JP6304376B2 (en) Multi-layer board with built-in components
CN108288535B (en) Hybrid inductor
JP2002271038A (en) Composite multilayer board, its manufacturing method and electronic component
JP5207854B2 (en) Component built-in ceramic substrate and manufacturing method thereof
US20100142115A1 (en) Buried capacitor, method of manufacturing the same, and method of changing capacitance thereof
JP6707970B2 (en) IC chip mounting board
KR100900671B1 (en) Method of forming conductive via for multilayer interconnection substrate
JP2013080764A (en) Circuit module
KR20190063090A (en) Multi-layered directional coupler
JP2017038085A (en) Circuit module
JP6007485B2 (en) Component built-in wiring board and manufacturing method thereof
JP6613857B2 (en) DC-DC converter module

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20190401

Year of fee payment: 4