JP2002223077A - Multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an electric noise and a simultaneous switching noise by using a multilayer wiring board. SOLUTION: The multilayer wiring board includes a first signal wiring group 3 having a wiring length L1, a second signal wiring group 7 having a wiring length L2 and a built-in capacitor composed of power source layers or grounding layers 8, 10, 11. Here, 0.8×[(0.670/εr-0.525)×e -2x(b+t)/h}+1]1/2<=L2/L 1<=1.2×[(0.670/εr-0.525)×e -2x(b+t)/h}+1]1/2 (wherein L1>L2, t is the thickness of a signal wiring of the first signal wiring group, h is the thickness of an insulating layer between the first signal wiring group and the power source layers or grounding layers formed as opposed to the first signal wiring group, b is the thickness of an insulating coating layer, εr is a specific inductive capacity of the insulating layer and the insulating coating layer, and e is a natural logarithm) is satisfied. A plurality of the built-in capacitors each having a different resonance frequency in the range from the operation frequency band of a semiconductor element 14 to the frequency band of a higher harmonic component are connected in parallel. The synthetic impedance value in the antiresonant frequency is equal to a predetermined value or lower.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer wiring board used for a semiconductor element housing package for housing a semiconductor element or an electronic circuit board on which a semiconductor element or an electronic component is mounted. The present invention relates to a multilayer wiring board having a wiring structure suitable for housing or mounting a semiconductor element.

[0002]

2. Description of the Related Art Conventionally, microprocessors and ASICs (Appl.
In a multilayer wiring board used for an electronic circuit board or the like, on which electronic components such as a semiconductor element typified by an ication specific integrated circuit) are mounted. Insulating layers made of ceramics and wiring conductor layers made of a high melting point metal such as tungsten (W) are alternately laminated to form a multilayer wiring board.

On the other hand, as the demand for improving the information processing capability increases, as the operating speed of the semiconductor element increases and the number of simultaneous switching increases, the signal wiring among the wiring conductors for internal wiring has characteristic impedance. There has been a demand for improvements in electrical characteristics such as matching of signals and reduction of crosstalk noise between signal wirings. Therefore, in order to meet such a demand, the wiring structure of the signal wiring is a strip line structure, and a wide-area power supply layer or a ground (ground) layer is formed above and below the signal wiring via an insulating layer.

Further, with the increase in the speed of electric signals handled by the multilayer wiring board, a glass epoxy resin base material having a relatively small relative dielectric constant of 3 to 5 is used instead of an alumina ceramic having a relative dielectric constant of about 10 for an insulating layer. Is formed using an organic material such as polyimide, epoxy resin, or the like, and a conductive film for internal wiring made of copper (Cu) is formed on the insulating layer by using a thin film forming technique such as plating, vapor deposition, or sputtering. Then, a fine pattern of wiring conductors is formed by photolithography or etching, and the insulating layer and the wiring conductors are alternately laminated in multiple layers to achieve high density,
Production of a multi-layer wiring board having high performance and capable of high-speed operation of a semiconductor element is also performed.

In addition, the number of signals has been increasing with the increase in the operation speed of semiconductor devices, and the number of signal wirings has been required to increase on a multilayer wiring board on which the semiconductor elements are mounted. In contrast,
A signal wiring having a strip line structure has an advantage that it can easily form a plurality of signal wiring layers and thus can easily cope with an increase in the number of signal wirings.

As a new problem arising in such a situation, there is a time difference in input timing between electric signals input to a semiconductor element. This time difference is a difference in time required for each electric signal to pass through the signal wiring, that is, a difference in propagation delay time, and occurs because the wiring length of each signal wiring is different. If the difference in the propagation delay time increases, the input timing between the electric signals input to the semiconductor element differs, which causes a malfunction of the semiconductor element.

In order to solve such a problem, in a conventional multilayer wiring board, as shown in a plan view of FIG. 8, wiring of signal wirings of a signal wiring group 102 formed on an insulating layer 101 is performed. By making the length the same, the propagation delay time of each signal wiring is made the same, and the semiconductor element 103 to which these are connected is
A design has been made in which the input timing of an electric signal to the signal wiring is the same for each signal wiring. Specifically, the distance connecting the start point and the end point of the signal wiring is reduced by making the wiring length of the signal wiring having a short distance connecting the start point and the end point of the signal wiring a structure in which a detour portion is provided in a part of the signal wiring. A method has been adopted in which the wiring length is made equal to the long signal wiring.

Further, as a line structure for reducing the propagation delay time of the signal wiring, a signal wiring is formed on the surface of the multilayer wiring board, and a power supply layer or a ground layer is formed so as to face the signal wiring. A microstrip line structure in which air is adjacent to the air has also been adopted. This is because the propagation delay time of the signal wiring is defined by the relative dielectric constant of the insulating material adjacent to the signal wiring. This is to reduce the dielectric constant and the propagation delay time.

However, in the microstrip line structure, since air is adjacent to the signal wiring, the signal wiring is easily oxidized with time, and the conduction resistance is increased.
There was a problem that desired electrical characteristics could not be obtained.
In order to solve this problem, a buried type microstrip line structure in which a signal wiring in the microstrip line structure is covered with an insulating material has been used. Even with this structure, the effective relative permittivity can be reduced as compared with the strip line structure, so that the propagation delay time of the signal wiring can be reduced.

On the other hand, a problem of simultaneous switching noise has arisen as a problem concerning power supply to a semiconductor element. This is because the power supply voltage required for switching the semiconductor element is supplied from the outside of the semiconductor element through the power layer and the ground layer, so that noise is generated due to the inductance component of the power layer or the ground layer of the multilayer wiring board. It is. Specifically, a transient current generated at the time of switching of a semiconductor element flows into a power supply layer or a ground layer in the multilayer wiring board, and a voltage variation occurs due to an inductance component of the power supply layer or the ground layer, which becomes noise and causes a semiconductor element. May cause malfunctions.

In order to solve such a problem, a method of incorporating a capacitor in which a power supply layer and a ground layer having a large area are opposed to each other via an insulating layer in a multilayer wiring board has been used. By forming the power supply layer and the ground layer having a large area so as to face each other, a capacitor having a large capacitance value of several nF can be built in the multilayer wiring board,
Since the impedance value of the built-in capacitor becomes small, it is possible to reduce simultaneous switching noise. Here, the impedance value is proportional to the square root of the inductance value, and is inversely proportional to the square root of the capacitance value. In general, it is known that simultaneous switching noise is reduced when the impedance value of the built-in capacitor is reduced. Further, in order to obtain a larger capacitance value, a plurality of capacitors are formed in a multilayer wiring board.

[0012]

However, as the information processing capability is required to be further improved, the operating speed of the semiconductor device exceeds 1 GHz and the number of simultaneous switching of the semiconductor device is rapidly increased. On the other hand, in the multilayer wiring board having the conventional structure, the distance connecting the start point and the end point of the signal wiring is short, the wiring length of the signal wiring is changed to a structure in which a detour portion is provided in a part of the signal wiring. By adopting a configuration in which the distance connecting the start point and the end point of the signal wiring is made equal to the wiring length of the signal wiring, the wiring length of the signal wiring having a short wiring length becomes unnecessarily long. as a result,
In proportion to the wiring length of the signal wiring, the electromagnetic coupling between the signal wirings and between the signal wiring and the power supply layer or the ground layer, that is, the capacitance and the inductance of the signal wirings increase, and electric noise such as signal noise and crosstalk noise increases. There is a problem that noise increases and a malfunction of the semiconductor element is caused.

Further, in order to make the wiring length uniform, a detour is provided at a part of the signal wiring which is short in a distance connecting the start point and the end point of the signal wiring. Has also been problematic.

Further, when the signal wiring is of a buried type microstrip line structure, since the signal wiring is formed on the surface of the insulating substrate, it is difficult to form a plurality of signal wiring layers. There was a problem that it was not possible to easily cope with an increase in the number of signal wirings.

It has been found that in order to reduce simultaneous switching noise, it is necessary to reduce the impedance value even in a frequency band up to about five times the operating frequency of the semiconductor device.

The transient current generated at the time of switching of the semiconductor element contains various harmonic components in addition to the operating frequency of the semiconductor element. Need to be considered.

The harmonic component is generally an nth-order (n is an integer of 2 or more) frequency component when the operating frequency of the semiconductor element is a fundamental wave. Is reduced. It is known that this harmonic component has a large component especially up to about five times the operating frequency. In order to reduce simultaneous switching noise, it is necessary to consider this harmonic component.

At this time, since the conventional multilayer wiring board has a structure in which a plurality of built-in capacitors having a single capacitance value are formed, the resonance frequency of the impedance characteristic of the built-in capacitor is changed to the operating frequency of the semiconductor element. By setting it near, the impedance value near the operating frequency could be reduced, but no consideration was given to the impedance value in the frequency band corresponding to higher-order harmonic components. Therefore, simultaneous switching noise can be reduced in a region where the operating frequency of the semiconductor element is low, but in a high frequency region where the operating frequency is several GHz or more, the impedance value of the built-in capacitor increases, and the simultaneous switching noise increases. Had problems.

Also, due to the parasitic inductance component contained in the multilayer wiring board, an anti-resonance frequency other than the self-resonance frequency is generated in the built-in capacitor, and EMI (Electro Magnetic Interference) noise at that frequency is increased. I also know that there are points.

The present invention has been completed to solve the above problems, and an object of the present invention is to reduce the electrical noise of signal wiring while making the propagation delay time of each signal wiring substantially the same, and to reduce the number of signal wiring. Provided is a multilayer wiring board suitable for an electronic circuit board or the like on which electronic components such as a semiconductor element operating at a high speed can be increased and the simultaneous switching noise and the EMI noise can be reduced. It is in.

[0021]

According to the present invention, there is provided a multilayer wiring board comprising a semiconductor element mounted on an upper surface thereof and a plurality of insulating layers laminated thereon, and a first wiring length provided on a surface of the insulating substrate. A first signal line group formed by forming a plurality of signal lines having L1, a power supply layer or a ground layer formed to face the first signal line group with the insulating layer interposed therebetween, and the first signal line A microstrip line portion composed of an insulating coating layer covering the group, a second signal wiring group formed by forming a plurality of signal wirings having a second wiring length L2 inside the insulating substrate, and the insulating layer. A strip line portion composed of a power supply layer or a ground layer formed above and below the second signal wiring group with the power signal layer and the ground layer inside the insulating substrate; Sandwiched and opposed A multilayer wiring board and a built-in capacitor is formed by the first wiring length L1 and the second wiring length L2 is, 0.8 × [(0.670 / εr
−0.525) × e ^{{−2 × (b + t) / h}} +1] ^1/2 ≦ L2 / L1 ≦
1.2 × [(0.670 / εr−0.525) × e ^{{-2 × (b + t) / h}} +
1] ^1/2 (where L1> L2, t is the thickness of the signal wiring of the first signal wiring group, and h is a power supply layer formed to face the first signal wiring group and the first signal wiring group. Or b is the thickness of the insulating coating layer, εr is the relative permittivity of the insulating layer and the insulating coating layer, and e is the natural logarithm). A composite impedance value at an anti-resonance frequency formed between a plurality of devices having different resonance frequencies in parallel in a range from the operating frequency band of the semiconductor element to the harmonic component frequency band, and generated between the different resonance frequencies Is less than or equal to a predetermined value.

According to the multilayer wiring board of the present invention, an insulating substrate having a semiconductor element mounted on the upper surface and a plurality of insulating layers laminated thereon, and a first wiring length L1 on the surface of the insulating substrate.
Covering a power supply layer or a ground layer and a first signal wiring group formed to face the first signal wiring group with a plurality of signal wirings each having A second signal line group formed by forming a plurality of signal lines having a second line length L2 inside the insulating substrate, and a second signal line via the insulating layer; With a structure including a power supply layer or a strip line portion formed of a ground layer formed above and below the wiring group, the wiring length of each signal wiring for each of the first and second signal wiring groups And the propagation delay time is proportional to the wiring length of the signal wiring, so that the propagation delay time of each signal wiring in the first and second signal wiring groups is substantially the same for each signal wiring group.

Further, the first signal wiring group has a buried type microstrip line structure, and the second signal wiring group has a strip line structure, each of which has a power supply layer or connection formed facing each signal wiring group. The presence of the underlayer blocks electromagnetic interference between the first and second signal wiring groups. Therefore, the propagation delay time Tpdl of the signal wiring for each of the first and second signal wiring groups is determined by the wiring length L of the signal wiring of each signal wiring group, the insulating layer in which each signal wiring group is formed, and air. Tpdl = ｛(εreff) ^1/2 / using the effective relative permittivity εreff defined by the relative permittivity of
It can be easily set from c｝ × L (c is the speed of light).

Further, the relative dielectric constant of the insulating layer in which the first and second signal wiring groups are formed and the ratio of each wiring length are set to the relationship shown in the above equation, so that the first wiring having different wiring lengths is obtained. In addition, the propagation delay time of the second signal wiring group can be made substantially the same within a range of ± 20%, which is a range in which a malfunction of the semiconductor element hardly occurs.

Further, since the relative permittivity of the insulating layer is substantially the same in the insulating substrate, the wiring length L2 of the signal wiring of the second signal wiring group having the strip line structure is determined by the above equation from the buried type micro wiring. The length is set shorter than the wiring length L1 of the signal wiring of the first signal wiring group having the strip line structure. From this, particularly in the second signal wiring group, it is possible to avoid that the wiring length of the signal wiring becomes unnecessarily long, so that electromagnetic coupling between the signal wirings and between the signal wiring and the power supply layer or the ground layer, that is, The capacitance and inductance of the signal wiring can be reduced, and electric noise such as signal noise and crosstalk noise can be reduced.

In addition, since it is possible to avoid an unnecessary increase in the wiring length of the signal wiring, particularly in the second signal wiring group, the wiring area of other signal wirings can be increased, and the wiring flexibility can be improved. .

Furthermore, since the buried type microstrip line structure and the strip line structure are provided, a plurality of signal wiring layers of the strip line structure can be easily formed, so that the number of signals of the semiconductor element can be increased. Thus, the number of signal wirings can be easily increased.

Further, according to the multilayer wiring board of the present invention, there is provided a built-in capacitor in which the power supply layer and the ground layer are arranged opposite to each other with the insulating layer interposed therebetween inside the insulating substrate. Since a plurality of devices having different resonance frequencies in a range from the operating frequency band of the element to the frequency band of the harmonic component are formed so as to be connected in parallel, the resonance frequency having the lowest impedance value is determined for each built-in capacitor in each semiconductor. It can be set to be dispersed within the frequency band of the harmonic component from the operating frequency of the element, and the combined impedance value at the anti-resonance frequency generated between different resonance frequencies is set to a predetermined value or less. The combined impedance value in the range from the operating frequency to the harmonic component frequency band is reduced over a wide frequency band. Rukoto can.

When the combined impedance value at the anti-resonance frequency is 1 Ω or less, the inductance components of the power supply layer and the ground layer become small, and even in the high frequency region where the operating frequency of the semiconductor element is several GHz or more, the harmonic component thereof becomes high. , It is possible to reduce simultaneous switching noise including the above frequency band.

Further, since the power supply layer and the ground layer have a large area and a built-in capacitor having a large capacitance value of several nF can be formed, simultaneous switching noise can be reduced even in a frequency band where the operating frequency of the semiconductor element is as low as several MHz. It becomes possible to reduce.

Further, by controlling the capacitance values of the plurality of built-in capacitors, the anti-resonance frequency included in the impedance characteristics of the built-in capacitors can be set to a frequency that does not match the frequency of the harmonic component included in the electric signal. EMI noise can also be reduced.

Further, the wiring length of the signal wiring is shortened, and since the voltage of the power supply layer and the grounding layer is stabilized by having the built-in capacitor, the electromagnetic coupling between the signal wirings is reduced, and the effect is further improved. Thus, the electrical noise and the crosstalk noise of the signal wiring can be reduced.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention. FIG. 2 is a plan view showing an example of each wiring layer in the multilayer wiring board of the present invention.
(E) is a plan view of each wiring layer formed on the upper surface of the insulating layers 2a to 2e, and (f1) and (f2) are plan views of the upper surface and the lower surface of the insulating layer 2f.

In this figure, 1 is a multilayer wiring board, 2 is an insulating board, and the insulating board 2 has a plurality of insulating layers 2a to 2f.
Are laminated. Also, the insulating layers 2a to 2f
The insulating coating layer 6 is made of an insulating material having the same relative dielectric constant. The first signal wiring group 3 is formed on the insulating layer 2a.
Is formed, and a large-area power supply layer or ground layer 4 is formed on the insulating layer 2b so as to face the first signal wiring group 3, and the first signal wiring group 3 is formed by an insulating coating layer 6. The first signal wiring group 3, which is covered, forms a microstrip line section 5 having a buried type microstrip line structure. On the insulating layer 2c, a second signal wiring group 7 is formed, and on the insulating layers 2b, 2d, a large-area power supply layer or ground layer 4, 8 facing the second signal wiring group 7 is formed. Are formed, and the second signal wiring group 7 constitutes a strip line section 9 having a strip line structure.

The first and second signal wiring groups 3, 7
May have different signal transmissions.

In this example, a semiconductor element 14 such as a microprocessor or an ASIC is mounted on the upper surface of the multilayer wiring board 1, and a conductor bump 15 and a semiconductor element 14 made of solder such as tin (Sn) -lead (Pb) are provided. It is electrically connected to the multilayer wiring board 1 through the connection electrode 13 for connecting the semiconductor element. On the surface (lower surface) of the multilayer wiring substrate 1 opposite to the surface on which the semiconductor element 14 is mounted, external electrodes 12 for electrically connecting to another wiring substrate are formed.

As shown in FIG. 2, the wiring lengths of the signal wirings of the first signal wiring group 3 and the second signal wiring group 7 are substantially the same for each signal wiring group. .

In general, the propagation delay time Tpd per unit wiring length of signal wiring is Tpd = (εreff) ^1/2 / c (εref
f is the effective relative permittivity defined by the relative permittivity of the insulating layer on which the signal wiring is provided and the air, and c is the speed of light). That is, the propagation delay time Tpd per unit wiring length of the signal wiring is proportional to the square root (1/2) of the effective relative permittivity refreff.
In a signal wiring having a large reff, the propagation delay time Tpd per unit wiring length of the signal wiring becomes large. On the contrary, in a signal wiring having a small effective relative permittivity εreff, the propagation delay per unit wiring length of the signal wiring becomes large. The time Tpd becomes smaller.

Here, the effective relative dielectric constant εreff in the buried type microstrip line structure is expressed as εreff = ( 0.670−0.525εr) × e ^{{-2 ×
(b + t) / h}} + εr (t is the wiring thickness of the signal wiring of the signal wiring group, and h is the thickness of the insulating layer between the signal wiring group and the power supply layer or the ground layer formed opposite to the signal wiring group. The thickness, b is the thickness of the insulating coating layer covering the signal wiring group), and the effective relative permittivity εre in the strip line structure.
ff is the relative dielectric constant of the insulating layer on which the signal wiring is formed, because the power supply layer or the ground layer formed above and below the signal wiring blocks the influence of the relative dielectric constant of the insulating coating layer and air. Ratio εr, and εreff = εr
It is.

From this, the effective relative dielectric constant εreff of the buried type microstrip line structure is smaller than the effective relative dielectric constant εreff of the stripline structure, so that the propagation delay time Tpd per unit wiring length of the signal wiring is buried. The stripline structure is larger than the microstrip line structure of the type.

In this embodiment, the line structure of the first signal wiring group 3 is a buried microstrip line structure, and the line structure of the second signal wiring group 6 is a strip line structure. The propagation delay time Tpd2 per unit wiring length of the signal wiring of the second signal wiring group 7 is larger than the propagation delay time Tpd1 per unit wiring length of the signal wiring of the wiring group 3. Accordingly, even if the wiring length L2 of the signal wiring of the second signal wiring group 7 is shorter than the wiring length L1 of the signal wiring of the first signal wiring group 3, the propagation delay time of the signal wiring is substantially the same. Can be

Next, the set value of the relative dielectric constant of the insulating layer is calculated to make the propagation delay time of the signal wiring of the buried type microstrip line structure equal to the propagation delay time of the signal wiring of the strip line structure. The method will be described.

The propagation delay time Tpdl of the signal wiring is given by Tpdl =
{(Εreff) ^1/2 / c} × L (where εreff is the effective relative permittivity defined by the relative permittivity of the insulating layer and the insulating coating layer on which the signal wiring is provided and the relative permittivity of air, c is the speed of light, and L is The propagation delay time Tpdl1 of the signal wiring of the first signal wiring group 3 having the buried type microstrip line structure is represented by Tpdl1 =
[[(0.670−0.525εr) × e ^{{−2 × (b + t) / h}} + εr] ^1/2 /
c] × L1 (c is the speed of light). Similarly, assuming that the second wiring length is L2, the propagation delay time Tpdl2 of the signal wiring of the second signal wiring group 7 having the stripline structure is Tpdl2 = Tpdl2 = ｛(ε
r) ^1/2 / c｝ × L2 (c is the speed of light).

Here, since the propagation delay times of the respective signal wiring groups 3 and 7 are made equal, when the equation is solved with Tpdl1 = Tpdl2, L2 / L1 = [(0.670 / εr−0.525)
× e ^{{ −2 × (b + t) / h}} +1] ^1/2 (where L1> L2) is obtained. Also, ± 20%, which is the range where the semiconductor element can be operated accurately and stably without causing malfunction.
, The relative dielectric constant εr of the insulating layer and the insulating coating layer, the wiring length L1 of the signal wiring of the first signal wiring group 3, and the wiring length L2 of the signal wiring of the second signal wiring group 7 so that the propagation delay time difference
Can be defined by the following equation.

0.8 × [(0.670 / εr−0.525) × e ^{{−2 ×
(b + t) / h}} +1] ^1/2 ≦ L2 / L1 ≦ 1.2 × [(0.670 / εr
−0.525) × e ^{{−2 × (b + t) / h}} +1] ^1/2 (L1
> L2) When L2 / L1 is out of the above range, the semiconductor element is likely to malfunction.

Preferably, the following formula: 0.9 × [(0.670 / εr−0.525) × e ^{{−2 × (b + t) / h}} +
1] ^1/2 ≦ L2 / L1 ≦ 1.1 × [(0.670 / εr−0.525)
× e ^{{−2 × (b + t) / h}} +1] ^1/2 (where L1> L2), as far as the difference in the propagation delay time is ± 10%, as far as possible. Since the propagation delay times of the signal wirings can be made the same, it is possible to cope with a further increase in the operating speed of the semiconductor element.

When the first and second signal wiring groups 3 and 7 satisfy the above equation, the propagation delay times of the first and second signal wiring groups 3 and 7 can be made substantially the same. Not only that, since it is possible to avoid an unnecessary increase in the wiring length of the signal wiring particularly in the second signal wiring group 7, electromagnetic coupling between the signal wirings and between the signal wiring and the power supply layer or the ground layer can be prevented. That is, the capacitance and inductance of the signal wiring can be reduced, and electric noise such as signal noise and crosstalk noise can be reduced.

Further, in this embodiment, the power supply or ground layers 8, 10, and 11 having a large area allow two layers in the multilayer wiring board.
The number of built-in capacitors is formed.

At this time, the power supply layer or the ground layer 8, 10,.
11 makes layers of different functions alternately overlap. In other words, when 8 and 11 are power supply layers, 10 is a ground layer and 8, 11
When is a ground layer, 10 is a power supply layer.

Here, the built-in capacitor will be described in detail with reference to FIGS.

FIG. 6A is a sectional view of an essential part showing an example of an embodiment of a multilayer wiring board according to the present invention. In FIG. 6, ground layers 4 and 10 in FIG. Is the case. 6A, the power supply layers 63 and 65 correspond to the power supply layers or the ground layers 8 and 11 shown in FIG. The ground layers 70 and 72 correspond to the power supply layer or the ground layers 4 and 10 shown in FIG.

In FIG. 6A, the power supply wiring is an external electrode.
From 61, it is connected to a power supply layer 63 through a via hole 62, connected to a power supply layer 65 through a via hole 64, and connected to a semiconductor element connection electrode 67 through a via hole 66. The ground wiring is connected from the external electrode 68 to the ground layer 70 through the via hole 69, is connected to the ground layer 72 through the via hole 71, and is connected to the semiconductor element connection electrode 74 through the via hole 73. By these,
Since a first built-in capacitor is formed between the power supply layer 63 and the ground layer 70 and a second built-in capacitor is formed between the power supply layer 65 and the ground layer 70, these electric circuits are illustrated in FIG. This can be represented by an electric circuit diagram shown in FIG. FIG.
As can be seen from (b), the two built-in capacitors are connected in parallel.

FIG. 7 is a sectional view of an essential part showing an example of an embodiment of the multilayer wiring board of the present invention. In FIG. 1, the power supply layers 4 and 10 and the ground layers 8 and 11 are used. It is. In FIG. 7, ground layers 90 and 92 correspond to the power supply layers or ground layers 8 and 11 shown in FIG. Also,
The power supply layers 83 and 85 correspond to the power supply layers 4 and 10 shown in FIG.

In FIG. 7, the ground wiring is connected from the external electrode 88 to the ground layer 90 through the via hole 89,
Connected to ground layer 92 through 91 and via hole
It is connected to a semiconductor element connection electrode 94 through 93.
The power supply wiring is connected from the external electrode 81 to the power supply layer 83 through the via hole 82, is connected to the power supply layer 85 through the via hole 84, and is connected to the semiconductor element connection electrode 87 through the via hole 86. Thereby, the ground layer 90
And a first built-in capacitor is formed between the power supply layer 83 and
A second built-in capacitor is formed between the ground layer 92 and the power supply layer 83, and these electric circuits can be represented by an electric circuit diagram similar to FIG. 6B. Therefore, also in this case, the two built-in capacitors are connected in parallel.

In the example shown in FIG. 1, the thickness of the insulating layer 2e having the power supply layer or the ground layer 10 formed on the upper surface is larger than the thickness of the insulating layer 2d having the power supply layer or the ground layer 8 formed on the upper surface. It is set large. Thereby, the first built-in capacitor formed between the power supply layer or the ground layer 10 and the power supply layer or the ground layer 11, and the first built-in capacitor formed between the power supply layer or the ground layer 8 and the power supply layer or the ground layer 10 The capacitance value of the second built-in capacitor is different from that of the second built-in capacitor, and as shown in FIG. 3, each built-in capacitor has an impedance characteristic including a different resonance frequency.

FIG. 3 is a diagram showing an example of the impedance characteristic of the built-in capacitor in the multilayer wiring board of the present invention. In FIG. 3, the horizontal axis represents the frequency, and the vertical axis represents the impedance value of the built-in capacitor. Here, in the built-in capacitor formed in the multilayer wiring board 1,
An impedance characteristic in a region lower in frequency than the resonance frequency tends to show a capacitance component, and an impedance characteristic in a region higher in frequency than the resonance frequency tends to show an inductance component. Further, when a plurality of capacitors having different resonance frequencies are formed in parallel, the resonance frequencies of the respective built-in capacitors remain unchanged.
The impedance characteristics are synthesized at the intersection (anti-resonance point) of the impedance characteristics, and the frequency at the anti-resonance point, that is, the anti-resonance frequency is the frequency at which the respective impedance characteristics intersect.

Simultaneous switching noise can be reduced as the impedance value of the built-in capacitor formed by the power supply layer or the ground layers 8, 10, and 11 having a large area becomes smaller. In particular, when the operating frequency of the semiconductor element 14 is several GH
In a high frequency region of z or more, a harmonic component having a large component at a frequency that is an integral multiple of the operating frequency is included,
In particular, a semiconductor element that operates at high speed by reducing the impedance value in a frequency region including a frequency band up to about five times the operating frequency of the semiconductor element 14 in which the harmonic component becomes large.
It is possible to reduce 14 simultaneous switching noises.

Here, the impedance value of the built-in capacitor becomes the smallest at the resonance frequency. According to the multilayer wiring board of the present invention, by forming a plurality of built-in capacitors having different resonance frequencies in parallel, the resonance frequency of each built-in capacitor can be changed from the operating frequency band of the semiconductor element 14 to the frequency band of the harmonic component. Can be set arbitrarily in the range between. In the example shown in FIG. 3, the resonance frequency included in the impedance characteristics of the first built-in capacitor is adjusted to the operating frequency band of the semiconductor element 14, and the resonance frequency included in the impedance characteristics of the second built-in capacitor is adjusted to the frequency of the harmonic component. Match the band. The resonance frequency included in the impedance characteristics of the built-in capacitor can be arbitrarily set by changing the capacitance value of the built-in capacitor formed by the power supply layer or the ground layers 8, 10, and 11. In this example, the capacitance value of the built-in capacitor is changed by changing the thickness of the insulating layer 2d or 2e on which the power supply layer or the ground layer 8, 10 is formed, and the resonance frequency included in the impedance characteristic of the built-in capacitor is changed to a desired value. Is set to a value. In this example, the thickness of the insulating layer 2e on which the first built-in capacitor is formed is the same as the thickness of the insulating layer 2d on which the second built-in capacitor is formed.
1.5 times the thickness of

Further, since the combined impedance value at the anti-resonance frequency generated between these resonance frequencies is set to a predetermined value or less, the combined impedance value in the range from the operating frequency band of the semiconductor element 14 to the frequency band of the harmonic component is reduced. It can be reduced over a wide frequency band. Here, the combined impedance value at the anti-co-frequency generated between the resonance frequencies included in the impedance characteristics of the plurality of built-in capacitors can be arbitrarily set according to the capacitance value of each built-in capacitor and the number of the built-in capacitors. It is. The predetermined value of the combined impedance value in the multilayer wiring board of the present invention is appropriately set so as to satisfy the required characteristics from the operating frequency of the semiconductor element 14 and the required amount of simultaneous switching noise.

Further, by setting the combined impedance value at the anti-resonance frequency to 1 Ω or less, the inductance component of the power supply layer or the ground layers 8, 10, 11 can be extremely reduced, and the operating frequency of the semiconductor element 14 becomes several GHz.
It is possible to sufficiently effectively reduce simultaneous switching noise even in a high frequency region of z or more. Here, the effective operating frequency of the semiconductor element 14 for which the combined impedance value is 1 Ω or less is about 1 to 10 GHz, and the frequency of the harmonic component at that time is converted to five times the operating frequency of the semiconductor element 14. It is about 5 to 50 GHz.

Note that the anti-resonance frequency included in the impedance characteristics of the built-in capacitor formed by the power supply layer or the ground layers 8, 10, and 11 formed in the multilayer wiring board 1 depends on the operating frequency of the semiconductor element 14 and its harmonics. When the components match, the EMI noise tends to increase. Therefore, it is preferable to set the anti-resonance frequency of the impedance characteristic of the built-in capacitor to a frequency that does not match the operating frequency of the semiconductor element 14.

Next, another example of the embodiment of the multilayer wiring board of the present invention will be described with reference to FIGS.

FIG. 4 is a sectional view similar to FIG. In FIG. 4, 21 is a multilayer wiring board, 22 is an insulating substrate, and the insulating substrate 22 is formed by laminating a plurality of insulating layers 22a to 22f. The insulating layers 22a to 22f and the insulating coating layer 26 are made of an insulating material having the same relative dielectric constant. A first signal wiring group 23 is formed on the insulating layer 22a, and a wide-area power supply layer or ground layer 24 is formed on the insulating layer 22b so as to face the first signal wiring group 23. Indicates that the first signal wiring group 23 is covered with the insulating coating layer 26,
The first signal wiring group 23 constitutes a microstrip line section 25 having a buried type microstrip line structure. On the insulating layer 22c, a second signal wiring group 27 is formed. On the insulating layers 22b, 22d, a large-area power supply layer or ground layer 24, facing the second signal wiring group 27, is formed.
The second signal wiring group 27 constitutes a strip line section 29 having a strip line structure.

The first and second signal wiring groups 23 and 27
May have different signal transmissions.

The wiring lengths of the signal wirings of the first signal wiring group 23 and the second signal wiring group 27 have substantially the same wiring length for each signal wiring group.

In this example, the semiconductor element 34 is mounted on the upper surface of the multilayer wiring board 21, and the conductor bump 35 and the semiconductor element 34
The semiconductor device is electrically connected to the multilayer wiring board 21 via a semiconductor element connection electrode 33 for connection. Further, the semiconductor element 34
External electrodes 32 for wiring board connection are formed on the surface of the multilayer wiring board 21 on the side opposite to the surface on which is mounted.

The power supply layers or ground layers 30 and 31 are the same as the power supply layers or ground layers 28 having a large area. In this example, the power supply layers or ground layers 28, 30 and 31 form a multilayer wiring board. Two built-in capacitors are formed in parallel in 21.

At this time, the power supply layer or the ground layer 28, 30,
31 makes layers of different functions alternately overlap. That is, the power supply layers 28 and 31 are the ground layers 30 and the ground layers 28 and 31
In this case, the power supply layer 30 is used.

In this example, the power supply layer or ground layer 28, 30 is a wide area wiring having substantially the same area, and the power supply layer or ground layer 31 is a large area having a smaller area than the power supply layer or ground layer 28. It is formed by wiring. This allows
A first built-in capacitor is formed between the power supply or ground layer 30 and the power supply or ground layer 31, and a second built-in capacitor is formed between the power supply or ground layer 28 and the power supply or ground layer 30. Will be done. Each of the built-in capacitors has a different capacitance value because the opposing areas of the power supply layer and the ground layer are different, and each built-in capacitor has an impedance characteristic including a different resonance frequency.

In this example, the resonance frequency included in the impedance characteristics of the first built-in capacitor is adjusted to the operating frequency band of the semiconductor element 34, and the resonance frequency included in the impedance characteristics of the second built-in capacitor is adjusted to the frequency of the harmonic component. Match the band. The resonance frequency included in the impedance characteristics of the built-in capacitor can be arbitrarily set by changing the capacitance value of the built-in capacitor formed by the power supply layer or the ground layers 28, 30, and 31. In this example, the capacitance value of the built-in capacitor is changed by changing the area of the wide area wiring of the power supply layer or the ground layer 31, and the resonance frequency included in the impedance characteristic of the built-in capacitor is set to a desired value.

Further, by setting the combined impedance value at the anti-resonance frequency generated between these resonance frequencies to a predetermined value or less, the combined impedance value in the frequency band of the harmonic component from the operating frequency of the semiconductor element 34 is widened. I'm making it smaller. In particular, by setting the combined impedance value at the anti-resonance frequency to 1 Ω or less, the inductance component of the power supply layer or the ground layers 28, 30, and 31 can be extremely reduced, and the operating frequency of the semiconductor element 34 becomes higher than several GHz. Even in the region, it is possible to sufficiently reduce simultaneous switching noise.

With such a structure, the set frequency range of the resonance frequency included in the impedance characteristics can be made wider than in the case where a plurality of built-in capacitors having different resonance frequencies are formed by changing the thickness of the insulating layer. It can be easily handled by increasing the operating frequency of the semiconductor element 34.

In this example, the power supply layer or the ground layer 28 is used.
Although the area of the wide area wiring layer of the power supply layer or the ground layer 31 is reduced, the area of the wide area wiring layer of the power layer or the ground layer 28 is reduced with respect to the power layer or the ground layer 31. Similar effects can be obtained.

Next, another example of the embodiment of the multilayer wiring board of the present invention shown in FIG. 5 will be described.

FIG. 5 is a sectional view similar to FIG. In FIG. 5, 41 is a multilayer wiring board, 42 is an insulating substrate, and the insulating substrate 42 is formed by laminating a plurality of insulating layers 42a to 42f. The insulating layers 42a to 42d and 42f and the insulating coating layer
Reference numeral 46 denotes an insulating material having the same relative dielectric constant.
A first signal wiring group 43 is formed on the insulating layer 42a, and a wide-area power supply layer or ground layer 44 is formed on the insulating layer 42b so as to face the first signal wiring group 43. The first signal wiring group 43 is covered with an insulating coating layer 46,
The first signal wiring group 43 constitutes a microstrip line section 45 having a buried type microstrip line structure. On the insulating layer 42c, a second signal wiring group 47 is formed. On the insulating layers 42b, 42d, the wide area power supply layers or ground layers 44, 48 are opposed to the second signal wiring group 47.
Are formed, and the second signal wiring group 47 constitutes a strip line section 49 having a strip line structure.

The first and second signal wiring groups 43 and 47
May have different signal transmissions.

The wiring lengths of the signal wirings of the first signal wiring group 43 and the second signal wiring group 47 have substantially the same wiring length for each signal wiring group.

A semiconductor element 54 is mounted on the upper surface of the multilayer wiring board 41, and is electrically connected to the multilayer wiring board 41 via the conductor bumps 55 and the semiconductor element connecting electrodes 53 for connecting the semiconductor element 54. I have. Further, an external electrode 52 for connecting the wiring board is formed on the surface of the multilayer wiring board 41 opposite to the surface on which the semiconductor element 54 is mounted.

The power supply layers or ground layers 50 and 51 are the same as the power supply layers or ground layers 48 having a large area. In this example, the power supply layers or ground layers 48, 50 and 51 form the multilayer wiring board 41. Inside, two built-in capacitors are formed in parallel.

At this time, the power supply layer or the ground layer 48, 50,
51 makes layers of different functions alternately overlap. That is, the power supply layers 48 and 51 are the ground layers 50, and the ground layers 48 and 51
In this case, the power supply layer 50 is used.

In this example, the insulating layer 42e having the power supply layer or the ground layer 50 formed on the upper surface is made of an insulating material having a higher relative dielectric constant than the insulating layer 42d having the power supply layer or the ground layer 48 formed on the upper surface. Is formed. Thereby, the first built-in capacitor formed between the power supply layer or the ground layer 50 and the power supply layer or the ground layer 51, and the first built-in capacitor formed between the power supply layer or the ground layer 48 and the power supply layer or the ground layer 50 The capacitance value of the second built-in capacitor is different from that of the second built-in capacitor, and each built-in capacitor has an impedance characteristic including a different resonance frequency.

In this example, the resonance frequency included in the impedance characteristics of the first built-in capacitor is adjusted to the operating frequency band of the semiconductor element 54, and the resonance frequency included in the impedance characteristics of the second built-in capacitor is adjusted to the frequency of the harmonic component. Match the band. The resonance frequency included in the impedance characteristics of the built-in capacitor can be arbitrarily set by changing the capacitance value of the built-in capacitor formed by the power supply layer or the ground layers 48, 50, and 51. In this example, the capacitance value of the built-in capacitor is changed by changing the relative permittivity of the insulating layers 42d and 42e on which the power supply layer or the ground layers 48 and 50 are formed, and the resonance frequency included in the impedance characteristic of the built-in capacitor is changed. It is set to the desired value.

Further, by setting the combined impedance value at the anti-resonance frequency generated between these resonance frequencies to a predetermined value or less, the combined impedance value in the frequency band from the operating frequency of the semiconductor element 54 to the harmonic component is widened. I'm making it smaller. In particular, by setting the combined impedance value at the anti-resonance frequency to 1Ω or less, the inductance component of the power supply layer or the ground layers 48, 50, and 51 can be extremely reduced, and the operating frequency of the semiconductor element 54 becomes higher than several GHz. Even in the region, it is possible to sufficiently reduce simultaneous switching noise.

With such a structure, the capacitance value of the built-in capacitor can be further increased, so that the impedance value can be further reduced.

In this example, the relative permittivity of the insulating layer 42e is larger than the relative permittivity of the insulating layer 42d. However, the relative permittivity of the insulating layer 42d may be larger than the relative permittivity of the insulating layer 42e. Similar effects can be obtained.

In the multilayer wiring board of the present invention, a similar wiring structure may be further laminated in multiple layers to form a multilayer wiring board.

The structure of the signal wiring may be a coplanar structure in which a power supply layer or a ground layer is formed adjacent to the signal wiring, and may be appropriately selected and used according to specifications required for a multilayer wiring board. be able to.

Further, a multilayer wiring board may be constructed by attaching a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor or an electrolytic capacitor, or the like.

The shape of each insulating layer in plan view is as follows:
The shape may be a square, a rectangle, a diamond, a hexagon, an octagon, or the like.

The multilayer wiring board of the present invention can be used as a package for storing electronic parts such as a package for storing semiconductor elements, a substrate for mounting electronic parts, a so-called multichip module or multichip on which a large number of semiconductor elements are mounted. Used as a package or motherboard.

In the multilayer wiring board of the present invention, each insulating layer is formed by, for example, a ceramic green sheet laminating method.
Using an inorganic insulating material such as aluminum oxide sintered body, aluminum nitride sintered body, silicon carbide sintered body, silicon nitride sintered body, mullite sintered body or glass ceramics, or polyimide, epoxy Electricity such as a composite insulating material using an organic insulating material such as resin, fluororesin, polynorbornene or benzocyclobutene, or combining an inorganic insulating powder such as a ceramic powder with a thermosetting resin such as an epoxy resin. It is formed using an insulating material.

These insulating layers are manufactured as follows. For example, in the case of a sintered body of aluminum oxide, first, an appropriate organic binder, a solvent and the like are added to and mixed with a raw material powder such as aluminum oxide, silicon oxide, calcium oxide or magnesium oxide to form a slurry. This is formed into a sheet by employing a conventionally known doctor blade method to obtain a ceramic green sheet. Then, a metal paste to be used for each signal wiring group and each wiring conductor layer is printed and applied in a predetermined pattern, and is laminated on top and bottom. Finally, the laminated body is fired at a temperature of about 1600 ° C. in a reducing atmosphere. Is done.

In the case of an epoxy resin, for example, an insulating layer of a glass epoxy resin or the like formed by impregnating a ceramic or a glass fiber woven cloth with an epoxy resin in general, which is made of an aluminum oxide sintered body. An insulating layer made of an organic resin such as an epoxy resin formed by applying an organic resin precursor by a coating technique such as a spin coating method or a curtain coating method and performing a thermosetting treatment on the upper surface thereof, and copper. It is manufactured by alternately laminating thin film wiring conductor layers formed by adopting thin film forming technology such as electroless plating method and vapor deposition method and photolithography technology, and heating and curing at a temperature of about 170 ° C. .

The thickness of these insulating layers is appropriately set according to the characteristics of the material to be used, so as to satisfy conditions such as mechanical strength and electrical characteristics corresponding to required specifications.

As a method for obtaining insulating layers having different relative dielectric constants, for example, an inorganic insulating material such as aluminum oxide, aluminum nitride, silicon carbide, silicon nitride, mullite or glass ceramics, or a polyimide or epoxy resin Add powder of high dielectric material such as barium titanate, strontium titanate, calcium titanate or magnesium titanate to organic insulating material such as PTFE, fluororesin, polynorbornene or benzocyclobutene, and heat and cure at appropriate temperature By doing so, a material having a desired relative permittivity may be obtained.

At this time, the particle diameter of the high dielectric material to be added to and mixed with the inorganic insulating material or the organic insulating material is determined by the ratio in the insulating layer caused by adding and mixing the high dielectric material to the inorganic or organic insulating material. In order to reduce the occurrence of variations in the dielectric constant and the decrease in workability due to a change in the viscosity of the insulating layer, the thickness is preferably in the range of 0.5 to 50 μm.

Further, the content of the high dielectric material to be added to and mixed with the inorganic insulating material or the organic insulating material is set so as to increase the relative dielectric constant of the insulating layer and to make the inorganic insulating material or the organic insulating material and the high dielectric material. 5 to prevent a decrease in the adhesive strength of the material
Desirably, it is 75% by weight.

The wide area pattern as each signal wiring group or power supply layer or ground layer is made of, for example, tungsten (W), molybdenum (Mo), molybdenum manganese (M
o-Mn), metal powder such as copper (Cu), silver (Ag) or silver palladium (Ag-Pd), or copper (Cu), silver (Ag), nickel (Ni), chromium (C
r), titanium (Ti), gold (Au) or niobium (N
b) or a thin film of a metal material such as an alloy thereof.

Specifically, when a wide area pattern as each signal wiring group or power supply layer or ground layer is formed by metallizing metal powder of W, an appropriate organic binder, a solvent or the like is added to and mixed with W powder. The metal paste can be formed by printing and applying a predetermined pattern on a ceramic green sheet serving as an insulating layer, and firing this together with a laminate of ceramic green sheets.

On the other hand, in the case of forming a thin film of a metal material,
For example, after a metal film is formed by a sputtering method, a vacuum evaporation method, or a plating method, a predetermined wiring pattern can be formed by a photolithography method.

In such a multilayer wiring board, the width of each signal wiring group is appropriately set according to the relative dielectric constant of the insulating layer on which each signal wiring group is provided, so that each signal wiring group The characteristic impedance values of the signal wirings can be the same.

The present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the present invention. For example, three or more signal wiring groups may be formed between different insulating layers. Further, the number of built-in capacitors formed in the multilayer wiring board may be three or more. further,
The pattern of the power supply layer or the ground layer may be a so-called mesh pattern having a large number of openings.

In the present invention, with respect to the first signal wiring group in which a plurality of signal wirings having the first wiring length L1 are formed, the wiring length of each signal wiring of the first signal wiring group is substantially equal to the first wiring length. What is necessary is just the wiring length L1. The same applies to the second wiring length L2.

[0105]

According to the present invention, there is provided a multilayer wiring board comprising a semiconductor element mounted on an upper surface thereof and a plurality of insulating layers laminated thereon, and a signal wiring having a first wiring length L1 on the surface of the insulating substrate. A power supply layer or a ground layer formed to face the first signal wiring group with the first signal wiring group and the insulating layer formed by a plurality of layers interposed therebetween, and an insulating coating layer covering the first signal wiring group. The formed microstrip line section is opposed to the second signal wiring group via a second signal wiring group formed by forming a plurality of signal wirings having a second wiring length L2 inside the insulating substrate and the insulating layer. And a built-in capacitor formed by arranging a power supply layer and a ground layer facing each other with an insulating layer interposed therebetween inside a insulating substrate. Equipped multi-layer A line substrate, a first wiring length L1
And the second wiring length L2 is 0.8 × [(0.670 / εr−0.525)
× e ^{{-2 × (b + t) / h}} +1] ^1/2 ≦ L2 / L1 ≦ 1.2 ×
[(0.670 / εr-0.525) x e ^{{-2 x (b + t) / h}} +1] ^1/2
(However, L1> L2, t is the thickness of the signal wiring of the first signal wiring group, and h is the difference between the first signal wiring group and the power supply layer or the ground layer formed facing the first signal wiring group. The thickness of the insulating layer between them, b is the thickness of the insulating coating layer, εr is the relative permittivity of the insulating layer and the insulating coating layer, and e is the natural logarithm). Because a plurality of components having different resonance frequencies in the range of the frequency band of the harmonic component are formed so as to be connected in parallel, and a combined impedance value at an anti-resonance frequency generated between different resonance frequencies is set to a predetermined value or less. The wiring length of each signal wiring of the first and second signal wiring groups becomes equal, and the propagation delay time of each signal wiring of the first and second signal wiring groups becomes substantially the same for each signal wiring group.

Further, the propagation delay times of the first and second signal wiring groups having different wiring lengths can be made substantially the same within a range of ± 20%, which is a range in which a malfunction of the semiconductor element hardly occurs.

In addition, the capacitance and inductance of the signal wiring can be reduced, and the electrical noise such as signal noise and crosstalk noise can be reduced. In particular, the wiring length of the signal wiring in the second signal wiring group can be reduced. Since unnecessary lengthening can be avoided, the wiring area of other signal wirings can be widened, and the wiring flexibility is improved.

Further, it is possible to easily increase the number of signal wirings in response to an increase in the number of signals of the semiconductor element.

Further, it is possible to reduce the combined impedance value in a wide frequency band from the operating frequency of the semiconductor element to the frequency band of the harmonic component. When the combined impedance value at the anti-resonance frequency is 1 Ω or less, simultaneous switching noise can be reduced even in the high frequency band where the operating frequency of the semiconductor element is several GHz or more, including the frequency band of its harmonic component. .

The operating frequency of the semiconductor device is several MHz.
And simultaneous switching noise can be reduced even in a low frequency band.

Further, EMI noise can be reduced.

Further, it is possible to more effectively reduce electric noise and crosstalk noise of signal wiring.

As a result, according to the present invention, it is possible to reduce the electric noise of the signal wiring and increase the number of signal wiring while keeping the propagation delay time of each signal wiring substantially the same. A multilayer wiring board which can reduce switching noise and EMI noise and is suitable for an electronic circuit board on which electronic parts such as semiconductor elements operating at high speed are mounted can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention.

FIGS. 2A to 2F are plan views showing an example of each wiring layer of the multilayer wiring board of the present invention.

FIG. 3 is a diagram showing an example of an impedance characteristic of a built-in capacitor in the multilayer wiring board of the present invention.

FIG. 4 is a sectional view showing another example of the embodiment of the multilayer wiring board of the present invention.

FIG. 5 is a sectional view showing another example of the embodiment of the multilayer wiring board of the present invention.

FIG. 6A is a sectional view of a main part showing an example of an embodiment of a multilayer wiring board of the present invention, and FIG. 6B is an electric circuit diagram of a built-in capacitor of the multilayer wiring board of the present invention.

FIG. 7 is a cross-sectional view of a principal part showing an example of an embodiment of a multilayer wiring board of the present invention.

FIG. 8 is a plan view showing an example of a signal wiring group in a conventional multilayer wiring board.

[Explanation of symbols]

1, 21, 41: multilayer wiring board 2, 22, 42: insulating board 2a to 2f, 22a to 22f, 42a to 42f: insulating layer 3, 23, 43: first signal wiring group 4, 8, 10, 11 , 24, 28, 30, 31, 44, 48, 50, 51: power supply layer or ground layer 5, 25, 45: microstrip line section 6, 26, 46: insulating coating layer 7, 27, 47: second layer Signal wiring group 9, 29, 49: strip line section 14, 34, 54: semiconductor element 63, 65, 83, 85: power supply layer 70, 72, 90, 92: ground layer

Claims (2)

[Claims] 1. An insulating substrate having a semiconductor element mounted on an upper surface thereof and a plurality of insulating layers laminated thereon, and a plurality of signal wirings having a first wiring length L1 formed on a surface of the insulating substrate. A power supply layer or a ground layer formed so as to face one signal wiring group and the first signal wiring group with the insulating layer interposed therebetween, and a micro-layer constituted by an insulating coating layer covering the first signal wiring group. Strip line part,
A second signal line group in which a plurality of signal lines having a second line length L2 are formed inside the insulating substrate, and formed above and below the second signal line group via the insulating layer. Multi-layer wiring comprising: a strip line portion formed by a power supply layer or a ground layer formed by the above-described method; and a built-in capacitor formed by arranging a power layer and a ground layer in the insulating substrate so as to face each other with the insulating layer interposed therebetween. The substrate, wherein the first wiring length L1 and the second wiring length L2 are 0.8 × [(0.670 / εr−0.525) × e ^{{−2 × (b + t) / h}} +
1] ^1/2 ≦ L2 / L1 ≦ 1.2 × [(0.670 / εr−0.525)
× e ^{{-2 × (b + t) / h}} +1] ^1/2 (where L1> L2, t
Is the thickness of the signal wiring of the first signal wiring group, h is the thickness of the insulating layer between the first signal wiring group and the power supply layer or the ground layer formed facing the first signal wiring group, b Is the thickness of the insulating coating layer, εr is the relative permittivity of the insulating layer and the insulating coating layer,
e is a natural logarithm), and the built-in capacitor is formed such that a plurality of capacitors having different resonance frequencies in a range from the operating frequency band of the semiconductor element to the frequency band of the harmonic component are connected in parallel. And a combined impedance value at an anti-resonance frequency generated between the different resonance frequencies is equal to or less than a predetermined value. 2. The multilayer wiring board according to claim 1, wherein a combined impedance value at the anti-resonance frequency is 1Ω or less.