WO2003100970A1 - Lc series resonance circuit, board incorporating lc series resonance circuit, and production methods therefor - Google Patents

Lc series resonance circuit, board incorporating lc series resonance circuit, and production methods therefor Download PDF

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Publication number
WO2003100970A1
WO2003100970A1 PCT/JP2003/006649 JP0306649W WO03100970A1 WO 2003100970 A1 WO2003100970 A1 WO 2003100970A1 JP 0306649 W JP0306649 W JP 0306649W WO 03100970 A1 WO03100970 A1 WO 03100970A1
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WO
WIPO (PCT)
Prior art keywords
series resonance
resonance circuit
coil
multilayer substrate
capacitor
Prior art date
Application number
PCT/JP2003/006649
Other languages
French (fr)
Japanese (ja)
Inventor
Yuichi Ichikawa
Kouichirou Sagawa
Masahiko Oshimura
Original Assignee
Ajinomoto Co.,Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ajinomoto Co.,Inc. filed Critical Ajinomoto Co.,Inc.
Priority to AU2003241821A priority Critical patent/AU2003241821A1/en
Publication of WO2003100970A1 publication Critical patent/WO2003100970A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0033Printed inductances with the coil helically wound around a magnetic core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/40Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021Constructional details
    • H03H2001/0085Multilayer, e.g. LTCC, HTCC, green sheets
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/0115Frequency selective two-port networks comprising only inductors and capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors

Definitions

  • the present invention relates to an LC series resonance circuit and a method of manufacturing the same, and more particularly, the number of turns and the forming direction of a coil can be set almost arbitrarily, and a capacitance component is positively applied and connected in series with the coil.
  • the present invention relates to a small LC series resonance circuit formed in a multilayer capable of controlling a series resonance frequency, and a method for manufacturing the same.
  • the LC series resonance circuit is not only a replacement for the chip capacitors conventionally used, but also a semiconductor chip in which composite parts such as LC filters and VCOs, multi-layer boards, and interposers that incorporate the circuit are laminated on the outer surface. It can also be suitably used.
  • a coupling capacitor which cuts a DC signal and passes only a high-frequency signal, is used for connection between the circuits.
  • a capacitor called a decoupling capacitor having a low impedance with respect to a used frequency is also used.
  • the decoupling capacitor works to drop the signal that has passed through high impedance components to GND.
  • the basic structure of a capacitor is a structure in which a dielectric is sandwiched between opposing conductors.
  • Various structures have been used by connecting them in series or in parallel.
  • the capacitor-containing component for example, in the case of an LC filter, as described in Japanese Patent Application Laid-Open No. Hei 6-20939, an inductor having a helical structure and a capacitor having opposing electrodes are all circuits. It is general that the formation direction is parallel to the opposite plane and an electrode for connecting the substrate is provided outside the plane.
  • these methods are structurally inevitably large and difficult to miniaturize.
  • VCO as a combination of a capacitor and an inductor.
  • the structure is the same as that of the LC filter, and miniaturization is also difficult.
  • ICs with inductors, capacitors, and resistors are widely used as the heart of various devices.
  • the IC circuit is a high-frequency circuit more than a general board, and the filter and capacitor as described above are indispensable and built into the circuit.
  • the individual capacitors as before, there has been no publication other than that of a structure in which a dielectric is sandwiched between opposing conductors.
  • Japanese Patent Application Laid-Open No. 58-187 there is a proposal of a chip inductor having a circuit formed like a chip. Further, Japanese Patent Application Laid-Open Nos. Sho 62-187970 and JP-A-Hei 437-1706 disclose a circuit similar to the coil portion of the present invention in the direction perpendicular to the opposite plane. A coil having a plurality of surfaces is formed in a spiral shape in a plurality of layers, and adjacent circuits via an insulating layer have a spiral pattern wound in opposite directions when viewed from the same direction. An inductor component using a coil characterized by being connected has been proposed. However, none of these proposals mentions a method of controlling the series resonance frequency by positively adding a capacitance component.
  • the present invention provides a small-sized LC series resonance circuit suitable for use as a chip capacitor, a capacitor built-in component, a capacitor built-in substrate and a capacitor component for a capacitor built-in Ic chip, which can easily control the series resonance frequency, and a method of manufacturing the same. The task is to do so.
  • the invention described in claim 1 is a coil formed integrally with a multilayer substrate, the coil including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. And a capacitor formed integrally with the multilayer substrate, the capacitor being electrically connected in series with the coil, wherein the coil and the capacitor are supported in the multilayer substrate,
  • Each of the unit windings of the coil has a spiral pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings.
  • the sets are characterized by being connected alternately at the tips or ends of the spiral pattern.
  • the invention described in claim 2 is a coil formed integrally with the multilayer substrate, wherein the coil includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate.
  • the invention described in claim 3 has the feature of the invention described in claim 2 in addition to the case where the unit winding of the coil is viewed from the same direction as another adjacent unit winding.
  • Each of the coils has a spiral pattern that turns in the opposite direction, and the sets of adjacent unit windings of the coil are connected alternately at the tips of the spiral pattern or at the ends thereof.
  • the invention described in claim 4 has the feature that, in addition to the features of the invention described in any one of claims 1 to 3, the coil has a winding portion parallel to the multilayer substrate. It is formed as a part of a stacked conductive layer, and a winding portion perpendicular to the multilayer substrate is formed as a bump connecting the adjacent conductive layer via the insulating layer.
  • the invention set forth in claim 5 is characterized in that, in addition to the features of the invention set forth in any one of claims 1 to 3, the coil is formed parallel to the multilayer substrate by a build-up method.
  • a winding portion is formed as a part of the stacked conductive layers, and a winding portion perpendicular to the multilayer substrate is formed as a via or a through hole connecting the adjacent conductive layers through the insulating layer. It is characterized by the following.
  • the dielectric constituting the capacitor is made of fired high dielectric ceramic.
  • the dielectric constituting the capacitor is a powder of high dielectric ceramic or It is made of an organic material containing whisker.
  • the invention described in claim 10 is characterized in that, in addition to the features of the invention described in claim 8 or 9, the high dielectric ceramic is at least one of barium titanate and strontium titanate. It is characterized by containing.
  • the invention described in claim 11 is formed integrally with the LC series resonance circuit according to any one of claims 1 to 10, the multilayer substrate, and the multilayer substrate. And another circuit supported in the multilayer substrate.
  • the invention described in claim 12 includes the LC series resonance circuit in a multilayer substrate according to any one of claims 1 to 10, and is laminated on an outer surface of a semiconductor chip. The semiconductor chip is electrically connected to a specific portion of the semiconductor chip.
  • the invention set forth in claim 13 is characterized in that, in addition to the features of the invention described in claim 3 of claim 11, the invention is laminated on the outer surface of the semiconductor chip, and is arranged between a specific portion of the semiconductor chip. And are electrically connected.
  • the invention described in claim 14 is a step of forming one insulating layer constituting the multilayer substrate, a step of forming a capacitor inside the multilayer substrate, and a winding of a coil parallel to the multilayer substrate. Forming at least a portion of the portion on the insulating layer in the multilayer substrate; and forming a vertical connection portion for electrically connecting at least a portion of the winding portion of the coil parallel to the multilayer substrate between the insulating layers. Forming at least a part of a winding portion of a coil perpendicular to the multilayer substrate, and connecting the capacitor and the coil so that they are electrically connected in series. Electrically connecting;
  • the step of forming an insulating layer the step of forming at least a part of a winding portion of a coil parallel to the multilayer substrate, and at least a part of a winding portion of a coil perpendicular to the multilayer structure.
  • a predetermined coil supported in the multilayer substrate is formed by a coil winding portion parallel to the multilayer substrate and a coil winding portion perpendicular to the multilayer substrate in at least one of the forming steps. And repeating steps as appropriate for the part of the multilayer substrate formed up to that point.
  • the unit windings of the predetermined coil each have a spiral pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings, and the unit windings of the predetermined coil are adjacent to each other.
  • the set of unit windings is characterized by being connected alternately at the ends or ends of the spiral pattern.
  • the invention according to claim 15 includes a step of forming one insulating layer constituting the multilayer substrate, a step of forming a capacitor in the multilayer substrate, and a winding of a coil parallel to the multilayer substrate. Forming at least a portion of the portion on an insulating layer in the multilayer substrate; and a vertical connection portion for electrically connecting at least a portion of the winding portion of the multilayer antiparallel coil between the insulating layers. Forming at least a part of a winding portion of a coil perpendicular to the multilayer substrate; and forming a capacitor between the capacitor and the coil so as to be electrically connected in series. Electrically connecting to each other; and forming a core structure made of a columnar magnetic material so as to be disposed inside the coil.
  • the step of forming an insulating layer the step of forming at least a part of a coil winding part parallel to the multilayer substrate, and the forming of at least a part of a coil winding part perpendicular to the multilayer substrate.
  • a predetermined coil supported in the multilayer substrate is formed by the winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate. Until it is formed Repeating the steps as appropriate for the portion of the multi-layer substrate.
  • the invention set forth in claim 16 may include, in addition to the features of the invention set forth in claim 14 or 15, the vertical connection portion may be adjacent to the conductive layer via the insulating layer. Are connected to each other.
  • Claim 17 provides, in addition to the features of the invention described in Claims 14 or 15, at least one of the steps is performed by a build-up method, and
  • the vertical connection portion is a via or a through hole connecting the adjacent conductive layers through the insulating layer.
  • the invention described in claim 18 uses an organic material for the insulating layer of the multilayer substrate in addition to the features of the invention described in any one of claims 14 to 17. It is characterized by the following.
  • the invention described in claim 19 is characterized in that, in addition to the features of the invention described in any one of claims 14 to 18, a ceramic is used for the dielectric material constituting the capacitor. It is characterized by doing.
  • the invention set forth in claim 20 is characterized in that, in addition to the features of the invention set forth in any one of claims 14 to 19, the dielectric material constituting the capacitor is fired. It is characterized by being made of dielectric ceramic.
  • the invention described in claim 21 is characterized in that, in addition to the features of the invention described in any one of claims 14 to 18, the dielectric constituting the capacitor is a high dielectric ceramic. Or an organic material containing whisker.
  • the invention set forth in claim 22 is the invention according to claim 20 or 21, wherein the high dielectric ceramic is made of barium titanate or sodium titanium titanate. It is characterized by containing at least one of the above.
  • the invention described in claim 23 is any one of claims 14 to 22. 2.
  • the invention described in claim 24 includes a step of the method for manufacturing an LC series resonance circuit according to any one of claims 14 to 22, wherein the LC series resonance circuit is provided.
  • the substrate with a built-in circuit is laminated on the outer surface of the semiconductor wafer, and a step for electrically connecting the substrate with a built-in LC series resonance circuit to a specific portion of the semiconductor chip; Separating the semiconductor wafer on which the substrate with a built-in resonance circuit is laminated in units of semiconductor chips.
  • the invention described in claim 25 has the feature of the invention described in claim 23, and furthermore, the substrate with a built-in LC series resonance circuit is laminated on the outer surface of the semiconductor wafer.
  • the invention set forth in claim 26 includes a step of the method for manufacturing an LC series resonance circuit according to any one of claims 14 to 22, wherein the LC series resonance circuit is provided.
  • the circuit is stacked on the outer surface of the semiconductor chip, and further includes a step of electrically connecting the LC series resonance circuit to a specific portion of the semiconductor chip.
  • the invention set forth in claim 27 includes a step of the method for manufacturing a multilayer substrate with built-in LC series resonance circuit according to claim 23, wherein the substrate with built-in LC series resonance circuit is a semiconductor.
  • tip and end in this specification refer to either one end of the spiral pattern, here the innermost end is the tip, and the outermost end is the end, based on the innermost end. I do.
  • terms representing positional relationships such as parallel and vertical are not required to be strictly geometrical, and have a meaning that such positional relationships are sufficient.
  • the LC series resonance circuit of the present invention has an active component added to it, and its size can be freely adjusted. As a result, the series connection of such LC series resonance circuit The resonance frequency can be easily controlled.
  • FIG. 1A is a perspective conceptual view of an LC series resonance circuit according to the first embodiment of the present invention
  • FIG. 1B is a perspective conceptual view of the LC series resonance circuit according to the second embodiment of the present invention.
  • Fig. 1 (c) is a perspective conceptual view of an LC series resonance circuit according to a third embodiment of the present invention
  • Figs. 1 (d) and 1 (e) show the structure of another coil. It is a figure showing an example.
  • FIG. 2A is a perspective conceptual view of the LC series resonance circuit according to the fourth embodiment of the present invention
  • FIG. 2B is a perspective conceptual view of the LC series resonance circuit according to the fifth embodiment of the present invention
  • FIG. 2C is a conceptual perspective view of an LC series resonance circuit according to a sixth embodiment of the present invention.
  • FIG. 3 is a conceptual perspective view of an LC series resonance circuit according to the first embodiment of the present invention at an initial stage of manufacturing.
  • FIG. 4 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 5 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 6 shows an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 6649 is a perspective conceptual view.
  • FIG. 2 is a schematic perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 8 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 9 is a perspective conceptual view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 10 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 11 is a perspective conceptual view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 12 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 13 is a perspective conceptual view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of an LC series resonance circuit according to the first embodiment of the present invention at an initial stage of manufacturing on an IC chip.
  • FIG. 15 is a cross-sectional view for explaining via formation.
  • FIG. 16 is a cross-sectional view for explaining formation of a conductive pattern for forming a circuit.
  • FIG. 17 is a cross-sectional view for explaining the formation of the second insulating layer. '.
  • FIG. 18 is a cross-sectional view for explaining the formation of the second conductive pattern.
  • FIG. 19 is a cross-sectional view for explaining formation of the third layer.
  • FIG. 20 is a conceptual sectional view of an LC series resonance circuit formed on an IC chip according to the first embodiment of the present invention.
  • FIG. 21 is a conceptual diagram of a cross section of a via.
  • FIG. 22 is a conceptual sectional view showing an example of an LC series resonance circuit formed on an IC chip according to the first embodiment of the present invention.
  • FIG. 23 is a conceptual cross-sectional view showing an example of an LC series resonance circuit formed on an IC chip according to the first embodiment of the present invention.
  • FIG. 24 is a plan view of a coil and a capacitor of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 25 is a cross-sectional view of the LC series resonance circuit according to the embodiment of the present invention, taken along the line AA.
  • FIG. 26 is a perspective view of a coil of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 27 is a graph illustrating a frequency characteristic of a reactance component of a coil of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 28 is a perspective view of a capacitor of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 29 is a graph showing the frequency characteristic of the reactance component of the capacitor of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 30 is a plan view of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 31 is a perspective view of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 32 is a graph illustrating a frequency characteristic of a reactance component of the LC series resonance circuit according to the example of the present invention.
  • FIG. 33 is a circuit diagram of an LC series resonance circuit and a graph showing frequency characteristics of a current.
  • FIG. 1A is a conceptual perspective view showing a schematic configuration of the LC series resonance circuit 100.
  • the LC series resonance circuit 100 is composed of a coil 100a, a capacitor 100c, connection points 100f and 100g, and a multilayer substrate 100h.
  • the coil 100a is a component that gives an inductance and is formed as a part of the conductive layer in each step of forming the plurality of insulating layers and conductive layers in the multilayer. Such a coil whose central axis is parallel to the multilayer substrate is called a “vertical coil”.
  • the coil 100a is preferably configured in such a manner that a unit winding 100 Ob having a repeating pattern of a conducting wire having a rectangular or circular cross section is electrically and continuously connected in series. Is done.
  • the form of the coil 100a and the unit winding 100b in the present specification is intended to broadly include any form for providing inductance.
  • a winding portion of the coil 100a parallel to the multilayer is formed as a part of a conductive layer to be stacked, and a winding portion perpendicular to the multilayer substrate is adjacent to the multilayer substrate via an insulating layer. It is formed as a bump, a via, a through hole, or the like connecting the conductive layers.
  • the coil 100a is formed in a multilayer board manufacturing process by using a known multilayer board (printed board) forming technique such as a build-up method.
  • the coil 100a includes a winding portion parallel to the multilayer substrate 100h and a winding portion perpendicular to the multilayer substrate.
  • the capacitor 100c is composed of two opposing electrode plates 100d and a dielectric material 100e sandwiched therebetween.
  • the electrode plate consisting of opposing comb-shaped electrodes and a multi-layer dielectric sandwiched between them, as used in a general multilayer capacitor, are used. It may be a configured capacitor.
  • the electrode plate 100d is preferably formed as a part of the conductive layer in the step of forming each of the plurality of insulating layers and the conductive layer in the multilayer substrate.
  • the dielectric 100 e may be the same material as the insulating material composing the multilayer fiber 100 h, and in consideration of the dielectric constant, cost, manufacturing process, etc., the multilayer substrate 100 h May be different from the insulating material constituting the material.
  • the connection point 100Of is a contact point for electrically connecting one end of the coil 100a and one of the electrode plates 100d.
  • Connection point 100 gl This is a contact for electrically connecting the wiring going to the outside and the other of the electrode plates 100 d.
  • the capacitor 100c and the coil 100a are electrically connected in series, and together form an LC series resonance circuit.
  • the other end of the coil 100a is connected to a wire extending from the LC series resonance circuit to the outside.
  • the multilayer substrate 10 Oh is a substrate configured by laminating insulating layers. In the actual step of forming the multilayer substrate 10 Oh, insulating layers and conductive layers are alternately laminated. The portion of the conductive layer becomes a part of the coil 100a, and the portion of the other insulating layer becomes the multilayer substrate 100 Oh.
  • the LC series resonance circuit 100 does not mean the entire multilayer substrate including such an LC series resonance circuit, but is characterized by being held in the multilayer substrate.
  • FIG. 1B is a conceptual perspective view showing a schematic configuration of the LC series resonance circuit 120.
  • the LC series resonance circuit 120 has a structure in which the capacitor 100c is arranged outside the coil 100a in the LC series resonance circuit 100.
  • Each component of the LC series resonance circuit 120 corresponds to a component of the LC series resonance circuit 100 whose reference numeral is changed from 100 to 120.
  • the capacitor 100c is placed inside the coil 100a, as in the LC series resonance circuit 100, it is said that the overall thickness is thinner and thinner by increasing the degree of integration. There are advantages.
  • the area of the unit winding 100b is increased to easily form the coil 100a having a larger inductance.
  • the process of laminating the coil 120c is omitted.
  • the capacitor 120 c is located near the outer surface of the multilayer substrate 12 Oh. Since it is located, it is possible to fine-tune the capacitance by trimming the electrode plate 120c with laser or the like and adjusting the area.
  • FIG. 1C is a perspective conceptual view showing a schematic configuration of the LC series resonance circuit 140.
  • the LC series resonance circuit 140 has a structure in which the magnetic body 140i is arranged inside the coil 120a in the LC series resonance circuit 120.
  • Each component of the LC series resonance circuit 140 corresponds to a component of the LC series resonance circuit 120 in which the numeral portion of the code is changed from 120 to 140.
  • the magnetic body 140i is disposed inside the coil 140a, there is an advantage that the inductance of the coil 140a can be increased.
  • a configuration in which a magnetic material is disposed inside the coil 100a of the LC series resonance circuit 100 according to the first embodiment of the present invention is also possible.
  • a magnetic body can be arranged on the upper side, the lower side, or both sides of the capacitor.
  • Figures 1 (d) and (e) are examples of other coil structures. In these examples, the coil is constituted only by the winding portion in the direction parallel or perpendicular to the center axis of the coil.
  • FIG. 2A is a perspective conceptual view showing a schematic configuration of the LC series resonance circuit 200.
  • the LC series resonance circuit 200 includes a coil 200a, a capacitor 200c, connection points 200f and 200g, and a multilayer substrate 200h.
  • the structure of these components is almost the same as that of the above-mentioned LC series resonance circuit 100, and the sign is also changed only from “100” to “200j” in the numerals.
  • the unit windings 200 Ob of the coil 200a each have a helical pattern that turns in the opposite direction when viewed from the same direction as other adjacent unit windings.
  • the configuration of the coil 100a is different from that of the coil 100a in that the lines are connected to each other at the tips or ends of the spiral pattern.
  • the number of turns in the unit winding can be made larger than one, and when a current flows through the coil 200a, all the unit windings generate a magnetic field in the same direction. Therefore, the inductance can be increased.
  • a coil having such a structure is distinguished from a single-layer coil such as the coil 100a, and is hereinafter referred to as a multilayer coil.
  • FIG. 2B is a schematic perspective view showing a schematic configuration of the LC series resonance circuit 220.
  • the LC series resonance circuit 220 has a structure in which the capacitor 200c is arranged outside the coil 200a in the LC series resonance circuit 200.
  • Each component of the LC series resonance circuit 220 corresponds to a component of the LC series resonance circuit 200 in which the numeral portion of the reference numeral is changed from 200 to 220.
  • the capacitor 200c is placed inside the coil 200a, as in the LC series resonance circuit 200, it is said that the overall thickness is thinner and thinner by increasing the degree of integration. There are advantages.
  • the area interlinking the magnetic field of the unit winding 200 Ob is increased to form a coil 200 a having a larger inductance.
  • the capacitor 220c is disposed outside the coil 220a, such as the LC series resonance circuit 220, the process of laminating the coil 220c is simplified.
  • a capacitor 220c having a larger electrode plate area can be selected. Further, similarly to the above-described LC series resonance circuit 120, the capacitance of the capacitor 220c can be finely adjusted.
  • FIG. 2C is a conceptual perspective view showing a schematic configuration of the LC series resonance circuit 240.
  • the LC series resonance circuit 240 has a structure in which the magnetic body 240i is arranged inside the coil 220a in the LC series resonance circuit 220.
  • Each component of the LC series resonance circuit 240 is [0306649] Corresponds to the component in which the numeral part of the code is changed from 220 to 240.
  • the magnetic material 240i is disposed inside the coil 240a, there is an advantage that the inductance of the coil 240a can be increased.
  • a configuration in which a magnetic body is disposed inside the coil 200a of the LC series resonance circuit 200 according to the fourth embodiment of the present invention is also possible.
  • a magnetic body can be arranged on the upper side, the lower side, or both sides of the capacitor.
  • the operation of the LC series resonance circuits 100, 120, 140, 200, 220 and 240 will now be described.
  • the multilayer substrate 100 h, 12 Oh, 14 Ohs 200 Ti, 22 Oh or 24 Oh is preferably used as an interposer for mounting a semiconductor chip constituting a monolithic IC or the like thereon.
  • the multilayer board 100 h, 120 h, 140 h, 200 h, 220 h or 240 h can have other circuit elements formed inside or mounted outside, and such other circuit elements can be mounted. It is possible to configure a semiconductor package in which the function of a circuit composed of a semiconductor chip and the LC series resonance circuit 100, 120, 140, 200, 220 or 240 is added to the function of the semiconductor chip itself.
  • the capacitance can be changed by changing the configuration of the capacitor (the plate area, the distance between the plates, the dielectric constant of the dielectric, etc.), and the degree of the decrease in the series resonance frequency can be controlled. That is, the series resonance frequency can be easily controlled while keeping the coil portion common. Further, by adjusting the extension direction of the coil, the number of windings can be set easily and almost arbitrarily, and the inductance can be changed.
  • the inductance can be set flexibly by adjusting the area where the unit winding interlinks with the magnetic field as a whole or partially. In this way, the static of the capacitor can be changed easily and freely. Therefore, the series resonance frequency can be set easily and freely.
  • the frequency band through which the current is passed or blocked, and the degree thereof can be flexibly set.
  • a decoupling capacitor that is, a capacitor that plays a role of dropping a high impedance signal to GND. If the LC series resonance circuit of the present invention having a series resonance frequency according to the operating frequency is used in place of the decoupling capacitor by adjusting the intagter component, the intended signal in the operating frequency band is more reliably dropped to GND. It is possible.
  • the series resonance frequency can be controlled.
  • the inductance component can be set almost arbitrarily by adjusting the number of turns and the length.
  • a part of the coil is formed in parallel with the opposite plane by sequentially forming an insulating layer, forming a hole, and forming a conductive pattern in parallel with the plane of the substrate.
  • a coil-shaped circuit having unit windings on a plane perpendicular to the opposite plane can be formed in a spiral shape. If necessary, adjacent unit windings have a spiral pattern wound in opposite directions when viewed from the same direction, and the leading ends or the trailing ends of the spiral pattern are viewed from the same direction.
  • Coils that are electrically connected to each other can be formed.
  • a coil having a desired number of turns can be easily obtained.
  • the conventional method of forming a spiral pattern on a plane parallel to the plane of the substrate it is necessary to increase the number of layers in order to increase the number of windings, resulting in a large cost increase.
  • the number of layers is not changed. It only needs to be stretched in the coil extension direction, and there is little cost increase.
  • the main magnetic field lines are generated in a direction parallel to the substrate, so that the transistor The effect is small in the direction perpendicular to the substrate. Therefore, the degree of freedom in design becomes very high. Further, in the method of the present invention, since the extension direction of the coil can be set to any direction in the plane of the substrate, the coil can be formed in the same process in any direction as necessary.
  • FIG. 24 is a plan view of a coil and a capacitor of the LC series resonance circuit according to the embodiment of the present invention.
  • FIG. 25 is a cross-sectional view of the LC series resonance circuit according to the example of the present invention, taken along the line AA.
  • the unit of the numerical value of the length in FIGS. 24 and 25 is mm.
  • the simulation was performed assuming that the conductors of the circuit, the bottom and side surfaces of the board were perfect conductors, and the permittivity between conductors was 2.0.
  • the LC series resonance circuit in which the coil and the capacitor are in such a positional relationship was analyzed using three-dimensional electromagnetic field simulation (Sonnet).
  • FIG. 26 is a perspective view of a coil of the LC series resonance circuit according to the embodiment of the present invention.
  • the graph shown in Fig. 27 was obtained. Based on these results, the inductance values corresponding to 500 MHz, 1000 MHz, and 2000 MHz are obtained as shown in the table below.
  • FIG. 28 shows an LC series according to the embodiment of the present invention. It is a perspective view of the condenser of a resonance circuit. When the frequency dependence of the reactance component of this capacitor was determined by simulation, the graph shown in Fig. 29 was obtained. Based on these results, the capacitance values corresponding to 500MHz, 1000MHz, and 200.0MHz were obtained as shown in the table below.
  • Equation for resonance frequency of series resonant circuit based on inductance value and capacitance value at 50 OMHz When the series resonance frequency was calculated from ( ⁇ * (C + CO)), it was 2119 MHz.
  • FIG. 33 shows a circuit diagram of the LC series resonance circuit and a graph showing the frequency characteristics of the current.
  • FIG. 1 and FIG. 2 are diagrams according to a typical embodiment of the LC series resonance circuit of the present invention.
  • FIG. 1 shows an embodiment in which a single-layer coil and a multilayer coil are provided with a capacitor pattern.
  • FIG. 3 A core substrate 1 having a through hole 1a which will later be a part of a coil and a capacitor plate 1c formed on both sides of the insulator lh is prepared.
  • the two plates Id sandwich the dielectric 1e, and they constitute a capacitor 1c.
  • connection points 1f and 1g to which wiring to an external circuit is connected are formed on each of the electrode plates 1d.
  • a copper-clad laminate using a known and common organic material as the insulator 1 h can be used.
  • the insulator lh for example, a glass epoxy tree S, a bismaleimide-triazine substrate, or a dielectric Polyphenylene ether resin, polyether ether ketone resin S, benzocyclobutene resin and the like having excellent properties can be used.
  • the same material as the insulator lh can be used as the dielectric 1e between the electrode plates lb.However, the dielectric 1e is replaced by a high dielectric filler such as barium titanate or strontium titanate. By blending it in the material, a capacitor layer with high capacity and low dielectric loss can be obtained.
  • a high-dielectric material composed of a cyanate ester and an epoxy resin can fill a high-dielectric film at a high level, and is suitable as a high-capacity capacitor material.
  • a dielectric 1e is formed by firing a ceramic mainly composed of a high dielectric ceramic such as barium titanate or strontium titanate, and a core substrate 1 having electrode plates lb formed on both surfaces thereof is formed. By using it, it is possible to obtain a small and high-capacity capacitor. Drilling of the through hole 1a can be performed by a widely used method such as a drill or a carbon dioxide laser or a YAG laser.
  • Patterning of the conductor can be performed by a known and commonly used method such as a subtractive method or an additive method. Subsequently, outermost layers are laminated and formed on both surfaces of the core substrate 1 as shown in FIG.
  • the same material and method as the core 1 can be used as a material of the insulating layer 1i, a hole forming method, a conductor patterning method, and an electrical connection method between layers.
  • the outermost layer can be formed by forming an insulating layer li on both sides of the inner layer material, and further forming a conductive layer outside the inner layer material, and performing power connection and electrical connection. In several ways A specific example will be given below.
  • An insulating layer is formed on a substrate made of the above inner layer material.
  • a prepreg such as a glass epoxy type or an aramide resin type, a liquid or film-like thermoplastic or thermosetting resin composition, or a copper foil with a resin generally called a copper foil and an insulating resin layer One that integrates can be used.
  • the formation of the insulating layer is performed, for example, as follows.
  • the core substrate 1 has a pre-predder 2 on both sides, an unpatterned copper foil 3,
  • a resin-coated copper foil 4 is placed, and as shown in Fig. 6, these are collectively laminated and cured by a lamination press method to create an integrated insulating layer and conductive layer. .
  • a liquid composition is applied onto the core substrate 1 by a known and common method such as screen printing, force coating, spray coating, etc., and cured by UV, electron beam, heat, or the like. Let it.
  • a film-like composition is pasted on the substrate by a method such as rolling or laminating, and cured by a predetermined method to obtain an insulating layer 5.
  • a via is formed.
  • a via 6 is formed at a predetermined position of the obtained by the above method using a drill, a laser or the like.
  • Fig. 8 (a) shows the case where prepreg 7 and copper foil 8 were used as the insulating layer and the conductive layer.
  • Fig. 8 (b) shows the copper foil with resin 9 and Fig. 8
  • thermosetting resin composition 10 is a liquid or film-like thermoplastic, and (c) is a description using a thermosetting resin composition 10. If a conductive layer is formed together with the insulating layer using prepregs or resin-coated copper foil, use a carbon dioxide gas laser widely used for forming blind vias. A so-called masking process may be performed to remove the conductor at a predetermined position by etching.
  • a conductive layer is formed together with an insulating layer using a pre-preda or resin-coated copper foil, for example, conductive powder such as silver or copper is mixed in the via as shown in Fig. 9 (a).
  • the conductive paste 11 is embedded by a method such as printing or dispensing, and is hardened by a predetermined method.
  • a normal through-hole plating that is, an electroless plating is performed after a plating catalyst is applied in a via, and then a plating layer 1 is formed by performing an electrolytic plating. Electrical connection is also achieved by the method of forming 2.
  • the insulating layer is formed using a liquid or film-like composition, as shown in FIG.
  • a copper foil 13 is pressed to form a conductive layer outside the insulating layer, and After performing mask processing at the position, the blind via is made conductive by the conductive paste 11 or the plating layer 12 and connected.
  • the blind via may be made conductive first.
  • a catalyst is applied to the reaction where the insulating layer and the blind via are formed, and the electroless plating is performed.
  • the formation of 14 and the conductivity of the blind via can also be performed at once.
  • the blind vias can be made conductive by a conductive paste.
  • the copper foil 3, 8, or 13 or the conductive layer 14 is patterned to form a coil.
  • the insulating layer, the conductive layer, and the electrical connection can be collectively performed by the following method. That is, as shown in FIG. 10, after a conductive bump 15 having a sharp tip is formed at a predetermined location on the core substrate 1 using a conductive paste or the like, a prepreg 2 and a copper foil 3 (FIG. 10 (a)) or press work after placing the film-shaped insulator 5 and copper foil 3 (Fig. 10 (b)), or copper foil 4 with resin (Fig. 10 (c)). As a result, the pointed conductive bumps 15 penetrate the insulating layer to realize connection with the conductive layer.
  • the hole is filled. Fill the through holes or blind vias with a finning or plating process and clean the surface You may perform smoothing.
  • the core substrate 1 and the outermost layer of FIG. 13 are aligned, and the composition that has been semi-cured by pressing is removed from the bump portion, and the insulating layer between the layers is removed.
  • the bumps are electrically connected to the conductors in the inner layer, producing an LC series resonant circuit with a four-layer structure.
  • the LC series resonance circuit 120 using a single-layer coil in which a capacitor 120c is arranged outside the three coils 120a is also the LC series resonance circuit 1 described above. It can be manufactured by appropriately performing the same steps as those of the manufacturing method 100 according to the configuration. In this case, it is preferable that the manufacturing process of the LC series resonance circuit 120 be started with one layer constituting the multilayer substrate 120h as an initial material or with the capacitor 120c as an initial material.
  • the magnetic body is arranged in the step of laminating the multilayer substrate so that the magnetic body is arranged inside the coil.
  • a core structure made of a columnar magnetic material penetrating the inside of the coil can be formed.
  • further multilayering is required. Further multilayering is possible using any of the above methods. In other words, a series of steps including the provision of an insulating layer, the provision of a conductive layer, the electrical connection between conductive layers (formation of through holes and encapsulation of a conductive material, the contact of bumps, etc.), and the patterning of the conductive layer are repeated. By returning, it can be multi-layered.
  • the position of the through hole in each layer and the pattern of the conductive layer are preferably the coil 200a as shown in FIG. 2 (a) or the coil 220a as shown in FIG. 2 (b). It is configured so that a is formed.
  • the LC series resonant circuit including the multilayer coil shown in Fig. 2 (a) and (b) can be easily manufactured.
  • a ceramic material can be used as the insulating material. Also in this case, it can be manufactured by basically forming a part of the coil and a capacitor-like pattern on each layer in the same process as the organic material, and laminating them.
  • the LC series resonance circuit in the multilayer substrate of the present invention can be formed by sequentially performing a method of forming a hole in a green sheet, filling a hole with a conductive paste, and printing, laminating, and firing in a conventional manner. As mentioned earlier, it is possible to use ceramic material only for the insulating layer that constitutes the capacitor, and to use organic material for the other parts.
  • any of the above-mentioned LC series resonance circuits can be formed by integrally forming other circuits, for example, circuits such as ICs, memories, resistors, or high-frequency elements in a multi-layered circuit. It can be a multilayer substrate with a built-in circuit. Such other circuits may be electrically connected to the LC series resonant circuit and may not be directly connected. Is also good.
  • This multi-layer substrate with built-in LC series resonance circuit is formed integrally with the LC series resonance circuit, so that it can be easily manufactured in the same manufacturing process, and has the advantage that the degree of integration of elements can be improved. is there. .
  • any of the above-described LC series resonance circuits or the multilayer substrate with a built-in LC series resonance circuit can be formed on a semiconductor chip constituting a monolithic IC or the like. With such a configuration, elements such as an LC series resonance circuit can be incorporated in the semiconductor package with a high degree of integration. From now on, the process of forming a coil having unit windings on a surface perpendicular to the plane of the substrate and forming a capacitor-like pattern parallel to the plane of the substrate will be described below. As a typical example, an example is shown in which an LC series resonance circuit 100 shown in FIG.
  • the semiconductor 1A is formed in a so-called electrode wiring layer on an upper layer of a silicon wafer in which a transistor is formed and an electrode portion is formed with tungsten or the like.
  • the semiconductor is not limited to silicon, and any known semiconductor material such as gallium arsenide can be used.
  • a lowermost insulating layer 22 is formed on a silicon wafer 21 on which transistors and electrode portions are formed.
  • the silicon oxide film can be formed by a vapor phase method such as CVD, or by spin-coating an organic material such as polyimide or benzocyclobutene, which has recently attracted attention, and then performing bast baking.
  • holes 23 are drilled in necessary places using various lasers. The hole 23 is a specific portion of the semiconductor wafer 21 or a portion for making an electrical connection with the lower electrode portion.
  • a conductive pattern 24 is formed.
  • a commonly used aluminum sputtering or copper layer is formed by a vapor phase method such as CVD or a wet method such as plating. Next, it is exposed, etched and patterned. In this case, the conductive layer may be formed after forming the resist layer that has been patterned in advance. In this process, as shown in Figure 15 The holes 23 formed in the process are also made conductive, and the first layer and the second layer are electrically connected. Before the exposure step, the surface is usually planarized by physical polishing or a method called chemical mechanical polishing (CMP) that combines physical polishing and physical polishing. Next, as shown in FIG. 17, a second insulating layer 25 is formed. Next, as shown in FIG.
  • CMP chemical mechanical polishing
  • a hole is formed again, and a second conductive pattern 26 is formed by forming a conductive pattern. At this time, a capacitor-shaped capacitor can be formed at the same time.
  • a third insulating layer 27 is formed by the above-described method, a hole is formed, the conductive layer is formed, and a third conductive pattern 28 is formed. Take the third layer conduction.
  • this operation is repeated to form a fourth insulating layer 29, as shown in FIG. 19, and then perform drilling, conducting, and patterning to form a fourth conductive pattern 30.
  • an LC series resonance circuit as shown in FIG. 1 can be formed on the semiconductor.
  • the hole (via hole) 31 is filled with a conductor 32.
  • a structure generally called a stacked via that is, a structure having a via hole on a filled via hole can be formed again, and the side of the coil can be made straight.
  • a stacked via structure cannot be formed by a commonly used method, that is, a method in which a via hole is not filled with a conductor. At that time, the manufactured coil has a cross-section in which the via-hole connection portion is stepped as shown in FIG. Even with such a structure, there is no practical problem particularly when used in a high frequency range.
  • the silicon substrate 21 and the multilayer substrate including the LC series resonance circuit are separated into semiconductor chip units.
  • the silicon wafer 21 may be divided into chips.
  • an LC series resonance circuit or a multilayer substrate incorporating the same may be laminated on the outer surface of the semiconductor chip that has been cut in advance in the same manner as in the above-described process.
  • the LC series resonance circuit manufactured by the method of the present invention can control the series resonance frequency more easily than the conventional one by adding a capacitor-like pattern to the inductor (coil) pattern. It can be used for a wide range of purposes despite its small size.
  • the number of turns of the coil and the direction in which the coil extends can be set freely, greatly improving the degree of freedom in design. Furthermore, it is also effective for noise suppression.

Abstract

A small LC series resonance circuit, and its producing method, in which a series resonance frequency can be set readily and the number of turns can be set substantially arbitrarily. The LC series resonance circuit comprises a coil being formed integrally with a multilayer board and including a winding part parallel with the multilayer board and a winding part perpendicular thereto, and a capacitor being formed integrally with the multilayer board and being connected electrically in series with the coil characterized in that the coil and the capacitor are supported in the multilayer board, adjacent unit windings of the coil, have spiral patterns turning in the opposite directions as viewed from the same direction and the sets of adjacent unit windings of the coil are connected alternately at the forward end or the end of the spiral pattern.

Description

明細書  Specification
L C直列共振回路、 L C直列共振回路内蔵基板、 及びそれらの製造方法  LC series resonance circuit, substrate with built-in LC series resonance circuit, and methods of manufacturing them
(技術分野) (Technical field)
本発明は、 L C直列共振回路及びその製造方法に関し、 より詳しくは、 コイル の巻き数および形成方向をほぼ任意に設定でき、 且つ容量成分を積極的に付カロし これをコイルと直列で接続することにより、 直列共振周波数を制御できる、 多層 内に形成される小型な L C直列共振回路及びその製造方法に関する。 該 L C 直列共振回路は、 従来使用されてきたチップコンデンサの代替のみならず、 該回 路を内蔵した L Cフィル夕や V C Oなどの複合部品、 多層基板、 インターポ一ザ が外面に積層される半導体チヅプにも好適に利用できる。  The present invention relates to an LC series resonance circuit and a method of manufacturing the same, and more particularly, the number of turns and the forming direction of a coil can be set almost arbitrarily, and a capacitance component is positively applied and connected in series with the coil. The present invention relates to a small LC series resonance circuit formed in a multilayer capable of controlling a series resonance frequency, and a method for manufacturing the same. The LC series resonance circuit is not only a replacement for the chip capacitors conventionally used, but also a semiconductor chip in which composite parts such as LC filters and VCOs, multi-layer boards, and interposers that incorporate the circuit are laminated on the outer surface. It can also be suitably used.
(背景技術)  (Background technology)
近年、 パソコン、 携帯電話など、 高周波を利用した、 高性能且つ小型の電気機 器が広く使用されている。 これらの機器には、 不要な信号除去のため、 インダク 夕 (コイル) とコンデンサを組み合わせた、 いわゆる積層 L Cフィル夕が多数用 いられている。  In recent years, high-performance and small-sized electric devices using high frequency, such as personal computers and mobile phones, have been widely used. These devices use a large number of so-called laminated LC filters that combine an inductor (coil) and a capacitor to remove unnecessary signals.
また、 これらの高周波回路では、 回路間の接続にカップリングコンデンサと呼 ばれる、 直流信号をカットし、 高周波信号のみを通すコンデンサが使用されてい る。  In these high-frequency circuits, a coupling capacitor, which cuts a DC signal and passes only a high-frequency signal, is used for connection between the circuits.
さらに、 デカヅプリングコンデンサと呼ばれる、 使用周波数に対して低いイン ピーダンスを有するコンデンサも用いられている。 デカツプリングコンデンサは、 高ィンピーダンスの部品を通過した信号を GNDに落とす働きをしている。  Furthermore, a capacitor called a decoupling capacitor having a low impedance with respect to a used frequency is also used. The decoupling capacitor works to drop the signal that has passed through high impedance components to GND.
これらコンデンサおよび'コンデンサ含有部品の提案は多数行われている。 コン デンサとしては、 対向する導体間に誘電体を挟み込んだ形が基本構造であり、 こ 3/06649 れを直列あるいは並列に接続することにより種々の構造が使用されている。 コン デンサ含有部品としては、 例えば L Cフィル夕の場合、 特開平 6— 2 0 8 3 9号 公報記載のように、 螺旋構造を有するインダク夕と、 対向する電極を有するコン デンサとを全ての回路形成方向が 反平面と平行になるようにし、 その外部に基 板接続用の電極を設けたものが一般的である。 しかしながらこれらの方法は、 構 造上必然的に大型となり、 小型化は困難である。 Many proposals for these capacitors and components containing capacitors have been made. The basic structure of a capacitor is a structure in which a dielectric is sandwiched between opposing conductors. Various structures have been used by connecting them in series or in parallel. As the capacitor-containing component, for example, in the case of an LC filter, as described in Japanese Patent Application Laid-Open No. Hei 6-20939, an inductor having a helical structure and a capacitor having opposing electrodes are all circuits. It is general that the formation direction is parallel to the opposite plane and an electrode for connecting the substrate is provided outside the plane. However, these methods are structurally inevitably large and difficult to miniaturize.
同様にコンデンサとインダク夕を組み合わせたものとして、 V C Oの提案も多 い。構造としては L Cフィル夕と同様であり、 やはり小型化は困難である。  Similarly, there are many proposals for VCO as a combination of a capacitor and an inductor. The structure is the same as that of the LC filter, and miniaturization is also difficult.
これら複合部品に関しては、 広く用いられているセラミック製のものに加えそ、 近年プリント基板用材料などの有機素材を用いた提案も数多くなされている。 し かしながら、 構造および製法については、 セラミックの場合と同様、 螺旋構造を 有するインダクタと、 対向する電極を有するコンデンサとを全ての回路形成方向 が基板平面と平行になるようにし、 その外部に 反接続用の電極を設けたものに ついての提案しかなされていない。  As for these composite parts, in addition to widely used ceramic parts, many proposals using organic materials such as printed circuit board materials have been made in recent years. However, as for the structure and manufacturing method, as in the case of ceramics, the inductor having a helical structure and the capacitor having opposing electrodes are arranged so that all circuit formation directions are parallel to the substrate plane, and Only proposals have been made for those provided with anti-connection electrodes.
一方、 ビルドアップ工法など、 近年の多層基板製造技術の発展に伴い、 各種能 動/受動基板を基板内部に作り込む、 いわゆる部品内蔵基板が活発に研究されて いる。 しかしながら、 コンデンサを基板内に形成する方法に関しては、 従来通り、 対向する導体間に誘電体を挟み込む構造のもの以外の発表は未だない。  On the other hand, with the recent development of multilayer substrate manufacturing technology such as the build-up method, so-called component-embedded substrates, in which various active / passive substrates are built inside the substrate, are being actively researched. However, as for the method of forming a capacitor in a substrate, there has been no publication other than that of a method of sandwiching a dielectric between opposing conductors as before.
更に、 インダク.夕やコンデンサ、 抵抗などが形成された I Cも各種機器の心臓 部として広く用いられている。 I Cの回路は、 一般的な基板以上の高周波回路で あり、 前述のようなフィル夕、 コンデンサは必須であり、 回路上に作り込まれて いる。 しかしながら個々のコンデンサに関しては、 従来通り、 対向する導体間に 誘電体を挟み込む構造のもの以外の発表は未だない。  In addition, ICs with inductors, capacitors, and resistors are widely used as the heart of various devices. The IC circuit is a high-frequency circuit more than a general board, and the filter and capacitor as described above are indispensable and built into the circuit. However, as for the individual capacitors, as before, there has been no publication other than that of a structure in which a dielectric is sandwiched between opposing conductors.
本発明の L C直列共振回路類似の発明として、 例えば特開昭 5 8— 2 1 8 0 7 号公報には、 本発明におけるコイル部分と類似の、 基板平面と垂直方向にコイル 状に回路が形成されたチップインダク夕の提案がある。 また、 特開昭 6 2—1 8 9 7 0 7号公報および特開平 4一 2 3 7 1 0 6号公報には、 本発明におけるコィ ル部分と類似の、 ¾反平面と垂直方向に回路面を持つコィルが複数層螺旋状に形 成され、 且つ絶縁層を介して隣接する回路が、 同じ向きから見た場合互いに反対 方向に巻かれた螺旋状のパターンを有し、 互いに電気的に接続されていることを 特徴とするコイルを用いたインダクタ成分が提案されている。 しかしながらこれ らの提案では、 積極的に容量成分を付与して直列共振周波数を制御する方法につ いては全く言及がない。 As an invention similar to the LC series resonance circuit of the present invention, for example, Japanese Patent Application Laid-Open No. 58-187 There is a proposal of a chip inductor having a circuit formed like a chip. Further, Japanese Patent Application Laid-Open Nos. Sho 62-187970 and JP-A-Hei 437-1706 disclose a circuit similar to the coil portion of the present invention in the direction perpendicular to the opposite plane. A coil having a plurality of surfaces is formed in a spiral shape in a plurality of layers, and adjacent circuits via an insulating layer have a spiral pattern wound in opposite directions when viewed from the same direction. An inductor component using a coil characterized by being connected has been proposed. However, none of these proposals mentions a method of controlling the series resonance frequency by positively adding a capacitance component.
本発明は、 小型で、 且つ直列共振周波数を容易に制御できる、 チヅプコンデン サ、 コンデンサ内蔵部品、 コンデンサ内蔵基板およびコンデンサ内蔵 I cチップ 用のコンデンサ成分として好適な L C直列共振回路およびその製造方法を提供す ることを課題としている。  The present invention provides a small-sized LC series resonance circuit suitable for use as a chip capacitor, a capacitor built-in component, a capacitor built-in substrate and a capacitor component for a capacitor built-in Ic chip, which can easily control the series resonance frequency, and a method of manufacturing the same. The task is to do so.
(発明の開示)  (Disclosure of the Invention)
上記課題は、 以下の特徴を有する本発明によって達成される。 すなわち、 請求 の範囲第 1項に記載の発明は、 多層基板と一体的に形成されるコイルであって、 当該多層基板に平行な巻線部分及び当該多層基板に垂直な卷線部分を含むコイル と、 当該多層基板と一体的に形成されるコンデンサであって、 当該コイルと電気 的に直列に接続されるコンデンサと、 を有し、 当該コイル及び当該コンデンサは、 当該多層基板内に支持され、 当該コイルの単位巻線は、 隣接する他の単位巻線と 同じ方向から見た場合に互いに反対方向に旋回する螺旋状のパターンをそれそれ 有し、 及び当該コイルの互いに隣接する単位巻線の組は、 当該螺旋状のパターン の先端同士又は末端同士において交互に接続されることを特徴とする。  The above object is achieved by the present invention having the following features. That is, the invention described in claim 1 is a coil formed integrally with a multilayer substrate, the coil including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. And a capacitor formed integrally with the multilayer substrate, the capacitor being electrically connected in series with the coil, wherein the coil and the capacitor are supported in the multilayer substrate, Each of the unit windings of the coil has a spiral pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings. The sets are characterized by being connected alternately at the tips or ends of the spiral pattern.
請求の範囲第 2項に記載の発明は、 多層基板と一体的に形成されるコイルであ つて、 当該多層基板に平行な卷線部分及び当該多層基板に垂直な卷線部分を含む コイルと、 当該多層基板と一体的に形成されるコンデンサであって、 当該コイル と電気的に直列に接続されるコンデンサと、 当該コイルの内部を貫通する柱状の 磁性体からなる芯構造と、 を有し、 当該コイル、 当該コンデンサ及び当該芯構造 は、 当該多層基板内に支持されることを特徴とする。 The invention described in claim 2 is a coil formed integrally with the multilayer substrate, wherein the coil includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. A capacitor formed integrally with the multilayer substrate, wherein the coil is And a core structure made of a columnar magnetic material penetrating the inside of the coil, and the coil, the capacitor and the core structure are supported in the multilayer substrate. It is characterized by being performed.
請求の範囲第 3項に記載の発明は、 請求の範囲第 2項に記載の発明の特徴に加 えて、 当該コイルの単位卷線は、 隣接する他の単位巻線と同じ方向から見た場合 に互いに反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び当該コイル の互いに隣接する単位巻線の組は、 当該螺旋状のパターンの先端同士又は末端同 士において交互に接続されることを特徴とする  The invention described in claim 3 has the feature of the invention described in claim 2 in addition to the case where the unit winding of the coil is viewed from the same direction as another adjacent unit winding. Each of the coils has a spiral pattern that turns in the opposite direction, and the sets of adjacent unit windings of the coil are connected alternately at the tips of the spiral pattern or at the ends thereof. Characterized by
請求の範囲第 4項に記載の発明は、 請求の範囲第 1乃至 3項のいずれか 1項に 記載の発明の特徴に加えて、 当該コイルは、 当該多層基板に平行な卷線部分が、 積層された導電層の一部として形成され、 当該多層基板に垂直な巻線部分が、 当 該絶縁層を介して隣接する当該導電層間を接続するバンプとして形成されること を特徴とする。  The invention described in claim 4 has the feature that, in addition to the features of the invention described in any one of claims 1 to 3, the coil has a winding portion parallel to the multilayer substrate. It is formed as a part of a stacked conductive layer, and a winding portion perpendicular to the multilayer substrate is formed as a bump connecting the adjacent conductive layer via the insulating layer.
請求の範囲第 5項に記載の発明は、 請求の範囲第 1乃至 3項のいずれか 1項に 記載の発明の特徴に加えて、 当該コイルは、 ビルドアップ工法により、 当該多層 基板に平行な巻線部分が、 積層された導電層の一部として形成され、 当該多層基 板に垂直な卷線部分が、 当該絶縁層を通して隣接する当該導電層間を接続するビ ァ或いはスルーホールとして形成されることを特徴とする。  The invention set forth in claim 5 is characterized in that, in addition to the features of the invention set forth in any one of claims 1 to 3, the coil is formed parallel to the multilayer substrate by a build-up method. A winding portion is formed as a part of the stacked conductive layers, and a winding portion perpendicular to the multilayer substrate is formed as a via or a through hole connecting the adjacent conductive layers through the insulating layer. It is characterized by the following.
請求の範囲第 6項に記載の発明は、 請求の範囲第 1乃至 5項のいずれか 1項に 記載の発明の特徴に加えて、 当該多層基板の絶縁層に有機素材を使用することを 特徴とする。  The invention described in claim 6 is characterized in that, in addition to the features of the invention described in any one of claims 1 to 5, an organic material is used for the insulating layer of the multilayer substrate. And
請求の範囲第 7項に記載の発明は、 請求の範囲第 1乃至 6項のいずれか 1項に 記載の発明の特徴に加えて、 当該コンデンサを構成する誘電体にセラミックを使 用することを特徴とする。  The invention set forth in claim 7 provides, in addition to the features of the invention set forth in any one of claims 1 to 6, the use of ceramic for the dielectric constituting the capacitor. Features.
請求の範囲第 8項に記載の発明は、 請求の範囲第 1乃至 7項のいずれか 1項に PC謂裏 49 記載の発明の特徴に加えて、 当該コンデンサを構成する誘電体が焼成された高誘 電セラミックからなることを特徴とする。 The invention described in claim 8 is defined in any one of claims 1 to 7 In addition to the features of the invention described in PC so-called back 49, the dielectric constituting the capacitor is made of fired high dielectric ceramic.
請求の範囲第 9項に記載の発明は、 請求の範囲第 1乃至 6項のいずれか 1項に 記載の発明の特徴に加えて、 当該コンデンサを構成する誘電体が高誘電セラミツ クの粉末或いはウイスカ一を含有する有機素材からなることを特徴とする。  The invention described in claim 9 is characterized in that, in addition to the features of the invention described in any one of claims 1 to 6, the dielectric constituting the capacitor is a powder of high dielectric ceramic or It is made of an organic material containing whisker.
請求の範囲第 1 0項に記載の発明は、 請求の範囲第 8又は 9項に記載の発明の 特徴に加えて、 当該高誘電セラミヅクが、 チタン酸バリウム、 チタン酸ストロン チウムの内の少なくとも一種を含有することを特徴とする。  The invention described in claim 10 is characterized in that, in addition to the features of the invention described in claim 8 or 9, the high dielectric ceramic is at least one of barium titanate and strontium titanate. It is characterized by containing.
請求の範囲第 1 1項に記載の発明は、 請求の範囲第 1乃至 1 0項のいずれか 1 項に記載の L C直列共振回路と、 当該多層基板と、 当該多層基板と一体的に形成 され、 当該多層基板内に支持された他の回路と、 を有することを特徴とする。 請求の範囲第 1 2項に記載の発明は、 請求の範囲第 1乃至 1 0項のいずれか 1 項に記載の多層基板内 L C直列共振回路を含んでおり、 半導体チップの外面に積 層され、 当該半導体チップの特定の箇所との間で電気的に接続されたことを特徴 とする。  The invention described in claim 11 is formed integrally with the LC series resonance circuit according to any one of claims 1 to 10, the multilayer substrate, and the multilayer substrate. And another circuit supported in the multilayer substrate. The invention described in claim 12 includes the LC series resonance circuit in a multilayer substrate according to any one of claims 1 to 10, and is laminated on an outer surface of a semiconductor chip. The semiconductor chip is electrically connected to a specific portion of the semiconductor chip.
請求の範囲第 1 3項に記載の発明は、 請求の範囲第 1 1項に言 3載の発明の特徴 に加えて、 半導体チヅプの外面に積層され、 当該半導体チップの特定の箇所との 間で電気的に接続されたことを特徴とする。  The invention set forth in claim 13 is characterized in that, in addition to the features of the invention described in claim 3 of claim 11, the invention is laminated on the outer surface of the semiconductor chip, and is arranged between a specific portion of the semiconductor chip. And are electrically connected.
請求の範囲第 1 4項に記載の発明は、 多層基板を構成する 1つの絶縁層を形成 するステップと、 コンデンサを当該多層 反内に形成するステップと、 当該多層 基板に平行なコイルの卷線部分の少なくとも一部を当該多層基板内の絶縁層上に 形成するステップと、 当該多層基板に平行なコイルの当該卷線部分の少なくとも 一部同士を絶縁層間で電気的に接続する垂直接続部を形成し、 それによつて当該 多層基板に垂直なコイルの卷線部分の少なくとも一部を形成するステップと、 当 該コンデンサと当該コィルとが電気的に直列に接続されるように、 それらの間を 電気的に接続するステップと、 The invention described in claim 14 is a step of forming one insulating layer constituting the multilayer substrate, a step of forming a capacitor inside the multilayer substrate, and a winding of a coil parallel to the multilayer substrate. Forming at least a portion of the portion on the insulating layer in the multilayer substrate; and forming a vertical connection portion for electrically connecting at least a portion of the winding portion of the coil parallel to the multilayer substrate between the insulating layers. Forming at least a part of a winding portion of a coil perpendicular to the multilayer substrate, and connecting the capacitor and the coil so that they are electrically connected in series. Electrically connecting;
絶縁層を形成する当該ステヅプ、 当該多層基板に平行なコィルの卷線部分の少な くとも一部を形成する当該ステップ、 及び当該多層 ¾反に垂直なコイルの卷線部 分の少なくとも一部を形成する当該ステップの少なくともいずれかを、 当該多層 基板に平行なコィルの卷線部分と当該多層基板に垂直なコィルの卷線部分とで当 該多層基板内に支持される所定のコイルが形成されるまで、 それまでに形成され た多層基板の部分に対して適宜反復するステップと、 を具備し、 The step of forming an insulating layer, the step of forming at least a part of a winding portion of a coil parallel to the multilayer substrate, and at least a part of a winding portion of a coil perpendicular to the multilayer structure. A predetermined coil supported in the multilayer substrate is formed by a coil winding portion parallel to the multilayer substrate and a coil winding portion perpendicular to the multilayer substrate in at least one of the forming steps. And repeating steps as appropriate for the part of the multilayer substrate formed up to that point.
当該所定のコィルの単位卷線は、 隣接する他の単位卷線と同じ方向から見た場合 に互いに反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び当該所定の コィルの互いに隣接する単位卷線の組は、 当該螺旋状のパターンの先端同士又は 末端同士において交互に接続されることを特徴とする。 The unit windings of the predetermined coil each have a spiral pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings, and the unit windings of the predetermined coil are adjacent to each other. The set of unit windings is characterized by being connected alternately at the ends or ends of the spiral pattern.
請求の範囲第 1 5項に記載の発明は、 多層基板を構成する 1つの絶縁層を形成 するステップと、 コンデンサを当該多層基板内に形成するステップと、 当該多層 基板に平行なコィルの卷線部分の少なくとも一部を当該多層基板内の絶縁層上に 形成するステップと、 当該多層 ¾反に平行なコイルの当該巻線部分の少なくとも 一部同士を絶縁層間で電気的に接続する垂直接続部を形成し、 それによつて当該 多層基板に垂直なコイルの卷線部分の少なくとも一部を形成するステップと、 当 該コンデンサと当該コイルとが電気的に直列に接続されるように、 それらの間を 電気的に接続するステップと、 柱状の磁性体からなる芯構造を当該コイルの内部 に配置されるように形成するステップと、  The invention according to claim 15 includes a step of forming one insulating layer constituting the multilayer substrate, a step of forming a capacitor in the multilayer substrate, and a winding of a coil parallel to the multilayer substrate. Forming at least a portion of the portion on an insulating layer in the multilayer substrate; and a vertical connection portion for electrically connecting at least a portion of the winding portion of the multilayer antiparallel coil between the insulating layers. Forming at least a part of a winding portion of a coil perpendicular to the multilayer substrate; and forming a capacitor between the capacitor and the coil so as to be electrically connected in series. Electrically connecting to each other; and forming a core structure made of a columnar magnetic material so as to be disposed inside the coil.
絶縁層を形成する当該ステヅプ、 当該多層基板に平行なコィルの卷線部分の少な くとも一部を形成する当該ステップ、 及び当該多層基板に垂直なコイルの卷線部 分の少なくとも一部を形成する当該ステップの少なくともいずれかを、 当該多層 基板に平行なコィルの卷線部分と当該多層基板に垂直なコィルの卷線部分とで当 該多層基板内に支持される所定のコイルが形成されるまで、 それまでに形成され た多層基板の部分に対して適宜反復するステップと、 を有することを特徴とする。 請求の範囲第 1 6項に記載の発明は、 請求の範囲第 1 4又は 1 5項に記載の発 明の特徴に加えて、 当該垂直接続部は当該絶縁層を介して隣接する当該導電層間 を接続するバンプであることを特徴とする。 The step of forming an insulating layer, the step of forming at least a part of a coil winding part parallel to the multilayer substrate, and the forming of at least a part of a coil winding part perpendicular to the multilayer substrate. A predetermined coil supported in the multilayer substrate is formed by the winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate. Until it is formed Repeating the steps as appropriate for the portion of the multi-layer substrate. The invention set forth in claim 16 may include, in addition to the features of the invention set forth in claim 14 or 15, the vertical connection portion may be adjacent to the conductive layer via the insulating layer. Are connected to each other.
請求の範囲第 1 7項に記載の発明は、 請求の範囲第 1 4又は 1 5項に記載の発 明の特徴に加えて、 当該ステップの少なくともいずれかはビルドァップ工法によ つて実施され、 及び  The invention described in Claim 17 provides, in addition to the features of the invention described in Claims 14 or 15, at least one of the steps is performed by a build-up method, and
当該垂直接続部は当該絶縁層を通して隣接する当該導電層間を接続するビア或い はスルーホールであることを特徴とする。 The vertical connection portion is a via or a through hole connecting the adjacent conductive layers through the insulating layer.
請求の範囲第 1 8項に記載の発明は、 請求の範囲第 1 4乃至 1 7項のいずれか 1項に記載の発明の特徴に加えて、 当該多層基板の絶縁層に有機素材を使用する ことを特徴とする。  The invention described in claim 18 uses an organic material for the insulating layer of the multilayer substrate in addition to the features of the invention described in any one of claims 14 to 17. It is characterized by the following.
請求の範囲第 1 9項に記載の発明は、 請求の範囲第 1 4乃至 1 8項のいずれか 1項に記載の発明の特徴に加えて、 当該コンデンサを構成する誘電体にセラミツ クを使用することを特徴とする。  The invention described in claim 19 is characterized in that, in addition to the features of the invention described in any one of claims 14 to 18, a ceramic is used for the dielectric material constituting the capacitor. It is characterized by doing.
請求の範囲第 2 0項に記載の発明は、 請求の範囲第 1 4乃至 1 9項のいずれか 1項に記載の発明の特徴に加えて、 当該コンデンサを構成する誘電体が焼成され た高誘電セラミックからなることを特徴とする。  The invention set forth in claim 20 is characterized in that, in addition to the features of the invention set forth in any one of claims 14 to 19, the dielectric material constituting the capacitor is fired. It is characterized by being made of dielectric ceramic.
請求の範囲第 2 1項に記載の発明は、 請求の範囲第 1 4乃至 1 8項のいずれか 1項に記載の発明の特徴に加えて、 当該コンデンサを構成する誘電体が高誘電セ ラミックの粉末或いはウイスカ一を含有する有機素材からなることを特徴とする。 請求の範囲第 2 2項に記載の発明は、 請求の範囲第 2 0又は 2 1項に記載の発 明の特徴に加えて、 当該高誘電セラミックが、 チタン酸バリウム、 チタン酸スト 口ンチウムの内の少なくとも一種を含有することを特徴とする。  The invention described in claim 21 is characterized in that, in addition to the features of the invention described in any one of claims 14 to 18, the dielectric constituting the capacitor is a high dielectric ceramic. Or an organic material containing whisker. The invention set forth in claim 22 is the invention according to claim 20 or 21, wherein the high dielectric ceramic is made of barium titanate or sodium titanium titanate. It is characterized by containing at least one of the above.
請求の範囲第 2 3項に記載の発明は、 請求の範囲第 1 4乃至 2 2項のいずれか 1項に記載の L C直列共振回路の製造方法のステヅプを有し、 当該多層 ¾ί反と一 体的に、 当該多層 ¾反内に支持される他の回路を形成するステップ、 を更に有す ることを特徴とする。 The invention described in claim 23 is any one of claims 14 to 22. 2. The method according to claim 1, further comprising the step of forming another circuit supported in the multilayer substrate integrally with the multilayer substrate. It is characterized by the following.
請求の範囲第 2 4項に記載の発明は、 請求の範囲第 1 4乃至 2 2項のいずれか 1項に記載の L C直列共振回路の製造方法のステヅプを含んでおり、 当該 L C直 列共振回路内蔵基板は半導体ゥェ一ハの外面に積層されるものであり、 当該 L C 直列共振回路内蔵基板を当該半導体チヅプの特定の箇所との間で電気的に接続す るステツプと、 当該 L C直列共振回路内蔵基板が積層された当該半導体ゥエーハ を半導体チップ単位に切り分けるステップと、 を更に有することを特徴とする。 請求の範囲第 2 5項に記載の発明は、 請求の範囲第 2 3項に記載の発明の特徴 に加えて、 当該 L C直列共振回路内蔵基板は半導体ゥェ一ハの外面に積層される - ものであり、 当該 L C直列共振回路内蔵基板を当該半導体チヅプの特定の箇所と の間で電気的に接続するステヅプと、 当該 L C直列共振回路内蔵 ¾反が積層され た当該半導体ゥヱ一八を半導体チヅプ単位に切り分けるステツプと、 を更に有す ることを特徴とする。  The invention described in claim 24 includes a step of the method for manufacturing an LC series resonance circuit according to any one of claims 14 to 22, wherein the LC series resonance circuit is provided. The substrate with a built-in circuit is laminated on the outer surface of the semiconductor wafer, and a step for electrically connecting the substrate with a built-in LC series resonance circuit to a specific portion of the semiconductor chip; Separating the semiconductor wafer on which the substrate with a built-in resonance circuit is laminated in units of semiconductor chips. The invention described in claim 25 has the feature of the invention described in claim 23, and furthermore, the substrate with a built-in LC series resonance circuit is laminated on the outer surface of the semiconductor wafer. A step of electrically connecting the substrate with a built-in LC series resonance circuit to a specific portion of the semiconductor chip; and a step of electrically connecting the substrate with a built-in LC series resonance circuit to the semiconductor. And a step of dividing into semiconductor chip units.
請求の範囲第 2 6項に記載の発明は、 請求の範囲第 1 4乃至 2 2項のいずれか 1項に記載の L C直列共振回路の製造方法のステップを含んでおり、 当該 L C直 列共振回路は半導体チップの外面に積層されるものであり、 当該 L C直列共振回 路を当該半導体チヅプの特定の箇所との間で電気的に接続するステヅプ、 を更に 有することを特徴とする。  The invention set forth in claim 26 includes a step of the method for manufacturing an LC series resonance circuit according to any one of claims 14 to 22, wherein the LC series resonance circuit is provided. The circuit is stacked on the outer surface of the semiconductor chip, and further includes a step of electrically connecting the LC series resonance circuit to a specific portion of the semiconductor chip.
請求の範囲第 2 7項に記載の発明は、 請求の範囲第 2 3項に記載の L C直列共 振回路内蔵多層基板の製造方法のステップを含んでおり、 当該 L C直列共振回路 内蔵基板は半導体チヅプの外面に積層されるものであり、 当該 L C直列共振回路 内蔵 ¾反を当該半導体チヅプの特定の箇所との間で電気的に接続するステヅプ、 を更に有することを特徴とする。 なお、 本明細書における先端及び末端の用語は、 螺旋状のパターンのいずれか 一端、 ここでは最も内側の一端を基準にして、 最も内側の端を先端、 最も外側の 端を末端と言うものとする。 また、 本明細書における平行、 垂直などの位置関係 を表わす用語は、 幾何学的な厳密さまでは要求しておらず、 実質的にそのような 位置関係であれば足りるという程度の意味である。 The invention set forth in claim 27 includes a step of the method for manufacturing a multilayer substrate with built-in LC series resonance circuit according to claim 23, wherein the substrate with built-in LC series resonance circuit is a semiconductor. A step of being stacked on the outer surface of the chip, further comprising: a step of electrically connecting the built-in LC series resonance circuit to a specific portion of the semiconductor chip. Note that the terms tip and end in this specification refer to either one end of the spiral pattern, here the innermost end is the tip, and the outermost end is the end, based on the innermost end. I do. Further, in the present specification, terms representing positional relationships such as parallel and vertical are not required to be strictly geometrical, and have a meaning that such positional relationships are sufficient.
本発明の L C直列共振回路はその構造から明らかなように、 積極的にィンダク 夕成分が付加されており、 その大きさを自由に調整することができ、 その結果、 かかる L C直列共振回路の直列共振周波数を簡便に制御する事が可能となる。  As is clear from the structure, the LC series resonance circuit of the present invention has an active component added to it, and its size can be freely adjusted. As a result, the series connection of such LC series resonance circuit The resonance frequency can be easily controlled.
(図面の簡単な説明)  (Brief description of drawings)
図 1 (a) は本発明の第 1の実施形態にかかる LC直列共振回路の斜視概念図 であり、 図 1 (b)は本発明の第 2の実施形態にかかる LC直列共振回路の斜視 概念図であり、 図 1 (c) は本発明の第 3の実施形態にかかる LC直列共振回路 の斜視概念図であり、 図 1 (d)及び図 1 (e) は、 他のコイルの構造の例を示 す図である。  FIG. 1A is a perspective conceptual view of an LC series resonance circuit according to the first embodiment of the present invention, and FIG. 1B is a perspective conceptual view of the LC series resonance circuit according to the second embodiment of the present invention. Fig. 1 (c) is a perspective conceptual view of an LC series resonance circuit according to a third embodiment of the present invention, and Figs. 1 (d) and 1 (e) show the structure of another coil. It is a figure showing an example.
図 2 (a) は本発明の第 4の実施形態にかかる LC直列共振回路の斜視概念図 であり、 図 2 (b) は本発明の第 5の実施形態にかかる LC直列共振回路の斜視 概念図であり、 図 2 (c) は本発明の第 6の実施形態にかかる LC直列共振回路 の斜視概念図である。  FIG. 2A is a perspective conceptual view of the LC series resonance circuit according to the fourth embodiment of the present invention, and FIG. 2B is a perspective conceptual view of the LC series resonance circuit according to the fifth embodiment of the present invention. FIG. 2C is a conceptual perspective view of an LC series resonance circuit according to a sixth embodiment of the present invention.
図 3は、 本発明の第 1の実施形態にかかる L C直列共振回路の製造初段階の斜 視概念図である。  FIG. 3 is a conceptual perspective view of an LC series resonance circuit according to the first embodiment of the present invention at an initial stage of manufacturing.
図 4は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を示 す斜視概念図である。  FIG. 4 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 5は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を示 す斜視概念図である。  FIG. 5 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 6は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を示  FIG. 6 shows an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
9 6649 す斜視概念図である。 9 FIG. 6649 is a perspective conceptual view.
図 Ίは、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を示 す斜ネ見概念図である。  FIG. 2 is a schematic perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 8は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を示 す斜視概念図である。  FIG. 8 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 9は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を示 す斜視概念図である。  FIG. 9 is a perspective conceptual view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 1 0は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を 示す斜視概念図である。  FIG. 10 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 1 1は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を 示す斜視概念図である。  FIG. 11 is a perspective conceptual view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 1 2は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を 示す斜視概念図である。  FIG. 12 is a conceptual perspective view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 1 3は、 本発明の第 1の実施形態にかかる L C直列共振回路の製法の一例を 示す斜視概念図である。  FIG. 13 is a perspective conceptual view showing an example of a method for manufacturing an LC series resonance circuit according to the first embodiment of the present invention.
図 1 4は、 本発明の第 1の実施形態にかかる L C直列共振回路の ICチップ上へ の製造初段階の断面図である。  FIG. 14 is a cross-sectional view of an LC series resonance circuit according to the first embodiment of the present invention at an initial stage of manufacturing on an IC chip.
図 1 5は、 ビア形成の説明のための断面図である。  FIG. 15 is a cross-sectional view for explaining via formation.
図 1 6は、 回路形成のための導電パターン形成の説明のための断面図である。 図 1 7は、 第 2の絶縁層形成の説明のための断面図である。 ' .  FIG. 16 is a cross-sectional view for explaining formation of a conductive pattern for forming a circuit. FIG. 17 is a cross-sectional view for explaining the formation of the second insulating layer. '.
図 1 8は、 第 2の導電パターン形成の説明のための断面図である。  FIG. 18 is a cross-sectional view for explaining the formation of the second conductive pattern.
図 1 9は、 第 3層形成の説明のための断面図である。  FIG. 19 is a cross-sectional view for explaining formation of the third layer.
図 2 0は、 I Cチップ上に形成された本発明の第 1の実施形態にかかる L C直 列共振回路の断面概念図である。  FIG. 20 is a conceptual sectional view of an LC series resonance circuit formed on an IC chip according to the first embodiment of the present invention.
図 2 1は、 ビアの断面概念図である。 図 2 2は、 I Cチップ上に形成された本発明の第 1の実施形態にかかる L C直 列共振回路の一例を示す断面概念図である。 FIG. 21 is a conceptual diagram of a cross section of a via. FIG. 22 is a conceptual sectional view showing an example of an LC series resonance circuit formed on an IC chip according to the first embodiment of the present invention.
図 2 3は、 I Cチヅプ上に形成された本発明の第 1の実施形態にかかる L C直 列共振回路の一例を示す断面概念図である。  FIG. 23 is a conceptual cross-sectional view showing an example of an LC series resonance circuit formed on an IC chip according to the first embodiment of the present invention.
図 2 4は、 本発明の実施例にかかる L C直列共振回路のコイルとコンデンサの 平面図である。  FIG. 24 is a plan view of a coil and a capacitor of the LC series resonance circuit according to the embodiment of the present invention.
図 2 5は、 本発明の実施例にかかる L C直列共振回路の A— A矢視横断面図で める。  FIG. 25 is a cross-sectional view of the LC series resonance circuit according to the embodiment of the present invention, taken along the line AA.
図 2 6は、 本発明の実施例にかかる L C直列共振回路のコイルの斜視図である。 図 2 7は、 本発明の実施例にかかる L C直列共振回路のコイルのリアクタンス 成分の周波数特性を表わすグラフである。  FIG. 26 is a perspective view of a coil of the LC series resonance circuit according to the embodiment of the present invention. FIG. 27 is a graph illustrating a frequency characteristic of a reactance component of a coil of the LC series resonance circuit according to the embodiment of the present invention.
図 2 8は、 本発明の実施例にかかる L C直列共振回路のコンデンザの斜視図で ある。  FIG. 28 is a perspective view of a capacitor of the LC series resonance circuit according to the embodiment of the present invention.
図 2 9は、 本発明の実施例にかかる L C直列共振回路のコンデンサのリアクタ ンス成分の周波数特性を表わすグ'ラフである。  FIG. 29 is a graph showing the frequency characteristic of the reactance component of the capacitor of the LC series resonance circuit according to the embodiment of the present invention.
図 3 0は、 本発明の実施例にかかる L C直列共振回路の平面図である。  FIG. 30 is a plan view of the LC series resonance circuit according to the embodiment of the present invention.
図 3 1は、 本発明の実施例にかかる L C直列共振回路の斜視図である。  FIG. 31 is a perspective view of the LC series resonance circuit according to the embodiment of the present invention.
図 3 2は、 本発明の実施例にかかる L C直列共振回路のリアクタンス成分の周 波数特性を表わすグラフである。  FIG. 32 is a graph illustrating a frequency characteristic of a reactance component of the LC series resonance circuit according to the example of the present invention.
図 3 3は、 L C直列共振回路の回路図及び電流の周波数特性を表わすグラフで ある。  FIG. 33 is a circuit diagram of an LC series resonance circuit and a graph showing frequency characteristics of a current.
(発明を実施するための最良の形態)  (Best mode for carrying out the invention)
以下、 本発明の実施の形態について、 図面を参照しながら説明していく。 また、 本発明の L C直列共振回路を高周波回路などに使用する場合の利点についても説 明する。 これから本発明の第 1の実施形態に係る L C直列共振回路 1 0 0の構成 画裏 649 について説明する。 図 1 ( a ) は、 L C直列共振回路 1 0 0の概略構成を示す斜 視概念図である。 L C直列共振回路 1 0 0は、 コイル 1 0 0 a、 コンデンサ 1 0 0 c、 接続点 1 0 0 f及び 1 0 0 g、 及び多層基板 1 0 O hから構成される。 コ ィル 1 0 0 aは、 多層 における複数の絶縁層及び導電層のそれぞれの形成ス テツプにおいて導電層の一部として形成される、 インダク夕ンスを与える構成要 素である。 中心軸が多層基板に平行なこのようなコイルを 「縦型コイル」 と称す ることにする。 コイル 1 0 0 aは、 好適には、 断 形状が四角形、 円形等の導線 の繰り返されるパターンである単位卷線 1 0 O bが、 電気的に直列に連続して接 続された形態で構成される。 本明細書におけるコイル 1 0 0 a及び単位巻線 1 0 0 bの形態は、 インダク夕ンスを与えるためのいかなる形態も広く含むものとす る。 好適には、 コイル 1 0 0 aの多層 ¾反に平行な卷線部分は、 積層される導電 層の一部として形成され、 多層基板に垂直な卷線部分は、 絶縁層を介して隣接す る導電層間を接続するバンプ、 ビア或いはスル一ホールなどとして形成される。 このようにしてコィノレ 1 0 0 aを形成することにより、 ビルドアップ工法などの 公知の多層基板 (プリント基板)形成技術を利用して、 多層基板の製造工程にお いてコイル 1 0 0 aを多層 内に同時に形成することが可能となる。 コイル 1 0 0 aは、 多層基板 1 0 0 hに平行な巻線部分及び当該多層基板に垂直な卷線部 分を含む。 コンデンサ 1 0 0 cは、 対向する 2枚の極板 1 0 0 dと、 それらに挟 まれる誘電体 1 0 0 eとから構成される。 なお、 コンデンサの容量をさらに増大 させることが必要な場合には、 一般の積層コンデンサで用いられているような、 対向する櫛形の電極からなる極板と、 その間に挟まれる多層の誘電体とから構成 されるコンデンサであってもよい。極板 1 0 0 dは、 好適には、 多層基板におけ る複数の絶縁層及び導電層のそれそれの形成ステツプにおいて導電層の一部とし て形成される。誘電体 1 0 0 eは、 多層纖反 1 0 0 hを構成する絶縁材料と同じ 材質でもよく、 また、 誘電率、 費用、 製造工程等を考慮して、 多層基板 1 0 O h を構成する絶縁材料と異なる材質であってもよい。接続点 1 0 O fは、 コイル 1 0 0 aの一端と極板 1 0 0 dの一方とを電気的に接続する接点である。接続点 1 0 0 g l 外部へと向かう配線と極板 1 0 0 dの他方とを電気的に接続する接点 である。 このように接続すると、 コンデンサ 1 0 0 cとコイル 1 0 0 aとが電気 的に直列に接続され、 それらは併せて L C直列共振回路を構成する。 コイル 1 0 0 aの他端には、 当該 L C直列共振回路から外部へと向かう配線が接続される。 多層基板 1 0 O hは、 絶縁層を積層させて構成される基板である。 なお、 実際の 多層基板 1 0 O hの形成ステップでは、 絶縁層と導電層とが交互に積層させられ る。 そして、 導電層の部分は前述のコイル 1 0 0 aの一部となり、 他の絶縁層の 部分は多層基板 1 0 O hとなる。 なお、 L C直列共振回路 1 0 0は、 そのような L C直列共振回路を含む多層基板全体を意味するのではなく、 多層基板内に保持 されたことを特徴とする、 そのような L C直列共振回路を意味する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The advantages of using the LC series resonance circuit of the present invention in a high-frequency circuit or the like will also be described. The configuration of the LC series resonance circuit 100 according to the first embodiment of the present invention will now be described. The back of the picture 649 will be described. FIG. 1A is a conceptual perspective view showing a schematic configuration of the LC series resonance circuit 100. The LC series resonance circuit 100 is composed of a coil 100a, a capacitor 100c, connection points 100f and 100g, and a multilayer substrate 100h. The coil 100a is a component that gives an inductance and is formed as a part of the conductive layer in each step of forming the plurality of insulating layers and conductive layers in the multilayer. Such a coil whose central axis is parallel to the multilayer substrate is called a “vertical coil”. The coil 100a is preferably configured in such a manner that a unit winding 100 Ob having a repeating pattern of a conducting wire having a rectangular or circular cross section is electrically and continuously connected in series. Is done. The form of the coil 100a and the unit winding 100b in the present specification is intended to broadly include any form for providing inductance. Preferably, a winding portion of the coil 100a parallel to the multilayer is formed as a part of a conductive layer to be stacked, and a winding portion perpendicular to the multilayer substrate is adjacent to the multilayer substrate via an insulating layer. It is formed as a bump, a via, a through hole, or the like connecting the conductive layers. By forming the coil 100a in this manner, the coil 100a is formed in a multilayer board manufacturing process by using a known multilayer board (printed board) forming technique such as a build-up method. At the same time. The coil 100a includes a winding portion parallel to the multilayer substrate 100h and a winding portion perpendicular to the multilayer substrate. The capacitor 100c is composed of two opposing electrode plates 100d and a dielectric material 100e sandwiched therebetween. When it is necessary to further increase the capacitance of the capacitor, the electrode plate consisting of opposing comb-shaped electrodes and a multi-layer dielectric sandwiched between them, as used in a general multilayer capacitor, are used. It may be a configured capacitor. The electrode plate 100d is preferably formed as a part of the conductive layer in the step of forming each of the plurality of insulating layers and the conductive layer in the multilayer substrate. The dielectric 100 e may be the same material as the insulating material composing the multilayer fiber 100 h, and in consideration of the dielectric constant, cost, manufacturing process, etc., the multilayer substrate 100 h May be different from the insulating material constituting the material. The connection point 100Of is a contact point for electrically connecting one end of the coil 100a and one of the electrode plates 100d. Connection point 100 gl This is a contact for electrically connecting the wiring going to the outside and the other of the electrode plates 100 d. When connected in this way, the capacitor 100c and the coil 100a are electrically connected in series, and together form an LC series resonance circuit. The other end of the coil 100a is connected to a wire extending from the LC series resonance circuit to the outside. The multilayer substrate 10 Oh is a substrate configured by laminating insulating layers. In the actual step of forming the multilayer substrate 10 Oh, insulating layers and conductive layers are alternately laminated. The portion of the conductive layer becomes a part of the coil 100a, and the portion of the other insulating layer becomes the multilayer substrate 100 Oh. The LC series resonance circuit 100 does not mean the entire multilayer substrate including such an LC series resonance circuit, but is characterized by being held in the multilayer substrate. Means
次に、 本発明の第 2の実施形態に係る L C直列共振回路 1 2 0の構成について 説明する。 図 1 ( b) は、 L C直列共振回路 1 2 0の概略構成を示す斜視概念図 である。 L C直列共振回路 1 2 0は、 L C直列共振回路 1 0 0において、 コンデ ンサ 1 0 0 cをコイル 1 0 0 aの外側に配置したような構造を有している。 L C 直列共振回路 1 2 0の各構成要素は、 L C直列共振回路 1 0 0において符号の数 字部分を 1 0 0から 1 2 0に替えた構成要素と対応している。 なお、 L C直列共 振回路 1 0 0のように、 コイル 1 0 0 aの内部にコンデンサ 1 0 0 cが配置され るような構造では、 集積度を上げて、 全体の厚みを薄くしゃすいという利点があ る。 また、 単位巻線 1 0 0 bの面積を大きくして、 より大きいインダク夕ンスの コイル 1 0 0 aを形成しやすいという利点がある。 一方、 L C直列共振回路 1 2 0のように、 コイル 1 2 0 aの外部にコンデンサ 1 2 0 cが配置されるような構 造では、 コイル 1 2 0 cの部分を積層するときの工程を単純にすることができる という利点がある。 また、 コンデンサ 1 2 0 cが多層基板 1 2 O hの外面付近に 位置するため、 極板 1 2 0 cにレーザなどで穴あけなどのトリミングをしてその 面積を調節することによって、 静電容量を微調整することもできる。 Next, the configuration of the LC series resonance circuit 120 according to the second embodiment of the present invention will be described. FIG. 1B is a conceptual perspective view showing a schematic configuration of the LC series resonance circuit 120. The LC series resonance circuit 120 has a structure in which the capacitor 100c is arranged outside the coil 100a in the LC series resonance circuit 100. Each component of the LC series resonance circuit 120 corresponds to a component of the LC series resonance circuit 100 whose reference numeral is changed from 100 to 120. In the structure where the capacitor 100c is placed inside the coil 100a, as in the LC series resonance circuit 100, it is said that the overall thickness is thinner and thinner by increasing the degree of integration. There are advantages. In addition, there is an advantage that the area of the unit winding 100b is increased to easily form the coil 100a having a larger inductance. On the other hand, in a structure such as the LC series resonance circuit 120 in which the capacitor 120c is disposed outside the coil 120a, the process of laminating the coil 120c is omitted. The advantage is that it can be simplified. In addition, the capacitor 120 c is located near the outer surface of the multilayer substrate 12 Oh. Since it is located, it is possible to fine-tune the capacitance by trimming the electrode plate 120c with laser or the like and adjusting the area.
その次に、 本発明の第 3の実施形態に係る L C直列共振回路 1 4 0の構成につ いて説明する。 図 1 ( c ) は、 L C直列共振回路 1 4 0の概略構成を示す斜視概 念図である。 L C直列共振回路 1 4 0は、 L C直列共振回路 1 2 0において、 磁 性体 1 4 0 iをコイル 1 2 0 aの内部に配置したような構造を有している。 L C 直列共振回路 1 4 0の各構成要素は、 L C直列共振回路 1 2 0において符号の数 字部分を 1 2 0から 1 4 0に替えた構成要素と対応している。 このように、 コィ ル 1 4 0 aの内部に磁性体 1 4 0 iが配置されているため、 コイル 1 4 0 aのィ ンダク夕ンスを大きくすることができるという利点がある。 なお、 本発明の第 1 の実施形態に係る L C直列共振回路 1 0 0のコイル 1 0 0 aの内部に磁性体を配 置したような構成も可能である。 この場合、 コンデンサの上側、 下側、 又は両側 に磁性体を配置することができる。 図 1 ( d ) 及び (e ) は、 他のコイルの構造 の例である。 これらの例では、 コイルの中心軸に平行又は直交する方向の卷線部 分のみでコイルが構成されている。  Next, the configuration of the LC series resonance circuit 140 according to the third embodiment of the present invention will be described. FIG. 1C is a perspective conceptual view showing a schematic configuration of the LC series resonance circuit 140. The LC series resonance circuit 140 has a structure in which the magnetic body 140i is arranged inside the coil 120a in the LC series resonance circuit 120. Each component of the LC series resonance circuit 140 corresponds to a component of the LC series resonance circuit 120 in which the numeral portion of the code is changed from 120 to 140. As described above, since the magnetic body 140i is disposed inside the coil 140a, there is an advantage that the inductance of the coil 140a can be increased. Note that a configuration in which a magnetic material is disposed inside the coil 100a of the LC series resonance circuit 100 according to the first embodiment of the present invention is also possible. In this case, a magnetic body can be arranged on the upper side, the lower side, or both sides of the capacitor. Figures 1 (d) and (e) are examples of other coil structures. In these examples, the coil is constituted only by the winding portion in the direction parallel or perpendicular to the center axis of the coil.
更に次に、 本発明の第 4の実施形態に係る L C直列共振回路 2 0 0の構成につ いて説明する。 図 2 ( a) は、 L C直列共振回路 2 0 0の概略構成を示す斜視概 念図である。 L C直列共振回路 2 0 0は、 コイル 2 0 0 a、 コンデンサ 2 0 0 c、 接続点 2 0 0 f及び 2 0 0 g、 及び多層基板 2 0 O hから構成される。 それら構 成要素の構造は、 前述の L C直列共振回路 1 0 0の場合とほぼ同じであり、 符号 も数字部分を 「1 0 0」 から 「2 0 0 j に替えただけである。 ただし、 コイル 2 0 0 aの単位卷線 2 0 O bは、 隣接する他の単位巻線と同じ方向から見た場合に 反対方向に旋回する螺旋状のパターンをそれぞれ有し、 及び互いに隣接する単位 卷線同士ほ、 当該螺旋状のパターンの先端同士又は末端同士において互いに接続 される点で、 コイル 1 0 0 aの構成と異なっている。 コイル 2 0 0 aをそのよう に構成することによって、 単位卷線内の卷数を 1より大きくすることができ、 か つ、 コイル 2 0 0 aに電流が流されるとすべての単位卷線が同じ方向の磁界を発 生するため、 インダク夕ンスを大きくすることができる。 このような構造のコィ ルを、 コイル 1 0 0 aのような単層コイルと区別して、 以下、 多層コイルと称す ることにする。 Next, the configuration of an LC series resonance circuit 200 according to a fourth embodiment of the present invention will be described. FIG. 2A is a perspective conceptual view showing a schematic configuration of the LC series resonance circuit 200. The LC series resonance circuit 200 includes a coil 200a, a capacitor 200c, connection points 200f and 200g, and a multilayer substrate 200h. The structure of these components is almost the same as that of the above-mentioned LC series resonance circuit 100, and the sign is also changed only from “100” to “200j” in the numerals. The unit windings 200 Ob of the coil 200a each have a helical pattern that turns in the opposite direction when viewed from the same direction as other adjacent unit windings. The configuration of the coil 100a is different from that of the coil 100a in that the lines are connected to each other at the tips or ends of the spiral pattern. With this configuration, the number of turns in the unit winding can be made larger than one, and when a current flows through the coil 200a, all the unit windings generate a magnetic field in the same direction. Therefore, the inductance can be increased. A coil having such a structure is distinguished from a single-layer coil such as the coil 100a, and is hereinafter referred to as a multilayer coil.
更にその次に、 本発明の第 5の実施形態に係る L C直列共振回路 2 2 0の構成 について説明する。 図 2 ( b ) は、 L C直列共振回路 2 2 0の概略構成を示す斜 視概念図である。 L C直列共振回路 2 2 0は、 L C直列共振回路 2 0 0において、 コンデンサ 2 0 0 cをコイル 2 0 0 aの外側に配置したような構造を有している。 L C直列共振回路 2 2 0の各構成要素は、 L C直列共振回路 2 0 0において符号 の数字部分を 2 0 0から 2 2 0に替えた構成要素と対応している。 なお、 L C直 列共振回路 2 0 0のように、 コイル 2 0 0 aの内部にコンデンサ 2 0 0 cが配置 されるような構造では、 集積度を上げて、 全体の厚みを薄くしゃすいという利点 がある。 また、 単位卷線 2 0 O bの磁界と鎖交する面積を大きくして、 より大き ぃィンダク夕ンスのコイル 2 0 0 aを形成しやすいという利点がある。 一方、 L C直列共振回路 2 2 0のように、 コイル 2 2 0 aの外部にコンデンサ 2 2 0 cが 配置されるような構造では、 コイル 2 2 0 cの部分を積層するときの工程を単純 にすることができ、 また、 より大きい極板面積のコンデンサ 2 2 0 cを選ぶこと ができるという利点がある。更に、 前述の L C直列共振回路 1 2 0と同様に、 コ ンデンサ 2 2 0 cの静電容量を微調整することもできる。  Next, the configuration of the LC series resonance circuit 220 according to the fifth embodiment of the present invention will be described. FIG. 2B is a schematic perspective view showing a schematic configuration of the LC series resonance circuit 220. The LC series resonance circuit 220 has a structure in which the capacitor 200c is arranged outside the coil 200a in the LC series resonance circuit 200. Each component of the LC series resonance circuit 220 corresponds to a component of the LC series resonance circuit 200 in which the numeral portion of the reference numeral is changed from 200 to 220. In a structure where the capacitor 200c is placed inside the coil 200a, as in the LC series resonance circuit 200, it is said that the overall thickness is thinner and thinner by increasing the degree of integration. There are advantages. In addition, there is an advantage that the area interlinking the magnetic field of the unit winding 200 Ob is increased to form a coil 200 a having a larger inductance. On the other hand, in a structure in which the capacitor 220c is disposed outside the coil 220a, such as the LC series resonance circuit 220, the process of laminating the coil 220c is simplified. In addition, there is an advantage that a capacitor 220c having a larger electrode plate area can be selected. Further, similarly to the above-described LC series resonance circuit 120, the capacitance of the capacitor 220c can be finely adjusted.
また更にその次に、 本発明の第 6の実施形態に係る L C直列共振回路 2 4 0の 構成について説明する。 図 2 ( c ) は、 L C直列共振回路 2 4 0の概略構成を示 す斜視概念図である。 L C直列共振回路 2 4 0は、 L C直列共振回路 2 2 0にお いて、 磁性体 2 4 0 iをコイル 2 2 0 aの内部に配置したような構造を有してい る。 L C直列共振回路 2 4 0の各構成要素は、 L C直列共振回路 2 2 0において 0306649 符号の数字部分を 220から 240に替えた構成要素と対応している。 このよう に、 コイル 240 aの内部に磁性体 240 iが配置されているため、 コイル 24 0 aのインダク夕ンスを大きくすることができるという利点がある。 なお、 本発 明の第 4の実施形態に係る LC直列共振回路 200のコイル 200 aの内部に磁 性体を配置したような構成も可能である。 この場合、 コンデンサの上側、 下側、 又は両側に磁性体を配置することができる。 Next, the configuration of the LC series resonance circuit 240 according to the sixth embodiment of the present invention will be described. FIG. 2C is a conceptual perspective view showing a schematic configuration of the LC series resonance circuit 240. The LC series resonance circuit 240 has a structure in which the magnetic body 240i is arranged inside the coil 220a in the LC series resonance circuit 220. Each component of the LC series resonance circuit 240 is [0306649] Corresponds to the component in which the numeral part of the code is changed from 220 to 240. As described above, since the magnetic material 240i is disposed inside the coil 240a, there is an advantage that the inductance of the coil 240a can be increased. Note that a configuration in which a magnetic body is disposed inside the coil 200a of the LC series resonance circuit 200 according to the fourth embodiment of the present invention is also possible. In this case, a magnetic body can be arranged on the upper side, the lower side, or both sides of the capacitor.
これから LC直列共振回路 100、 120、 140、 200、 220及び 24 0の動作について説明する。 多層基板 100 h、 12 Oh, 14 Ohs 200 ti、 22 Oh又は 24 Ohは、 モノリシヅク I Cなどを構成する半導体チヅプをその 上にマウントするインタポーザとして使用すると好適である。 また、 多層基板 1 00 h、 120 h、 140 h、 200 h、 220 h又は 240 hは、 他の回路素 子をその内部に形成又は外部にマウントすることができ、 そのような他の回路素 子と LC直列共振回路 100、 120、 140、 200、 220又は 240とで 構成される回路の機能を、 半導体チップ自身の機能に付加した半導体パヅケージ を構成することが可能になる。 このような半導体パッケージにおいて、 LC直列 共振回路 100、 120、 140、 200、 220又は 240の直列共振周波数 を自由に制御することができると、 半導体パヅケージの特性を柔軟に設定するこ とができるようになる。 本発明では、 コンデンサの構成 (極板面積、 極板間距離、 誘電体の誘電率など) を変化させることによって静電容量を変化させ、 直列共振 周波数の低下の程度を制御することができる。 すなわち、 コイル部分は共通のま ま直列共振周波数を簡便に制御できる。 更に、 コイルの伸長方向の調節により、 巻き数を簡便且つほぼ任意に設定でき、 インダク夕ンスを変化させることができ る。 また、 単位卷線が磁界と鎖交する面積を全体的あるいは部分的に調節するこ とによってもインダク夕ンスを柔軟に設定できる。 このように、 コンデンサの静 を簡便かつ自由に変化させることができるた め、 直列共振周波数を簡便かつ自由に設定することができる。 これにより、 外部 の回路から L C直列共振回路に交流電圧が印加されたときに、 電流を通過させた り、 阻止したりする周波数帯及びその程度を柔軟に設定することができる。 まず、 回路間の接続に用いられ、 直流信号のカット、 及び高周波信号の通過を 担うカヅプリングコンデンサの代替につき記す。後述するが、 本発明の L C直列 共振回路では、 インダク夕成分を簡便に、 ほぼ任意に付与できることから直列共 振周波数の制御が容易である。 したがって、 カップリングコンデンサの効果に加 え、 必要な周波数領域のみを通過させる、 いわゆるバンドパスフィル夕の効果を 発現させることができる。 The operation of the LC series resonance circuits 100, 120, 140, 200, 220 and 240 will now be described. The multilayer substrate 100 h, 12 Oh, 14 Ohs 200 Ti, 22 Oh or 24 Oh is preferably used as an interposer for mounting a semiconductor chip constituting a monolithic IC or the like thereon. Also, the multilayer board 100 h, 120 h, 140 h, 200 h, 220 h or 240 h can have other circuit elements formed inside or mounted outside, and such other circuit elements can be mounted. It is possible to configure a semiconductor package in which the function of a circuit composed of a semiconductor chip and the LC series resonance circuit 100, 120, 140, 200, 220 or 240 is added to the function of the semiconductor chip itself. In such a semiconductor package, if the series resonance frequency of the LC series resonance circuit 100, 120, 140, 200, 220, or 240 can be freely controlled, the characteristics of the semiconductor package can be flexibly set. become. In the present invention, the capacitance can be changed by changing the configuration of the capacitor (the plate area, the distance between the plates, the dielectric constant of the dielectric, etc.), and the degree of the decrease in the series resonance frequency can be controlled. That is, the series resonance frequency can be easily controlled while keeping the coil portion common. Further, by adjusting the extension direction of the coil, the number of windings can be set easily and almost arbitrarily, and the inductance can be changed. Also, the inductance can be set flexibly by adjusting the area where the unit winding interlinks with the magnetic field as a whole or partially. In this way, the static of the capacitor can be changed easily and freely. Therefore, the series resonance frequency can be set easily and freely. Thus, when an AC voltage is applied from an external circuit to the LC series resonance circuit, the frequency band through which the current is passed or blocked, and the degree thereof can be flexibly set. First, the replacement of the coupling capacitor that is used for the connection between circuits and that cuts the DC signal and passes the high-frequency signal will be described. As will be described later, in the LC series resonance circuit of the present invention, the inductance component can be easily and almost arbitrarily added, so that the series resonance frequency can be easily controlled. Therefore, in addition to the effect of the coupling capacitor, a so-called band-pass filter effect that allows only a necessary frequency region to pass can be exhibited.
次にデカップリングコンデンサ、 すなわち、 高インピーダンスの信号を GND に落とす役割を担っているコンデンサへの応用につき記す。 イングクタ成分の調 整により、 使用周波数にあわせた直列共振周波数を有する本発明の L C直列共振 回路をデカップリングコンデンサの代わりに用いると、 目的とする、 使用周波数 帯の信号をより確実に G N Dに落とすことが可能である。  Next, the application to a decoupling capacitor, that is, a capacitor that plays a role of dropping a high impedance signal to GND is described. If the LC series resonance circuit of the present invention having a series resonance frequency according to the operating frequency is used in place of the decoupling capacitor by adjusting the intagter component, the intended signal in the operating frequency band is more reliably dropped to GND. It is possible.
本発明の L C直列共振回路は、 積極的にコイル状の回路が付カ卩されている。 こ のような構造をとることにより、 直列共振周波数を制御することができる。 すな わち、 コンデンサ部分は共通のまま直列共振周波数の制御をすることも、 コイル 状部分はそのままで制御することもいずれも可能である。 更に、 コイル状回路部 分は卷き数および長さの調節によりインダク夕成分をほぼ任意に設定できる。 次に、 本発明の L C直列共振回路 1 0 0、 1 2 0、 2 0 0及び 2 2 0の製造方 法について、 従来技術と比較した利点と共に説明する。 このような構造を形成す るには、 基板平面と垂直な方向に形成されるパターン (コイル状回路) と、 平行 な方向に形成されるパターン (コンデンサ状回路) の両方を一括で行う方法が必 要となる。従来広く用いられてきたコイルの形成方法、 すなわち、 基板平面と平 行な方向に螺旋状パターンを形成する、 と言う方法では、 基板平面と垂直な方向 にコンデンサ成分を形成するために座く、りなどの複雑な工程が必要になり、 事実 上不可能である。 In the LC series resonance circuit of the present invention, a coil-shaped circuit is actively added. With such a structure, the series resonance frequency can be controlled. In other words, it is possible to control the series resonance frequency while keeping the capacitor portion common, or to control the coil-shaped portion as it is. Furthermore, in the coil-shaped circuit part, the inductance component can be set almost arbitrarily by adjusting the number of turns and the length. Next, a method of manufacturing the LC series resonance circuits 100, 120, 200, and 220 of the present invention will be described together with advantages compared with the prior art. In order to form such a structure, there is a method in which a pattern formed in a direction perpendicular to the substrate plane (coil-shaped circuit) and a pattern formed in a direction parallel to the substrate (capacitor-shaped circuit) are collectively performed. It is necessary. In a method of forming a coil that has been widely used in the past, that is, a method of forming a spiral pattern in a direction parallel to the plane of the substrate, a method perpendicular to the plane of the substrate is used. This requires complicated processes such as sitting and gluing to form a capacitor component, which is practically impossible.
これに対して本発明では、 基板平面と平行に絶縁層の形成、 穴開けおよび導体 パターンの形成を順次行うことにより、 ¾反平面と平行にコィルの一部分を形成 し、 これを繰り返して電気的接続をすることにより、 反平面と垂直な面上にそ れそれ単位卷線を有するコィル状回路を螺旋状に形成することができる。 必要に 応じて、 同様の方法により隣接する単位卷線が、 同じ向きから見た場合互いに反 対方向に巻かれた螺旋状のパターンを有し、 当該螺旋状のパターンの先端同士又 は末端同士において互いに電気的に接続されたコィルを形成できる。 これらコィ ルの作成時に、 あわせて基板平面と平行な面上にコンデンサを形成することによ り、 一括で基板平面と垂直方向および平面方向両方に広がりを持つ回路を一体的 に形成できる。  On the other hand, in the present invention, a part of the coil is formed in parallel with the opposite plane by sequentially forming an insulating layer, forming a hole, and forming a conductive pattern in parallel with the plane of the substrate. By making the connection, a coil-shaped circuit having unit windings on a plane perpendicular to the opposite plane can be formed in a spiral shape. If necessary, adjacent unit windings have a spiral pattern wound in opposite directions when viewed from the same direction, and the leading ends or the trailing ends of the spiral pattern are viewed from the same direction. , Coils that are electrically connected to each other can be formed. By forming the capacitors on a plane parallel to the substrate plane when these coils are created, it is possible to integrally form circuits that extend in both the vertical direction and the plane direction with the substrate plane.
また、 本発明の方法を用いれば、 所望の巻き数のコイルを簡便に得ることがで きる。従来の、 基板平面と平行な面に螺旋パターンを形成する方法では、 卷き数 を増やすには積層数を増やす必要が生じ、 大きなコストアップとなるが、 本発明 の方法では積層数はそのままでコイルの伸長方向に伸ばすだけでよく、 コストァ ップは少ない。  Further, by using the method of the present invention, a coil having a desired number of turns can be easily obtained. In the conventional method of forming a spiral pattern on a plane parallel to the plane of the substrate, it is necessary to increase the number of layers in order to increase the number of windings, resulting in a large cost increase. However, in the method of the present invention, the number of layers is not changed. It only needs to be stretched in the coil extension direction, and there is little cost increase.
更に、 ノイズ対策の点からも有利である。従来の基板平面と平行な面上にスパ ィラルパターンを形成する方法では、 主たる磁力線が基板平面と垂直方向に生じ、 配線の上部又は下部にある部分に悪影響を及ぼす。 例えば近年一般化した高周波 領域で使用される I cでは非常に大きな問題となっており、 スパイラルパターン とトランジスタの距離をできるだけ大きく取るなどの方法でこの問題を回避して いる。 この点で従来の 平面と平行な面上にスパイラルパターンを形成する方 法は設計の自由度が非常に小さい。 これに対して本発明の方法により形成された コイルは、 主たる磁力線は基板と平行方向に生じるため、 トランジスタの形成さ れている基板に垂直な方向には影響が少ない。 したがって、 設計の自由度が非常 に高くなる。 更に、 本発明の方法では、 コイルの伸長方向を基板平面内の任意の 方向に設定できるため、 必要に応じてどの方向にも同一プロセスでコィルを形成 することが可能である。 It is also advantageous from the point of noise suppression. In the conventional method of forming a spiral pattern on a plane parallel to the plane of the substrate, main lines of magnetic force are generated in a direction perpendicular to the plane of the substrate, which adversely affects the upper or lower part of the wiring. For example, Ic used in the high-frequency region, which has become popular in recent years, is a very serious problem, and this problem is avoided by making the distance between the spiral pattern and the transistor as large as possible. In this regard, the conventional method of forming a spiral pattern on a plane parallel to a plane has a very small degree of freedom in design. On the other hand, in the coil formed by the method of the present invention, the main magnetic field lines are generated in a direction parallel to the substrate, so that the transistor The effect is small in the direction perpendicular to the substrate. Therefore, the degree of freedom in design becomes very high. Further, in the method of the present invention, since the extension direction of the coil can be set to any direction in the plane of the substrate, the coil can be formed in the same process in any direction as necessary.
次に本発明の実施例について説明する。 図 24は、 本発明の実施例にかかる L C直列共振回路のコイルとコンデンサの平面図である。 図 25は、 本発明の実施 例にかかる LC直列共振回路の A— A矢視横断面図である。 図 24及び図 25中 の長さの数値の単位は mmである。 回路の導体及び基板底面と側面は完全導体、 導体間の誘電率は 2. 0としてシミュレーションを実施した。 コイルとコンデン サとがこのような位置関係にある L C直列共振回路について、 三次元電磁界シミ ユレ一夕 (Sonnet) を使用して解析を行った。  Next, examples of the present invention will be described. FIG. 24 is a plan view of a coil and a capacitor of the LC series resonance circuit according to the embodiment of the present invention. FIG. 25 is a cross-sectional view of the LC series resonance circuit according to the example of the present invention, taken along the line AA. The unit of the numerical value of the length in FIGS. 24 and 25 is mm. The simulation was performed assuming that the conductors of the circuit, the bottom and side surfaces of the board were perfect conductors, and the permittivity between conductors was 2.0. The LC series resonance circuit in which the coil and the capacitor are in such a positional relationship was analyzed using three-dimensional electromagnetic field simulation (Sonnet).
まず、 コイルの解析を行った。 図 26は、 本発明の実施例にかかる LC直列共 振回路のコィルの斜視図である。 このコイルのリアクタンス成分の周波数依存性 をシミュレーションで求めると、 図 27に示されるグラフのようになった。 この 結果より、 500MHz、 1000MHz、 2000 MH zに対応するインダク 夕ンス値を求めると下表のようになった。
Figure imgf000021_0001
First, the coil was analyzed. FIG. 26 is a perspective view of a coil of the LC series resonance circuit according to the embodiment of the present invention. When the frequency dependence of the reactance component of this coil was determined by simulation, the graph shown in Fig. 27 was obtained. Based on these results, the inductance values corresponding to 500 MHz, 1000 MHz, and 2000 MHz are obtained as shown in the table below.
Figure imgf000021_0001
また、 図 27に示されるグラフには、 自己共振周波数が 3150MHz付近に 見られる。 この共振周波数は、 コイルと並列に存在する寄生容量によるものと考 えられる。 この寄生容量を、 上記の表の中で寄生容量の影響が小さい 500MH zの場合のインダク夕ンス値 14. 33 nHを用いて、 共振周波数の式 f=l /2ΤΓ (L*C0) より算出すると、 寄生容量 C0は 0. 178pFとなった 次にコンデンサの角军析を行った。 図 28は、 本発明の実施例にかかる LC直列 共振回路のコンデンザの斜視図である。 このコンデンサのリアクタンス成分の周 波数依存性をシミュレーションで求めると、 図 29に示されるグラフのようにな つた。 この結果より、 500MHz、 1000MHz、 200.0MHzに対応す るキャパシタンス値を求めると下表のようになった。
Figure imgf000022_0002
In the graph shown in Fig. 27, the self-resonant frequency is seen near 3150MHz. This resonance frequency is considered to be due to the parasitic capacitance existing in parallel with the coil. This parasitic capacitance is calculated from the resonance frequency formula f = l / 2ΤΓ (L * C0) using the inductance value of 14.33 nH in the above table at 500 MHz where the effect of the parasitic capacitance is small. Then, the parasitic capacitance C0 became 0.178 pF. Next, the capacitor was subjected to angular analysis. FIG. 28 shows an LC series according to the embodiment of the present invention. It is a perspective view of the condenser of a resonance circuit. When the frequency dependence of the reactance component of this capacitor was determined by simulation, the graph shown in Fig. 29 was obtained. Based on these results, the capacitance values corresponding to 500MHz, 1000MHz, and 200.0MHz were obtained as shown in the table below.
Figure imgf000022_0002
50 OMH zの場合のインダク夕ンス値及びキャパシタンス値に基づき、 直列 共振回路の共振周波数の式
Figure imgf000022_0001
(ί* (C + CO)) より直列共振周 波数を計算すると 2119MHzとなった。
Equation for resonance frequency of series resonant circuit based on inductance value and capacitance value at 50 OMHz
Figure imgf000022_0001
When the series resonance frequency was calculated from (ί * (C + CO)), it was 2119 MHz.
一方、 これらのコイルとコンデンサを、 図 30及び図 31に示すように直列に 接続し、 この直列回路の共振周波数を三次元電磁界シミュレ一夕により求めると、 図 32に示されるグラフのようになった。 この直列回路の共振周波数は、 220 0MHz付近に現れており、 この値は、 直列共振回路の共振周波数の式 f =1 2ΤΓ (L* (C + CO)) より算出した、 下表に示される直列共振周波数 2 119MHzと非常によく一致している。 図 33に、 LC直列共振回路の回路図 及び電流の周波数特性を表わすグラフを示す。
Figure imgf000022_0003
On the other hand, when these coils and capacitors are connected in series as shown in Figs. 30 and 31, and the resonance frequency of this series circuit is determined by a three-dimensional electromagnetic field simulation, it can be seen from the graph shown in Fig. 32. became. The resonance frequency of this series circuit appears around 2200 MHz, and this value is calculated from the equation of the resonance frequency of the series resonance circuit, f = 12 共振 (L * (C + CO)), as shown in the table below. It is in good agreement with the series resonance frequency of 2 119MHz. FIG. 33 shows a circuit diagram of the LC series resonance circuit and a graph showing the frequency characteristics of the current.
Figure imgf000022_0003
本発明の L C直列共振回路の製造方法につき、 以下具体的に図面を用いて説明 する。 本発明の LC直列共振回路の典型的な実施形態に係る図として、 図 1, 図 2を示す。 図 1は単層コイル、 図 2は多層コイルにコンデンサのパターンを付与 した実施形態である。  The method for manufacturing the LC series resonance circuit of the present invention will be specifically described below with reference to the drawings. FIG. 1 and FIG. 2 are diagrams according to a typical embodiment of the LC series resonance circuit of the present invention. FIG. 1 shows an embodiment in which a single-layer coil and a multilayer coil are provided with a capacitor pattern.
これから図 1 (a) に示した、 単層コイルを用いた LC直列共振回路 100を 有機材料を絶縁体として用いて製造する場合につき説明する。 まず、 図 3に示す ような、 絶縁体 l hに、 後でコイルの一部となるスルーホール 1 aと、 両面にコ ンデンザの極板 1 cとが形成されたコア基板 1を用意する。 2つの極板 I dは誘 電体 1 eを挟んでおり、 それらでコンデンサ 1 cを構成する。 極板 1 dのそれそ れには、 外部の回路との配線が接続される接続点 1 f及び 1 gを形成する。 コア 基板 1としては公知慣用の有機素材を絶縁体 1 hとして用いた銅張積層板を用い ることができ、 絶縁体 l hには、 例えばガラスエポキシ樹 S旨、 ビスマレイミ ド一 トリアジン基板あるいは、 誘電特性に優れたポリフエ二レンエーテル樹脂、 ポリ エーテルエ一テルケトン樹 S旨、 ベンゾシクロブテン樹且旨などを用いることができ る。 極板 l b間の誘電体 1 eとして、 絶縁体 l hと同じ材料を使用することもで きるが、 誘電体 1 eの部分をチタン酸バリウム、 チタン酸ストロンチウムなどの 高誘電フイラ一を上述した有機素材に配合することにより、 高容量でかつ誘電損 失の少ないコンデンサ層を得ることができる。 特に、 シァネートエステルとェポ キシ樹脂からなる高誘電材料は、 高誘電性フイラ一を高充填することができ、 高 容量のコンデンサ材料として好適である。 また、 チタン酸バリウムやチタン酸ス トロンチウムなどの高誘電性セラミックを主成分とするセラミックを焼成するこ とにより誘電体 1 eを形成し、 さらにその両面に極板 l bを形成したコア基板 1 を使用することによって、 小型で高容量のコンデンサを得ることが可能となる。 スルーホール 1 aの穴あけはドリルあるいは炭酸ガスレーザ一や Y A Gレーザー などの広く用いられている方法で行うことができる。 導体のパターニングは、 サ ブトラクティブ法、 アディティブ法など、 公知慣用の方法で行うことができる。 続いて、 コア基板 1の両面に最外層を図 4のように積層 '形成する。 絶縁層 1 iの材料、 穴開け方法、 導体のパ夕一ニング方法、 層間の電気的接続法としては コァ¾反 1と同様の材料、 方法が使用できる。 A case in which the LC series resonance circuit 100 using a single-layer coil shown in FIG. 1A is manufactured using an organic material as an insulator will now be described. First, shown in Figure 3 A core substrate 1 having a through hole 1a which will later be a part of a coil and a capacitor plate 1c formed on both sides of the insulator lh is prepared. The two plates Id sandwich the dielectric 1e, and they constitute a capacitor 1c. On each of the electrode plates 1d, connection points 1f and 1g to which wiring to an external circuit is connected are formed. As the core substrate 1, a copper-clad laminate using a known and common organic material as the insulator 1 h can be used.For the insulator lh, for example, a glass epoxy tree S, a bismaleimide-triazine substrate, or a dielectric Polyphenylene ether resin, polyether ether ketone resin S, benzocyclobutene resin and the like having excellent properties can be used. The same material as the insulator lh can be used as the dielectric 1e between the electrode plates lb.However, the dielectric 1e is replaced by a high dielectric filler such as barium titanate or strontium titanate. By blending it in the material, a capacitor layer with high capacity and low dielectric loss can be obtained. In particular, a high-dielectric material composed of a cyanate ester and an epoxy resin can fill a high-dielectric film at a high level, and is suitable as a high-capacity capacitor material. In addition, a dielectric 1e is formed by firing a ceramic mainly composed of a high dielectric ceramic such as barium titanate or strontium titanate, and a core substrate 1 having electrode plates lb formed on both surfaces thereof is formed. By using it, it is possible to obtain a small and high-capacity capacitor. Drilling of the through hole 1a can be performed by a widely used method such as a drill or a carbon dioxide laser or a YAG laser. Patterning of the conductor can be performed by a known and commonly used method such as a subtractive method or an additive method. Subsequently, outermost layers are laminated and formed on both surfaces of the core substrate 1 as shown in FIG. The same material and method as the core 1 can be used as a material of the insulating layer 1i, a hole forming method, a conductor patterning method, and an electrical connection method between layers.
最外層の積層 '形成は、 内層材に対し、 両面に絶縁層 l i、 その外側に更に導 電層を作成し、 パ夕一ニングおよび電気的接続を行えばよい。 いくつかの方法に つき具体的に例を挙げ T説明する。 The outermost layer can be formed by forming an insulating layer li on both sides of the inner layer material, and further forming a conductive layer outside the inner layer material, and performing power connection and electrical connection. In several ways A specific example will be given below.
いわゆるビルドアップ法による場合につき説明する。 上記内層材からなる基板 に絶縁層を形成する。 絶縁層としてはガラスエポキシ系あるいはァラミド樹脂系 などのプリプレグ、 液状あるいはフィルム状の熱可塑あるいは熱硬ィ匕性の樹脂組 成物あるいは一般的に樹脂付き銅箔と呼ばれる、 銅箔と絶縁樹脂層を一体化した ものなどが使用できる。  The case of the so-called build-up method will be described. An insulating layer is formed on a substrate made of the above inner layer material. As the insulating layer, a prepreg such as a glass epoxy type or an aramide resin type, a liquid or film-like thermoplastic or thermosetting resin composition, or a copper foil with a resin generally called a copper foil and an insulating resin layer One that integrates can be used.
絶縁層の形成は例えば以下のように行われる。 図 5 ( a ) に示すように、 上記 コア基板 1両面にプリプレダ 2、 パターン化されていない銅箔 3、 あるいは図 5 The formation of the insulating layer is performed, for example, as follows. As shown in Fig. 5 (a), the core substrate 1 has a pre-predder 2 on both sides, an unpatterned copper foil 3,
( b ) に示すように樹脂付き銅箔 4を配置し、 図 6に示すように積層プレス法に よりこれらを一括で積層、 硬化させ、 絶縁層と導電層を一体化したものを作成す る。 あるいは、 図 8に示すように、 上記コア基板 1上に液状の組成物をスクリ一 ン印刷、 力一テンコート、 スプレーコートなどの公知慣用の方法で塗布し、 UV、 電子線、 熱などで硬化させる。 あるいは上記基板上にフィルム状の組成物をロー ル、 ラミネートなどの方法で貼り付け、 所定の方法にて硬化させ、 絶縁層 5を得 る o As shown in (b), a resin-coated copper foil 4 is placed, and as shown in Fig. 6, these are collectively laminated and cured by a lamination press method to create an integrated insulating layer and conductive layer. . Alternatively, as shown in FIG. 8, a liquid composition is applied onto the core substrate 1 by a known and common method such as screen printing, force coating, spray coating, etc., and cured by UV, electron beam, heat, or the like. Let it. Alternatively, a film-like composition is pasted on the substrate by a method such as rolling or laminating, and cured by a predetermined method to obtain an insulating layer 5.o
続いてビアを形成する。 上記の方法で得られた の所定の位置にドリル、 レ —ザ一などを用いてビア 6を形成する。 図 8 ( a ) は絶縁層および導電層として プリプレグ 7と銅箔 8を用いた場合、 同様に図 8 ( b ) は樹脂付き銅箔 9、 図 8 Subsequently, a via is formed. A via 6 is formed at a predetermined position of the obtained by the above method using a drill, a laser or the like. Fig. 8 (a) shows the case where prepreg 7 and copper foil 8 were used as the insulating layer and the conductive layer. Similarly, Fig. 8 (b) shows the copper foil with resin 9 and Fig. 8
( c ) は液状あるいはフィルム状の熱可塑ある 、は熱硬化性の樹脂組成物 1 0を 用いた場合について記したものである。 プリプレグ類あるいは樹脂付き銅箔を用 いて絶縁層と共に導電層も形成した場合に、 ブラインドビアの形成に広く用いら れている炭酸ガスレ一ザ一を用 、る場合には、 必要に応じてあらかじめ所定の位 置の導電体をエッチングで除く、 いわゆるマスク加工を施してもよい。 (c) is a liquid or film-like thermoplastic, and (c) is a description using a thermosetting resin composition 10. If a conductive layer is formed together with the insulating layer using prepregs or resin-coated copper foil, use a carbon dioxide gas laser widely used for forming blind vias. A so-called masking process may be performed to remove the conductor at a predetermined position by etching.
プリプレダ類あるいは樹脂付き銅箔を用いて絶縁層と共に導電層も形成した場 合は、 例えば図 9 ( a) に示すようにビアに銀、 銅などの導電性粉末を配合した 導電性ペースト 1 1を印刷、 デイスペンスなどの方法で埋め込み、 所定の方法で 硬ィ匕させる。 あるいは、 図 9 ( b ) に示すように通常のスルーホールメヅキすな わちビア内にメツキ触媒を付与したのちに無電解メヅキを行い、 続いて電解メヅ キを行う方法によってメツキ層 1 2を形成する方法によっても電気的接続は達成 される。 液状もしくはフィルム状の組成物を用いて絶縁層を形成した場合は、 図 9 ( c ) に示すように、 例えば銅箔 1 3をプレスし、 絶縁層の外側に導電層を形 成し、 所定の位置をマスク加工した後、 ブラインドビアを導電性ペースト 1 1あ るいはメツキ層 1 2により導電化し接続する。 この場合、 先にブラインドビアの 導電化を行っても良い。 また、 図 9 ( d ) に示すように、 絶縁層、 ブラインドビ ァが形成された謝反に触媒を付与し、 無電解メヅキ処理し、 続いて必要に応じて 電解メッキ処理することによって導電層 1 4の形成とプラインドビアの導電化を 一括で行うこともできる。 この場合、 ブラインドビアの導電化は導電性べ一スト によっても行うことができる。 次に、 図 9 ( e ) に示すように、 銅箔 3、 8、 又 は 1 3あるいは導電層 1 4をパターニングし、 コイルを形成させる。 When a conductive layer is formed together with an insulating layer using a pre-preda or resin-coated copper foil, for example, conductive powder such as silver or copper is mixed in the via as shown in Fig. 9 (a). The conductive paste 11 is embedded by a method such as printing or dispensing, and is hardened by a predetermined method. Alternatively, as shown in FIG. 9 (b), a normal through-hole plating, that is, an electroless plating is performed after a plating catalyst is applied in a via, and then a plating layer 1 is formed by performing an electrolytic plating. Electrical connection is also achieved by the method of forming 2. When the insulating layer is formed using a liquid or film-like composition, as shown in FIG. 9 (c), for example, a copper foil 13 is pressed to form a conductive layer outside the insulating layer, and After performing mask processing at the position, the blind via is made conductive by the conductive paste 11 or the plating layer 12 and connected. In this case, the blind via may be made conductive first. Also, as shown in FIG. 9 (d), a catalyst is applied to the reaction where the insulating layer and the blind via are formed, and the electroless plating is performed. The formation of 14 and the conductivity of the blind via can also be performed at once. In this case, the blind vias can be made conductive by a conductive paste. Next, as shown in FIG. 9 (e), the copper foil 3, 8, or 13 or the conductive layer 14 is patterned to form a coil.
あるいは以下の方法により、 絶縁層と導電層、 電気的接続を一括で行うことも できる。 すなわち、 図 1 0に示すように、 コア ¾反 1上所定の場所に導電性べ一 ストなどを用いて先端のとがった導電性バンプ 1 5を形成した後、 プリプレグ 2 と銅箔 3 (図 1 0 ( a))、 あるいはフィルム状の絶縁体 5と銅箔 3 (図 1 0 ( b ))、 または樹脂付き銅箔 4を配置した後にプレス加工を行うこと (図 1 0 ( c ) ) によりとがった導電性バンプ 1 5が絶縁層を貫通し、 導電層との接続を実現す る。  Alternatively, the insulating layer, the conductive layer, and the electrical connection can be collectively performed by the following method. That is, as shown in FIG. 10, after a conductive bump 15 having a sharp tip is formed at a predetermined location on the core substrate 1 using a conductive paste or the like, a prepreg 2 and a copper foil 3 (FIG. 10 (a)) or press work after placing the film-shaped insulator 5 and copper foil 3 (Fig. 10 (b)), or copper foil 4 with resin (Fig. 10 (c)). As a result, the pointed conductive bumps 15 penetrate the insulating layer to realize connection with the conductive layer.
なお、 メツキにより接続されたスルーホール基板を用い、 上記の液状あるいは フィルム状の絶縁材料を使用する場合、 あるいは一旦ビルドアヅプ法により形成 したブラインドビアのある絶縁層上に更に積層する場合には、 穴埋め用のィンキ あるいはメツキ処理によりスルーホールあるいはブラインドビアを埋め、 表面を 平滑ィ匕してもよい。 When a through-hole board connected by plating is used and the above liquid or film-like insulating material is used, or when it is further laminated on an insulating layer having a blind via once formed by a build-up method, the hole is filled. Fill the through holes or blind vias with a finning or plating process and clean the surface You may perform smoothing.
あるいは、 以下の方法により一括に積層させることもできる。 絶縁層としてガ ラスエポキシ系のプリプレグを用いた 4層構造の場合につき説明する。 すなわち、 図 1 1に示すように、 銅張片面ガラスエポキシ基板の基材 1 6側の所定の位置を レーザ一などを用いて穴開け加工する。続いて、 銅箔 1 7を電極として電気メッ キを行い、 生じた穴をメヅキ 1 8で充填する。 その上に、 低融点の金属バンプ 1 9を引き続きメツキ法により作成する。銅箔 1 7は図 1 2に示すように所定のパ ターンにエツチング加工する。 バンプ側には絶縁層に用いるものと同様の組成物 2 0を薄く塗布し、 半硬ィ匕させておく。 この片面基板から製造されたものは最外 層すなわち第 1層および第 4層となる。  Alternatively, they can be collectively laminated by the following method. The case of a four-layer structure using glass epoxy prepreg as the insulating layer will be described. That is, as shown in FIG. 11, a predetermined position on the base material 16 side of the copper-clad single-sided glass epoxy substrate is drilled using a laser or the like. Subsequently, electric plating is performed using the copper foil 17 as an electrode, and the formed hole is filled with the plating 18. On top of this, low melting point metal bumps 19 are successively formed by the plating method. The copper foil 17 is etched into a predetermined pattern as shown in FIG. On the bump side, a composition 20 similar to that used for the insulating layer is thinly applied and is semi-hardened. The one manufactured from this single-sided substrate is the outermost layer, that is, the first and fourth layers.
続いて、 図 1 3に示すように、 コア基板 1と図 1 3の最外層を位置あわせし、 プレス加工することにより半硬化させた組成物はバンプ部から除かれ、 層間の絶 縁層を形成すると同時にバンプ部は内層の導電体と電気的に接続され、 4層構造 を有する L C直列共振回路が製造される。 この方法を応用することにより、 更な る多層化も容易に行うことができる。  Subsequently, as shown in FIG. 13, the core substrate 1 and the outermost layer of FIG. 13 are aligned, and the composition that has been semi-cured by pressing is removed from the bump portion, and the insulating layer between the layers is removed. At the same time as the bumps are formed, the bumps are electrically connected to the conductors in the inner layer, producing an LC series resonant circuit with a four-layer structure. By applying this method, further multilayering can be easily performed.
図 1 (b ) に示した、 3ィル 1 2 0 aの外部にコンデンサ 1 2 0 cが配置され た単層コイルを用いた L C直列共振回路 1 2 0も、 上述の L C直列共振回路 1 0 0の製造方法と同様の工程を、 その構成に合わせてそれそれ適切に実施すること によって製造することができる。 この場合、 L C直列共振回路 1 2 0の製造工程 は、 多層基板 1 2 O hを構成する 1つの層を初期材料として、 或いはコンデンサ 1 2 0 cを初期材料として開始すると好適である。  As shown in FIG. 1 (b), the LC series resonance circuit 120 using a single-layer coil in which a capacitor 120c is arranged outside the three coils 120a is also the LC series resonance circuit 1 described above. It can be manufactured by appropriately performing the same steps as those of the manufacturing method 100 according to the configuration. In this case, it is preferable that the manufacturing process of the LC series resonance circuit 120 be started with one layer constituting the multilayer substrate 120h as an initial material or with the capacitor 120c as an initial material.
コィルの内部に磁性体が形成される実施形態については、 磁性体がコイルの内 部に配置されることになるように、 多層基板の積層工程において磁性体を配置す る。 これによつて、 コイルの内部を貫通する柱状の磁性体からなる芯構造を形成 することができる。 螺旋状のパターンをより密にしたい場合は、 更なる多層化が必要となる。 上記 のいずれの方法を用いても、 更なる多層化が可能である。 すなわち、 絶縁層の付 与、 導電層の付与、 導電層間の電気的接続 (スルーホールの形成及び導電材料の 封入、 バンプの接触など)、 及び導電層のパ夕一ニングの一連のステヅプを繰り 返すことによって、 多層化することができる。 この際、 各層におけるスルーホ一 ルの位置、 及び導電層のパターンは、 好適には、 図 2 ( a ) に示すようなコイル 2 0 0 a又は図 2 (b ) に示すようなコイル 2 2 0 aが形成されるように構成す る。 In the embodiment in which the magnetic body is formed inside the coil, the magnetic body is arranged in the step of laminating the multilayer substrate so that the magnetic body is arranged inside the coil. Thereby, a core structure made of a columnar magnetic material penetrating the inside of the coil can be formed. In order to make the spiral pattern denser, further multilayering is required. Further multilayering is possible using any of the above methods. In other words, a series of steps including the provision of an insulating layer, the provision of a conductive layer, the electrical connection between conductive layers (formation of through holes and encapsulation of a conductive material, the contact of bumps, etc.), and the patterning of the conductive layer are repeated. By returning, it can be multi-layered. At this time, the position of the through hole in each layer and the pattern of the conductive layer are preferably the coil 200a as shown in FIG. 2 (a) or the coil 220a as shown in FIG. 2 (b). It is configured so that a is formed.
これらの方法を応用することにより、 図 2 ( a) 及び (b ) に示した多層コィ ルを含んだ L C直列共振回路も容易に製造できる。  By applying these methods, the LC series resonant circuit including the multilayer coil shown in Fig. 2 (a) and (b) can be easily manufactured.
また、 上記の各種の積層方法で各種基板を製造する際、 所定の位置で上記方法 を応用すれば、 本発明の L C直列共振回路を含有する L C直列共振回路内蔵部品、 L C直列共振回路内蔵基板も容易に製造できる。  Further, when manufacturing the various substrates by the above-described various laminating methods, if the above method is applied at a predetermined position, a component with a built-in LC series resonance circuit containing the LC series resonance circuit of the present invention, a substrate with a built-in LC series resonance circuit, Can also be easily manufactured.
上述のいずれの L C直列共振回路においても、 セラミック材料を絶縁材料に用 いることができる。 その場合も、 基本的には有機材料と同様の工程すなわち、 各 層にコイルの一部分およびコンデンサ様パターンを形成し、 これを積層する事に より製造できる。従来から行われている方法である、 グリーンシートへの穴開け、 導電ペーストによる穴埋めおよびパターン印刷、 積層、 焼成を順次行うことによ り本発明の多層基板内 L C直列共振回路は形成できる。 先に述べたように、 コン デンサを構成する絶縁層のみにセラミック材料を使用し、 その他の部分には有機 材料を使用することも可能である。 - また、 上述のいずれの L C直列共振回路も、 他の回路、 例えば、 I C、 メモリ、 抵抗器又は高周波素子のような回路を、 一体的に多層 ¾反内に形成して、 L C直 列共振回路内蔵多層基板とすることができる。 そのような他の回路は、 L C直列 共振回路と電気的に接続されていてもよく、 また、 直接には接続されていなくて もよい。 この L C直列共振回路内蔵多層基板は、 L C直列共振回路と一体的に形 成されるため、 同様の製造工程で簡単に製造でき、 また、 素子の集積度を向上さ せることができるという利点がある。 . In any of the above-described LC series resonance circuits, a ceramic material can be used as the insulating material. Also in this case, it can be manufactured by basically forming a part of the coil and a capacitor-like pattern on each layer in the same process as the organic material, and laminating them. The LC series resonance circuit in the multilayer substrate of the present invention can be formed by sequentially performing a method of forming a hole in a green sheet, filling a hole with a conductive paste, and printing, laminating, and firing in a conventional manner. As mentioned earlier, it is possible to use ceramic material only for the insulating layer that constitutes the capacitor, and to use organic material for the other parts. -In addition, any of the above-mentioned LC series resonance circuits can be formed by integrally forming other circuits, for example, circuits such as ICs, memories, resistors, or high-frequency elements in a multi-layered circuit. It can be a multilayer substrate with a built-in circuit. Such other circuits may be electrically connected to the LC series resonant circuit and may not be directly connected. Is also good. This multi-layer substrate with built-in LC series resonance circuit is formed integrally with the LC series resonance circuit, so that it can be easily manufactured in the same manufacturing process, and has the advantage that the degree of integration of elements can be improved. is there. .
更に、 上述のいずれの L C直列共振回路或いは L C直列共振回路内蔵多層基板 についても、 モノリシック I Cなどを構成する半導体チップ上に形成することが できる。 このような構成にすることにより、 半導体パッケージ内に L C直列共振 回路などの素子を高い集積度で組み込むことができる。 これから、 半導体基板上 に、 基板平面と垂直な面上に単位卷線を有するコイルと.、 基板平面と平行にコン デンサ様パターンを形成する過程を以下に示す。 典型例として、 トランジスタを 形成し、 更にタングステンなどで電極部を形成したシリコンウェハの上層いわゆ る電極配線層に、 図 1 ( a ) の L C直列共振回路 1 0 0を形成する例を示す。 こ の方法を応用することにより、 ターン数、 列 (層) 数、 形成方向などは任意に設 定可能である。 なお半導体は、 シリコンに限られることはなく、 ガリウムひ素な どの任意の公知の半導体材料を使用することができる。  Further, any of the above-described LC series resonance circuits or the multilayer substrate with a built-in LC series resonance circuit can be formed on a semiconductor chip constituting a monolithic IC or the like. With such a configuration, elements such as an LC series resonance circuit can be incorporated in the semiconductor package with a high degree of integration. From now on, the process of forming a coil having unit windings on a surface perpendicular to the plane of the substrate and forming a capacitor-like pattern parallel to the plane of the substrate will be described below. As a typical example, an example is shown in which an LC series resonance circuit 100 shown in FIG. 1A is formed in a so-called electrode wiring layer on an upper layer of a silicon wafer in which a transistor is formed and an electrode portion is formed with tungsten or the like. By applying this method, the number of turns, the number of rows (layers), the formation direction, etc. can be set arbitrarily. Note that the semiconductor is not limited to silicon, and any known semiconductor material such as gallium arsenide can be used.
まず、 図 1 4に示すように、 トランジスタ、 電極部を形成したシリコンウェハ 2 1上に、 最下層の絶縁層 2 2を形成する。 CVDなどの気相法を用いてシリコ ン酸化膜を形成するか、 近年注目されているポリイミド、 ベンゾシクロブテンな どの有機素材をスピンコート後にボストベークする事によって形成できる。続い て、 図 1 5に示すように必要な箇所に各種レーザーを用いて穴 2 3の穴開けを行 う。 穴 2 3は、 半導体ゥェ一ハ 2 1の特定の箇所又は下層の電極部との電気的接 続を行う箇所である。続いて、 図 1 6に示すように、 導電性パターン 2 4を形成 する。 一般的に用いられている、 アルミニウムのスパッタリング、 あるいは銅の 層を CVDなどの気相法、 あるいはメヅキ法などの湿式法を用いて形成する。 つ いで露光、 エッチングしてパターニングする。 この場合、 先にパ夕一ニングした レジスト層を形成した後に導電ィ匕を行っても良い。 この工程で、 図 1 5に示した 工程で穴開けされた穴 2 3も導電化され、 第 1層と窠 2層の電気的接続がなされ る。 なお、 露光工程の前には通常、 物理的な研磨、 あるいは CMP法と呼ばれる 化学的研磨と物理的研磨を組み合わせた方法などにより、 表面を平坦化する。 次に、 図 1 7のように、 第 2の絶縁層 2 5を形成する。 ついで、 図 1 8のよう に、 再び穴開け、 導体パターン形成により第 2の導電性パターン 2 6を形成する。 この際、 コンデンサ状パ夕一ンも同時に形成できる。 ついで図 1 9のように第 3 の絶縁層 2 7を前述の方法により形成し、 穴開け、 導電化、 パ夕一ニングを施し、 第 3の導電性パターン 2 8を形成すると共に第 2層、 第 3層の導通を取る。 First, as shown in FIG. 14, a lowermost insulating layer 22 is formed on a silicon wafer 21 on which transistors and electrode portions are formed. The silicon oxide film can be formed by a vapor phase method such as CVD, or by spin-coating an organic material such as polyimide or benzocyclobutene, which has recently attracted attention, and then performing bast baking. Subsequently, as shown in FIG. 15, holes 23 are drilled in necessary places using various lasers. The hole 23 is a specific portion of the semiconductor wafer 21 or a portion for making an electrical connection with the lower electrode portion. Subsequently, as shown in FIG. 16, a conductive pattern 24 is formed. A commonly used aluminum sputtering or copper layer is formed by a vapor phase method such as CVD or a wet method such as plating. Next, it is exposed, etched and patterned. In this case, the conductive layer may be formed after forming the resist layer that has been patterned in advance. In this process, as shown in Figure 15 The holes 23 formed in the process are also made conductive, and the first layer and the second layer are electrically connected. Before the exposure step, the surface is usually planarized by physical polishing or a method called chemical mechanical polishing (CMP) that combines physical polishing and physical polishing. Next, as shown in FIG. 17, a second insulating layer 25 is formed. Next, as shown in FIG. 18, a hole is formed again, and a second conductive pattern 26 is formed by forming a conductive pattern. At this time, a capacitor-shaped capacitor can be formed at the same time. Next, as shown in FIG. 19, a third insulating layer 27 is formed by the above-described method, a hole is formed, the conductive layer is formed, and a third conductive pattern 28 is formed. Take the third layer conduction.
以後、 この操作を繰り返し、 図 1 9のように第 4の絶縁層 2 9を形成した後、 穴開け、 導電化、 パターニングを行って、 第 4の導電性パターン 3 0を形成する。 この段階で、 図 1に示すような L C直列共振回路が半導体上に形成できる。 この 操作を応用すれば、 夕一ン数の増減、 列 (層) 数の増減、 異なる伸長方向を有す る複数のコィルの形成などが簡便に行える。  Thereafter, this operation is repeated to form a fourth insulating layer 29, as shown in FIG. 19, and then perform drilling, conducting, and patterning to form a fourth conductive pattern 30. At this stage, an LC series resonance circuit as shown in FIG. 1 can be formed on the semiconductor. By applying this operation, it is possible to easily increase or decrease the number of evenings, increase or decrease the number of rows (layers), or form multiple coils having different extension directions.
絶縁層形成、 穴開け後に導電層を形成すると共に線間の電気的接続を行う際、 図 2 1に示すように、 穴部分 (ビアホール) 3 1を導電体 3 2で充填すると、 図 2 2にコイル断面を示すように、 一般的にスタックトビアと呼ばれる構造すなわ ち充填されたビアホール上に再びビアホールのある構造を形成でき、 コイルの辺 を直線にすることができる。  When forming a conductive layer after forming an insulating layer and drilling holes and making electrical connections between wires, as shown in Fig. 21, the hole (via hole) 31 is filled with a conductor 32. As shown in the figure, a structure generally called a stacked via, that is, a structure having a via hole on a filled via hole can be formed again, and the side of the coil can be made straight.
また、 一般的に行われている方法、 すなわち、 ビアホールを導電体で充填しな い方法では、 スタックトビァ構造は形成できない。 その際、 製造されたコイルは、 図 2 3に示すような、 ビアホール接続部が階段状となった断面を有する。 このよ うな構造となっても、 特に高周波領域で使用する場合には実用上問題ない。  In addition, a stacked via structure cannot be formed by a commonly used method, that is, a method in which a via hole is not filled with a conductor. At that time, the manufactured coil has a cross-section in which the via-hole connection portion is stepped as shown in FIG. Even with such a structure, there is no practical problem particularly when used in a high frequency range.
シリコンゥェ一ハ 2 1上の多層基板内に所望の L C直列共振回路が形成された 後に、 そのシリコンゥヱ一ハ 2 1と L C直列共振回路を含む多層基板とを半導体 チップ単位に切り分ける。 なお、 シリコンゥェ一ハ 2 1に L C直列共振回路又はそれを内蔵する多層基板 を積層させる前に、 シリコンゥェ一ハ 2 1をチヅプ単位に切り分けておくことも できる。 この場合、 あらかじめ切り分けた半導体チップの外面に、 上記の工程と 同様にして、 L C直列共振回路又はそれを内蔵する多層基板を積層させるとよい。 以上のように、 本発明の方法により製造された L C直列共振回路は、 インダク 夕 (コイル) パターンにコンデンサ様パターンを付加することにより、 従来のも のに比べて直列共振周波数が容易に制御でき、 小型ながら広い用途に使用できる。 また、 自由にコイルの卷き数、 コイルの伸長方向を設定でき、 設計の自由度が飛 躍的に向上する。 更に、 ノイズ対策にも有効である。 After a desired LC series resonance circuit is formed in the multilayer substrate on the silicon wafer 21, the silicon substrate 21 and the multilayer substrate including the LC series resonance circuit are separated into semiconductor chip units. Before laminating the LC series resonant circuit or the multilayer substrate incorporating the same on the silicon wafer 21, the silicon wafer 21 may be divided into chips. In this case, an LC series resonance circuit or a multilayer substrate incorporating the same may be laminated on the outer surface of the semiconductor chip that has been cut in advance in the same manner as in the above-described process. As described above, the LC series resonance circuit manufactured by the method of the present invention can control the series resonance frequency more easily than the conventional one by adding a capacitor-like pattern to the inductor (coil) pattern. It can be used for a wide range of purposes despite its small size. In addition, the number of turns of the coil and the direction in which the coil extends can be set freely, greatly improving the degree of freedom in design. Furthermore, it is also effective for noise suppression.

Claims

請求の範囲 The scope of the claims
1 . 多層基板と一体的に形成されるコイルであって、 当該多層基板に平行な卷 線部分及び当該多層 »反に垂直な卷線部分を含むコィルと、 1. a coil formed integrally with the multilayer substrate, the coil including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate;
前記多層基板と一体的に形成されるコンデンサであって、 前記コィルと電気的 に直列に接続されるコンデンサと、 を有し、  A capacitor formed integrally with the multilayer substrate, the capacitor being electrically connected in series with the coil;
前記コィル及び前記コンデンサは、 前記多層基板内に支持され、  The coil and the capacitor are supported in the multilayer substrate,
前記コィルの単位巻線は、 隣接する他の単位巻線と同じ方向から見た場合に互 いに反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び  The unit windings of the coil each have a spiral pattern that turns in opposite directions when viewed from the same direction as the other adjacent unit windings; and
前記コイルの互いに隣接する単位巻線の組は、 当該螺旋状のパターンの先端同 士又は末端同士において交互に接続されることを特徴とする L C直列共振回路。 The LC series resonance circuit, wherein sets of adjacent unit windings of the coil are connected alternately at the leading end or the trailing end of the spiral pattern.
2 . 多層基板と一体的に形成されるコイルであって、 当該多層基板に平行な卷 線部分及び当該多層 に垂直な卷線部分を含むコィルと、 2. a coil formed integrally with the multilayer substrate, the coil including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate;
前記多層基板と一体的に形成されるコンデンサであって、 前記コイルと電気的 に直列に接続されるコンデンサと、  A capacitor formed integrally with the multilayer substrate, the capacitor being electrically connected in series with the coil;
前記コィルの内部を貫通する柱状の磁性体からなる芯構造と、 を有し、 前記コイル、 前記コンデンサ及び前記芯構造は、 前記多層基板内に支持される ことを特徴とする L C直列共振回路。  And a core structure made of a columnar magnetic material penetrating the inside of the coil, wherein the coil, the capacitor and the core structure are supported in the multilayer substrate.
3 . 前記コイルの単位巻線は、 隣接する他の単位卷線と同じ方向から見た場合 に互いに反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び  3. Each of the unit windings of the coil has a spiral pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings, and
前記コイルの互いに隣接する単位巻線の組は、 当該螺旋状のパターンの先端同 士又は末端同士において交互に接続されることを特徴とする請求の範囲第 2項に 記載の L C直列共振回路。  3. The LC series resonance circuit according to claim 2, wherein sets of adjacent unit windings of the coil are connected alternately at the leading end or the trailing end of the spiral pattern.
4 . 前記コイルは、 前記多層基板に平行な卷線部分が、 積層された導電層の一 部として形成され、 前記多層基板に垂直な巻線部分が、 前記絶縁層を介して隣接 する前記導電層間を接続するバンプとして形成されることを特徴とする請求の範 囲第 1乃至 3項のいずれか 1項に記載の L C直列共振回路。 4. In the coil, a winding portion parallel to the multilayer substrate is formed as a part of a stacked conductive layer, and a winding portion perpendicular to the multilayer substrate is adjacent via the insulating layer. The LC series resonance circuit according to any one of claims 1 to 3, wherein the LC series resonance circuit is formed as a bump connecting the conductive layers.
5 . 前記コィルは、 ビルドァヅプ工法により、 前記多層 反に平行な卷線部分 が、 積層された導電層の一部として形成され、 前記多層基板に垂直な卷線部分が、 前記絶縁層を通して隣接する前記導電層間を接続するビア或いはスル一ホ一ルと して形成されることを特徴とする請求の範囲第 1乃至 3項のいずれか 1項に記載 の L C直列共振回路。  5. In the coil, a winding portion parallel to the multilayer is formed as a part of a stacked conductive layer by a build-up method, and a winding portion perpendicular to the multilayer substrate is adjacent to the multilayer substrate through the insulating layer. The LC series resonance circuit according to any one of claims 1 to 3, wherein the LC series resonance circuit is formed as a via or a through hole connecting the conductive layers.
6 . 前記多層基板の絶縁層に有機素材を使用することを特徴とする請求の範囲 第 1乃至 5項のいずれか 1項に記載の L C直列共振回路。  6. The LC series resonance circuit according to any one of claims 1 to 5, wherein an organic material is used for an insulating layer of the multilayer substrate.
7 . 前記コンデンサを構成する誘電体にセラミックを使用することを特徴とす る請求の範囲第 1乃至 6項のいずれか 1項に記載の L C直列共振回路。  7. The LC series resonance circuit according to any one of claims 1 to 6, wherein ceramic is used for a dielectric material constituting the capacitor.
8 . 前記コンデンサを構成する誘電体が焼成された高誘電セラミックからなる ことを特徴とする、 請求の範囲第 1乃至 7項のいずれか 1項に記載の L C直列共 振回路。  8. The LC series resonance circuit according to any one of claims 1 to 7, wherein the dielectric constituting the capacitor is made of fired high dielectric ceramic.
9 . 前記コンデンサを構成する誘電体が高誘電セラミヅクの粉末或いはウイス 力一を含有する有機素材からなることを特徴とする、 請求の範囲第 1乃至 6項の いずれか 1項に記載の L C直列共振回路。  9. The LC series according to any one of claims 1 to 6, wherein the dielectric constituting the capacitor is made of a high dielectric ceramic powder or an organic material containing wisdom. Resonant circuit.
1 0 . 前記高誘電セラミックが、 チタン酸バリウム、 チタン酸ストロンチウム の内の少なくとも一種を含有することを特徴とする請求の範囲第 8又は 9項に記 載の L C直列共振回路。  10. The LC series resonance circuit according to claim 8 or 9, wherein the high dielectric ceramic contains at least one of barium titanate and strontium titanate.
1 1 . 請求の範囲第 1乃至 1 0項のいずれか 1項に記載の L C直列共振回路と、 前記多層 と、  11. The LC series resonance circuit according to any one of claims 1 to 10, and the multilayer,
前記多層基板と一体的に形成され、 当該多層 ¾反内に支持された他の回路と、 を有することを特徴とする L C直列共振回路内蔵多層基板。  A multi-layer board with a built-in LC series resonance circuit, comprising: another circuit formed integrally with the multi-layer board and supported in the multi-layer board.
1 2 . 請求の範囲第 1乃至 1 0項のいずれか 1項に記載の多層基板内 L C直列 共振回路を含む L C直列共振回路内蔵多層基板において、 12. The LC series in the multilayer substrate according to any one of claims 1 to 10. In a multilayer board with built-in LC series resonance circuit including a resonance circuit,
半導体チップの外面に積層され、  Laminated on the outer surface of the semiconductor chip,
前記半導体チップの特定の箇所との間で電気的に接続されたことを特徴とする、 L C直列共振回路内蔵多層基板。  A multilayer substrate with a built-in LC series resonance circuit, which is electrically connected to a specific portion of the semiconductor chip.
1 3 . 請求の範囲第 1 1項に記載の L C直列共振回路内蔵多層基板において、 半導体チップの外面に積層され、  13. The multilayer substrate with a built-in LC series resonance circuit according to claim 11, which is laminated on an outer surface of a semiconductor chip,
前記半導体チヅプの特定の箇所との間で電気的に接続されたことを特徴とする、 L C直列共振回路内蔵多層基板。  A multilayer substrate with a built-in LC series resonance circuit, wherein the multilayer substrate is electrically connected to a specific portion of the semiconductor chip.
1 4 . 多層基板を構成する 1つの絶縁層を形成するステップと、  1 4. A step of forming one insulating layer constituting a multilayer substrate;
コンデンサを前記多層基板内に形成するステップと、  Forming a capacitor in the multilayer substrate;
前記多層基板に平行なコィルの卷線部分の少なくとも一部を前記多層基板内の 絶縁層上に形成するステヅプと、  Forming at least a part of a winding portion of a coil parallel to the multilayer substrate on an insulating layer in the multilayer substrate;
前記多層基板に平行なコィルの前記卷線部分の少なくとも一部同士を絶縁層間 で電気的に接続する垂直接続部を形成し、 それによつて前記多層基板に垂直なコ ィルの卷線部分の少なくとも一部を形成するステツプと、  A vertical connecting portion is formed to electrically connect at least a part of the winding portion of the coil parallel to the multilayer substrate between insulating layers, thereby forming a winding portion of the coil perpendicular to the multilayer substrate. Steps forming at least a part thereof;
前記コンデンザと前記コィルとが電気的に直列に接続されるように、 それらの 間を電気的に接続するステヅプと、  Electrically connecting the capacitor and the coil so that they are electrically connected in series; and
絶縁層を形成する前記ステツプ、 前記多層 ¾反に平行なコイルの巻線部分の少 なくとも一部を形成する前記ステップ、 及び前記多層基板に垂直なコイルの卷線 部分の少なくとも一部を形成する前記ステツプの少なくともいずれかを、 前記多 層基板に平行なコィルの卷線部分と前記多層 反に垂直なコィルの卷線部分とで 前記多層基板内に支持される所定のコイルが形成されるまで、 それまでに形成さ れた多層 ¾反の部分に対して適宜反復するステップと、 を具備し、  The step of forming an insulating layer; the step of forming at least a part of a winding part of the coil parallel to the multilayer; and forming at least a part of a winding of a coil perpendicular to the multilayer substrate. A predetermined coil supported in the multilayer substrate is formed by a coil winding portion parallel to the multilayer substrate and a coil winding portion parallel to the multilayer substrate. And optionally repeating steps for the previously formed multi-layer part.
前記所定のコィルの単位巻線は、 隣接する他の単位卷線と同じ方向から見た場 合に互いに反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び 前記所定のコイルの互いに隣接する単位卷線の組は、 前記螺旋状のパ夕一ンの 先端同士又は末端同士において交互に接続されることを特徴とする L C直列共振 回路の製造方法。 The unit windings of the predetermined coil each have a helical pattern that turns in opposite directions when viewed from the same direction as the other adjacent unit windings; and A method of manufacturing an LC series resonance circuit, wherein sets of unit windings adjacent to each other of the predetermined coil are alternately connected at the tips or ends of the spiral pattern.
1 5 . 多層基板を構成する 1つの絶縁層を形成するステヅプと、  1 5. A step of forming one insulating layer constituting the multilayer substrate;
コンデンサを前記多層基板内に形成するステツプと、  Forming a capacitor in the multilayer substrate;
前記多層基板に平行なコイルの卷線部分の少なくとも一部を前記多層基板内の 絶縁層上に形成するステヅプと、  Forming at least a part of a winding portion of a coil parallel to the multilayer substrate on an insulating layer in the multilayer substrate;
前記多層基板に平行なコィルの前記卷線部分の少なくとも一部同士を絶縁層間 で電気的に接続する垂直接続部を形成し、 それによつて前記多層基板に垂直なコ ィルの卷線部分の少なくとも一部を形成するステップと、  A vertical connecting portion is formed to electrically connect at least a part of the winding portion of the coil parallel to the multilayer substrate between insulating layers, thereby forming a winding portion of the coil perpendicular to the multilayer substrate. Forming at least a part of;
前記コンデンサと前記コィルとが電気的に直列に接続されるように、 それらの 間を電気的に接続するステヅプと、  Electrically connecting the capacitor and the coil so that they are electrically connected in series; and
柱状の磁性体からなる芯構造を前記コィルの内部に配置されるように形成する ステップと、  Forming a core structure made of a columnar magnetic body so as to be arranged inside the coil;
絶縁層を形成する前記ステヅプ、 前記多層基板に平行なコィルの卷線部分の少 なくとも一部を形成する前記ステップ、 及び前記多層基板に垂直なコイルの卷線 部分の少なくとも一部を形成する前記ステップの少なくともいずれかを、 前記多 層基板に平行なコィルの卷線部分と前記多層基板に垂直なコィルの卷線部分とで 前記多層基板内に支持される所定のコイルが形成されるまで、 それまでに形成さ れた多層 反の部分に対して適宜反復するステップと、 を有することを特徴とす る L C直列共振回路の製造方法。  The step of forming an insulating layer; the step of forming at least a part of a coil winding part parallel to the multilayer substrate; and the forming of at least a part of a coil winding part perpendicular to the multilayer substrate. At least one of the steps is performed until a predetermined coil supported in the multilayer substrate is formed by the coil winding portion parallel to the multilayer substrate and the coil winding portion perpendicular to the multilayer substrate. And a step of appropriately repeating the multi-layered portion formed so far, and a method of manufacturing an LC series resonance circuit.
1 6 . 前記垂直接続部は前記絶縁層を介して隣接する前記導電層間を接続する バンプであることを特徴とする請求の範囲第 1 4又は Γ 5項に記載の L C直列共 振回路の製造方法。  16. The manufacturing of the LC series resonant circuit according to claim 14 or 5, wherein the vertical connection portion is a bump connecting the adjacent conductive layers via the insulating layer. Method.
1 7 . 前記ステップの少なくともいずれかはビルドァヅプェ法によって実施さ れ、 及び ' 前記垂直接続部は前記絶縁層を通して隣接する前記導電層間を接続するビア或 いはスルーホールであることを特徴とする請求の範囲第 1 4又は 1 5項に記載の L C直列共振回路の製造方法。 17. At least one of the above steps is performed by the build-up method. 16. The LC series resonance according to claim 14, wherein the vertical connection portion is a via or a through hole connecting the adjacent conductive layers through the insulating layer. Circuit manufacturing method.
1 8 . 前記多層 の絶縁層に有機素材を使用することを特徴とする請求の範 囲第 1 4乃至 1 7項のいずれか 1項に記載の L C直列共振回路の製造方法。  18. The method for manufacturing an LC series resonance circuit according to any one of claims 14 to 17, wherein an organic material is used for the multilayer insulating layer.
1 9 . 前記コンデンサを構成する誘電体にセラミックを使用することを特徴と する請求の範囲第 1 4乃至 1 8項のいずれか 1項に記載の L C直列共振回路の製 造方法。 19. The method for manufacturing an LC series resonance circuit according to any one of claims 14 to 18, wherein ceramic is used for a dielectric material constituting the capacitor.
2 0 . 前記コンデンサを構成する誘電体が焼成された高誘電セラミックからな ることを特徴とする、 請求の範囲第 1 4乃至 1 9項のいずれか 1項に記載の L C 直列共振回路の製造方法。  20. The manufacturing of the LC series resonance circuit according to any one of claims 14 to 19, wherein the dielectric constituting the capacitor is made of fired high dielectric ceramic. Method.
2 1 . 前記コンデンサを構成する誘電体が高誘電セラミヅクの粉末或いはウイ スカ一を含有する有機素材からなることを特徴とする、 請求の範囲第 1 4乃至 1 8項のいずれか 1項に記載の L C直列共振回路の製造方法。  21. The method according to any one of claims 14 to 18, wherein the dielectric constituting the capacitor is made of an organic material containing high dielectric ceramic powder or whiskers. Method of manufacturing LC series resonance circuit.
2 2 . 前記高誘電セラミックが、 チタン酸バリウム、 チタン酸ストロンチウム の内の少なくとも一種を含有することを特徴とする請求の範囲第 2 0又は 2 1項 に記載の L C直列共振回路の製造方法。 22. The method for manufacturing an LC series resonance circuit according to claim 20 or 21, wherein said high dielectric ceramic contains at least one of barium titanate and strontium titanate.
2 3 . 請求の範囲第 1 4乃至 2 2項のいずれか 1項に記載の L C直列共振回路 の製造方法のステップを有し、  23. The method according to any one of claims 14 to 22, comprising a step of a method of manufacturing an LC series resonance circuit,
前記多層基板と一体的に、 当該多層基板内に支持される他の回路を形成するス テヅプ、 .  A step of forming another circuit supported in the multilayer substrate integrally with the multilayer substrate;
を更に有することを特徴とする L C直列共振回路内蔵多層基板の製造方法。A method of manufacturing a multilayer substrate with a built-in LC series resonance circuit, further comprising:
2 4 . 請求の範囲第 1 4乃至 2 2項のいずれか 1項に記載の L C直列共振回路 の製造方法のステヅプを有し、 前記 L C直列共振回路は半導体ゥエーハの外面に積層されるものであり、 前記 L C直列共振回路を前記半導体ゥヱーハの特定の箇所との間で電気的に接 続するステップと、 24. A method for manufacturing an LC series resonance circuit according to any one of claims 14 to 22, The LC series resonance circuit is laminated on an outer surface of a semiconductor wafer, and electrically connecting the LC series resonance circuit to a specific portion of the semiconductor wafer;
前記 L C直列共振回路が積層された前記半導体ゥヱ一ハを半導体チップ単位に 切り分けるステップと、  Isolating the semiconductor wafer on which the LC series resonance circuit is stacked in units of semiconductor chips;
を更に有することを特徴とする、 L C.直列共振回路の製造方法。 L C. A method for manufacturing a series resonant circuit.
2 5 . 請求の範囲第 2 3項に記載の L C直列共振回路内蔵多層基板の製造方法 のステップを有し、  25. The method for manufacturing a multilayer substrate with a built-in LC series resonance circuit according to claim 23, comprising:
前記 L C直列共振回路内蔵基板は半導体ゥェ一ハの外面に積層されるものであ り、  The LC series resonance circuit built-in substrate is laminated on an outer surface of a semiconductor wafer,
前記 L C直列共振回路内蔵基板を前記半導体ゥヱ一ハの特定の箇所との間で電 気的に接続するステップと、  Electrically connecting the substrate with a built-in LC series resonance circuit to a specific portion of the semiconductor screen;
前記 L C直列共振回路内蔵基板が積層された前記半導体ゥエーハを半導体チッ プ単位に切り分けるステップと、  Dividing the semiconductor wafer on which the LC series resonance circuit built-in substrate is laminated into semiconductor chips;
を更に有することを特徴とする、 L C直列共振回路内蔵多層基板の製造方法。A method for manufacturing a multilayer substrate with a built-in LC series resonance circuit, further comprising:
2 6 . 請求の範囲第 1 4乃至 2 2項のいずれか 1項に記載の L C直列共振回路 の製造方法のステップを有し、 26. The method according to any one of claims 14 to 22, comprising a step of manufacturing the LC series resonance circuit according to any one of claims 1 to 22,
前記 L C直列共振回路は半導体チップの外面に積層されるものであり、 前記 L C直列共振回路を前記半導体チップの特定の箇所との間で電気的に接続 するステップ、  The LC series resonance circuit is laminated on an outer surface of a semiconductor chip, and electrically connecting the LC series resonance circuit to a specific portion of the semiconductor chip;
を更に有することを特徴とする、 L C直列共振回路の製造方法。 A method of manufacturing an LC series resonance circuit, further comprising:
2 7 . 請求の範囲第 2 3項に記載の L C直列共振回路内蔵多層基板の製造方法 のステップを有し、  27. The method of manufacturing a multilayer substrate with a built-in LC series resonance circuit according to claim 23, comprising:
前記 L C直列共振回路内蔵 ¾ί反は半導体チヅプの外面に積層されるものであり、 前記 L C直列共振回路内蔵基板を前記半導体チップの特定の箇所との間で電気 的に接続するステップ、 The built-in LC series resonance circuit is laminated on the outer surface of the semiconductor chip, and electrically connects the substrate with built-in LC series resonance circuit to a specific portion of the semiconductor chip. Step to connect,
を更に有することを特徴とする、 L C直列共振回路内蔵多層 »反の製造方法。 A method of manufacturing a multilayer with a built-in LC series resonance circuit.
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