JP2006514781A - 3次元メモリアレイ - Google Patents
3次元メモリアレイ Download PDFInfo
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- JP2006514781A JP2006514781A JP2004571614A JP2004571614A JP2006514781A JP 2006514781 A JP2006514781 A JP 2006514781A JP 2004571614 A JP2004571614 A JP 2004571614A JP 2004571614 A JP2004571614 A JP 2004571614A JP 2006514781 A JP2006514781 A JP 2006514781A
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- 238000010586 diagram Methods 0.000 description 13
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
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Abstract
Description
3次元(3D)メモリアレイは、平坦な表面を有する基板上に製作される。3次元メモリアレイは、平坦な表面に対して平行な2つ以上の平面内に構成される複数の第1の選択線を含む。複数の第2の選択線は、基板の平坦な表面に対して直交して配置されるピラー内に形成される。複数のメモリセルは、複数の第1の選択線及び複数の第2の選択線にそれぞれ結合される。
本明細書で説明される、3Dメモリアーキテクチャの実施形態は、メモリセルのアレイ内の特定のメモリセルを選択するために用いられる行線又は列線のいずれかを形成するために垂直ピラーを利用する。このアーキテクチャは、積重することにより従来のクロスポイントメモリアレイに簡単に拡張する従来の3Dアーキテクチャに比べてはるかに容積空間効率が高く、高速で、しかも製作するのが容易である複数のメモリセルから、「立方形の」アレイ構造を作成する。本明細書で説明される一実施形態は、ワンタイムプログラマブル(OTP)メモリ又は追記型(WORM)メモリとしても知られている、ライトワンスアレイを含む。「3次元」(即ち、3つの次元を有するが、それぞれは同じ長さである必要はない)メモリアレイにおいて垂直ピラーをビット線(又は代案として、ワード線)として用いてライトワンスアレイを実現するとき、水平なワード線と垂直なビット線の交差部分において、垂直ピラー上にトンネル接合が形成される。3次元メモリアレイを形成する際に、水平なワード線と垂直なビット線との間に、記憶素子に物理的に隣接し、且つ記憶素子に直列に接続される各記憶素子に制御素子が含まれることが好ましい。本発明の範囲及び思想から逸脱することなく、ワード線が垂直になされ、列線が水平になされてもよいことは当業者には理解されたい。本明細書において本発明を説明する際にわかりやすくするために、垂直な選択線は、列線又はビット線と呼ばれ、水平な選択線は、ワード線又は行線と呼ばれる。代わりに、水平な選択線は一般的にドライブ線と呼ばれる場合もあり、垂直な選択線はセンス線と呼ばれる場合もある。ドライブ線及びセンス線の向きは互いに交換できるので、実際には、互いに対して直交する別個の面内に配置され、3次元メモリアレイを形成する1組の第1の選択線及び1組の第2の選択線が存在する。第1又は第2の選択線のうちの一方は、メモリアレイが形成される基板の平面に対して垂直なピラーを形成する。
Claims (20)
- 3次元メモリアレイであって、
平坦な表面(12)を有する基板(10)と、
前記平坦な表面(12)に対して平行な2つ以上の平面(14、16)内に構成される複数の第1の選択線(20)と、
前記基板(10)の前記平坦な表面(12)に対して直交して配置されるピラー内に形成される複数の第2の選択線(18)と、及び
前記複数の第1の選択線(20)及び前記複数の第2の選択線(18)にそれぞれ結合される複数のメモリセル(22)とを含む、3次元メモリアレイ。 - 前記メモリセル(22)のうちの少なくとも1つが、メモリ記憶素子(24)と直列に接続された制御素子(26)を含む、請求項1に記載の3次元メモリアレイ。
- 前記メモリ記憶素子(24)が、前記ピラー(18)のうちの1つのピラーのエッジに沿って形成される、請求項2に記載の3次元メモリアレイ。
- 前記メモリ記憶素子(24)がアンチヒューズデバイスである、請求項2に記載の3次元メモリアレイ。
- 前記メモリ記憶素子(24)が、書込み/消去/書込み、又は書換え可能な相変化材料からなる、請求項2に記載の3次元メモリアレイ。
- 前記制御素子(26)が、前記第1の選択線(20)のうちの1つの選択線のエッジに沿って形成される、請求項2に記載の3次元メモリアレイ。
- 前記制御素子(26)が、1つの点を形成する前記第1の選択線(20)の少なくとも2つのエッジに沿って形成され、それによりプログラミング中の電界が強化される、請求項6に記載の3次元メモリアレイ。
- 前記第1の選択線(20)が蛇行した形状である、請求項6に記載の3次元メモリアレイ。
- 前記制御素子(26)がトンネル接合デバイスである、請求項2に記載の3次元メモリアレイ。
- 少なくとも1つのピラー(18)に電気接続され、且つ個々のピラーの概ね真下に配置される切替え素子(60、61)を前記基板内にさらに含む、請求項1に記載の3次元メモリアレイ。
- メモリ回路を形成する方法であって、
基板(10)に対して概ね平行な平面(14、16)内に第1の選択線(20)のアレイを形成するステップ(62)と、
前記第1の選択線の平面に対して垂直な第2の選択線(18)のアレイを形成するステップ(64)と、及び
個々の第1及び第2の選択線にそれぞれ結合されるメモリセル(22)のアレイを形成するステップ(66)とを含む、メモリ回路を形成する方法。 - 前記メモリセルのアレイを形成するステップが、メモリ記憶デバイス(22)を前記第2の選択線(18)のうちの1つに接触させるステップをさらに含む、請求項11に記載の方法。
- 前記メモリセルのアレイを形成するステップが、トンネル接合デバイスを形成するステップをさらに含む、請求項11に記載の方法。
- 前記メモリセルのアレイを形成するステップが、ドーピングされた半導体材料から制御素子(26)を形成することをさらに含む、請求項11に記載の方法。
- 前記第1の選択線(20)の平面に対して垂直な第2の選択線(18)を形成するステップが、交差する少なくとも2つのエッジにおいて前記メモリセル(22)を接触させることをさらに含む、請求項11に記載の方法。
- 前記第2の選択線(18)の前記形成されたアレイのうちの少なくとも1つに対して概ね隣接して配置されて結合されるトランジスタ(60)を前記基板内に形成するステップをさらに含む、請求項11に記載の方法。
- メモリ回路を製作する方法であって、
基板(10)上に絶縁体(40)を被着するステップ(82)と、
前記基板(10)に対して平行な1つ又は複数の平面(14、16)内に1組の第1の導体(20)を被着するステップ(83)と、
個々の第1の導体(20)上に1組の制御素子(26)を形成するステップ(84)と、
前記第1の導体(20)の前記平面に対して直交する第2の導体(18)を被着するステップ(85)と、及び
前記第2の導体(18)と個々の前記制御素子(26)との間に1組のメモリ記憶素子(24)を形成するステップ(86)とを含む、メモリ回路を製作する方法。 - 請求項17に記載のステップをN回繰り返すことを含む、N段のメモリ回路を製作する方法。
- 前記1組の制御素子(26)を形成するステップが、
前記1組の第1の導体(18)を酸化させるステップと、及び
前記酸化した1組の第1の導体(18)上に1組のパターニングされた第3の導体(42)を被着するステップとをさらに含む、請求項17に記載の方法。 - 前記1組のメモリ記憶素子(24)を形成するステップが、前記1組のパターニングされた第3の導体(42)を酸化させるステップをさらに含む、請求項17に記載の方法。
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PCT/US2003/010351 WO2004100267A1 (en) | 2003-04-03 | 2003-04-03 | Cubic memory array |
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JP (1) | JP4376191B2 (ja) |
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JP2009224778A (ja) * | 2008-03-13 | 2009-10-01 | Samsung Electronics Co Ltd | 抵抗物質および内部電極を使用する不揮発性メモリ装置、これの製造方法、およびこれを含むプロセシングシステム |
JP2010010688A (ja) * | 2008-06-26 | 2010-01-14 | Samsung Electronics Co Ltd | 不揮発性メモリ素子及びその製造方法 |
JP2010114376A (ja) * | 2008-11-10 | 2010-05-20 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2010539729A (ja) * | 2007-09-19 | 2010-12-16 | マイクロン テクノロジー, インク. | クロスポイント型可変抵抗材料メモリの埋め込み低抵抗金属ワード線 |
JP2011243738A (ja) * | 2010-05-18 | 2011-12-01 | Hitachi Ltd | 不揮発性記憶装置およびその製造方法 |
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KR100695168B1 (ko) * | 2006-01-10 | 2007-03-14 | 삼성전자주식회사 | 상변화 물질 박막의 형성방법, 이를 이용한 상변화 메모리소자의 제조방법 |
KR100827697B1 (ko) * | 2006-11-10 | 2008-05-07 | 삼성전자주식회사 | 3차원 구조를 가지는 반도체 메모리 장치 및 셀 어레이구조 |
US7817454B2 (en) * | 2007-04-03 | 2010-10-19 | Micron Technology, Inc. | Variable resistance memory with lattice array using enclosing transistors |
US8679977B2 (en) * | 2007-07-25 | 2014-03-25 | Micron Technology, Inc. | Method and apparatus providing multi-planed array memory device |
KR101539697B1 (ko) * | 2008-06-11 | 2015-07-27 | 삼성전자주식회사 | 수직형 필라를 활성영역으로 사용하는 3차원 메모리 장치,그 제조 방법 및 그 동작 방법 |
KR101489458B1 (ko) * | 2009-02-02 | 2015-02-06 | 삼성전자주식회사 | 3차원 반도체 소자 |
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CN108401468A (zh) * | 2015-09-21 | 2018-08-14 | 莫诺利特斯3D有限公司 | 3d半导体器件和结构 |
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JP2010539729A (ja) * | 2007-09-19 | 2010-12-16 | マイクロン テクノロジー, インク. | クロスポイント型可変抵抗材料メモリの埋め込み低抵抗金属ワード線 |
US9129845B2 (en) | 2007-09-19 | 2015-09-08 | Micron Technology, Inc. | Buried low-resistance metal word lines for cross-point variable-resistance material memories |
US9666800B2 (en) | 2007-09-19 | 2017-05-30 | Micron Technology, Inc. | Buried low-resistance metal word lines for cross-point variable-resistance material memories |
US10090464B2 (en) | 2007-09-19 | 2018-10-02 | Micron Technology, Inc. | Buried low-resistance metal word lines for cross-point variable-resistance material memories |
US10573812B2 (en) | 2007-09-19 | 2020-02-25 | Micron Technology, Inc. | Buried low-resistance metal word lines for cross-point variable-resistance material memories |
US10847722B2 (en) | 2007-09-19 | 2020-11-24 | Micron Technology, Inc. | Buried low-resistance metal word lines for cross-point variable-resistance material memories |
JP2009224778A (ja) * | 2008-03-13 | 2009-10-01 | Samsung Electronics Co Ltd | 抵抗物質および内部電極を使用する不揮発性メモリ装置、これの製造方法、およびこれを含むプロセシングシステム |
JP2010010688A (ja) * | 2008-06-26 | 2010-01-14 | Samsung Electronics Co Ltd | 不揮発性メモリ素子及びその製造方法 |
JP2010114376A (ja) * | 2008-11-10 | 2010-05-20 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2011243738A (ja) * | 2010-05-18 | 2011-12-01 | Hitachi Ltd | 不揮発性記憶装置およびその製造方法 |
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KR20060002905A (ko) | 2006-01-09 |
EP1609186B1 (en) | 2010-09-08 |
KR101018598B1 (ko) | 2011-03-04 |
DE60334153D1 (de) | 2010-10-21 |
CN100539154C (zh) | 2009-09-09 |
CN1774807A (zh) | 2006-05-17 |
AU2003221799A1 (en) | 2004-11-26 |
EP1609186A1 (en) | 2005-12-28 |
WO2004100267A1 (en) | 2004-11-18 |
JP4376191B2 (ja) | 2009-12-02 |
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