JP2006351051A5 - - Google Patents

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Publication number
JP2006351051A5
JP2006351051A5 JP2005171864A JP2005171864A JP2006351051A5 JP 2006351051 A5 JP2006351051 A5 JP 2006351051A5 JP 2005171864 A JP2005171864 A JP 2005171864A JP 2005171864 A JP2005171864 A JP 2005171864A JP 2006351051 A5 JP2006351051 A5 JP 2006351051A5
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JP
Japan
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JP2005171864A
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JP4999287B2 (ja
JP2006351051A (ja
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Priority to JP2005171864A priority Critical patent/JP4999287B2/ja
Priority claimed from JP2005171864A external-priority patent/JP4999287B2/ja
Priority to US11/451,312 priority patent/US7505339B2/en
Publication of JP2006351051A publication Critical patent/JP2006351051A/ja
Publication of JP2006351051A5 publication Critical patent/JP2006351051A5/ja
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Publication of JP4999287B2 publication Critical patent/JP4999287B2/ja
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JP2005171864A 2005-06-13 2005-06-13 スタティック型半導体記憶装置 Active JP4999287B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005171864A JP4999287B2 (ja) 2005-06-13 2005-06-13 スタティック型半導体記憶装置
US11/451,312 US7505339B2 (en) 2005-06-13 2006-06-13 Static semiconductor memory device allowing simultaneous writing of data into a plurality of memory cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005171864A JP4999287B2 (ja) 2005-06-13 2005-06-13 スタティック型半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2006351051A JP2006351051A (ja) 2006-12-28
JP2006351051A5 true JP2006351051A5 (ja) 2008-05-29
JP4999287B2 JP4999287B2 (ja) 2012-08-15

Family

ID=37573206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005171864A Active JP4999287B2 (ja) 2005-06-13 2005-06-13 スタティック型半導体記憶装置

Country Status (2)

Country Link
US (1) US7505339B2 (ja)
JP (1) JP4999287B2 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5101222B2 (ja) * 2007-09-10 2012-12-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR101799482B1 (ko) * 2010-12-29 2017-11-20 삼성전자주식회사 기입 어시스트 회로를 포함하는 정적 메모리 장치
JP5539916B2 (ja) * 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
US9190141B2 (en) 2013-07-30 2015-11-17 Qualcomm Incorporated Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations, and related systems and methods
US11929114B2 (en) * 2021-12-29 2024-03-12 Advanced Micro Devices, Inc. Rapid tag invalidation circuit

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3100617B2 (ja) * 1990-10-23 2000-10-16 沖電気工業株式会社 半導体装置
JPH0756759B2 (ja) * 1990-12-27 1995-06-14 株式会社東芝 スタティック型半導体記憶装置
JP3064498B2 (ja) * 1991-06-21 2000-07-12 日本電気株式会社 半導体記憶装置
JPH06223597A (ja) * 1993-01-27 1994-08-12 Seiko Epson Corp 半導体装置
JPH0778479A (ja) * 1993-09-08 1995-03-20 Fujitsu Ltd 半導体記憶装置
JPH0863997A (ja) * 1994-08-26 1996-03-08 Matsushita Electric Ind Co Ltd 半導体メモリ回路装置
JPH0945081A (ja) * 1995-07-26 1997-02-14 Toshiba Microelectron Corp スタティック型メモリ
JPH09231768A (ja) * 1996-02-21 1997-09-05 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JPH10188571A (ja) * 1996-12-25 1998-07-21 Toshiba Corp 半導体メモリ回路装置及び半導体メモリセルの書き込み方法
KR100240883B1 (ko) * 1997-02-06 2000-01-15 윤종용 Cmos sram 장치
DE19919360C2 (de) * 1999-04-28 2001-09-20 Infineon Technologies Ag Integrierter Speicher mit Bitleitungen, Wortleitungen und Plattenleitungen sowie Betriebsverfahren für einen entsprechenden Speicher
JP2001014895A (ja) * 1999-06-29 2001-01-19 Nec Corp 半導体記憶装置
JP2001084796A (ja) * 1999-09-17 2001-03-30 Sony Corp 半導体記憶装置
US6392941B1 (en) * 2000-12-29 2002-05-21 Cypress Semiconductor Corp. Wordline and pseudo read stress test for SRAM
US6621755B2 (en) * 2001-08-30 2003-09-16 Micron Technology, Inc. Testmode to increase acceleration in burn-in
JP3884976B2 (ja) * 2002-02-22 2007-02-21 株式会社ルネサステクノロジ 半導体記憶装置およびテスト方法
US7016251B2 (en) * 2004-07-29 2006-03-21 International Business Machines Corporation Method and apparatus for initializing SRAM device during power-up
US7154795B2 (en) * 2004-07-30 2006-12-26 United Memories, Inc. Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM
US7483332B2 (en) * 2005-08-11 2009-01-27 Texas Instruments Incorporated SRAM cell using separate read and write circuitry

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