JP2006287227A5 - - Google Patents

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Publication number
JP2006287227A5
JP2006287227A5 JP2006096225A JP2006096225A JP2006287227A5 JP 2006287227 A5 JP2006287227 A5 JP 2006287227A5 JP 2006096225 A JP2006096225 A JP 2006096225A JP 2006096225 A JP2006096225 A JP 2006096225A JP 2006287227 A5 JP2006287227 A5 JP 2006287227A5
Authority
JP
Japan
Prior art keywords
base
die
layer
thermal expansion
counterbalance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006096225A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006287227A (ja
JP5657188B2 (ja
Filing date
Publication date
Priority claimed from US11/095,929 external-priority patent/US7408246B2/en
Application filed filed Critical
Publication of JP2006287227A publication Critical patent/JP2006287227A/ja
Publication of JP2006287227A5 publication Critical patent/JP2006287227A5/ja
Application granted granted Critical
Publication of JP5657188B2 publication Critical patent/JP5657188B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP2006096225A 2005-03-31 2006-03-31 集積回路デバイスにおける反りの制御 Expired - Lifetime JP5657188B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/095929 2005-03-31
US11/095,929 US7408246B2 (en) 2005-03-31 2005-03-31 Controlling warping in integrated circuit devices

Publications (3)

Publication Number Publication Date
JP2006287227A JP2006287227A (ja) 2006-10-19
JP2006287227A5 true JP2006287227A5 (enExample) 2008-05-08
JP5657188B2 JP5657188B2 (ja) 2015-01-21

Family

ID=37069337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006096225A Expired - Lifetime JP5657188B2 (ja) 2005-03-31 2006-03-31 集積回路デバイスにおける反りの制御

Country Status (3)

Country Link
US (4) US7408246B2 (enExample)
JP (1) JP5657188B2 (enExample)
KR (2) KR20060105607A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5128951B2 (ja) * 2005-09-28 2013-01-23 日本碍子株式会社 ヒートシンクモジュール及びその製造方法
JP5466578B2 (ja) * 2010-05-27 2014-04-09 株式会社神戸製鋼所 ダイヤモンド・アルミニウム接合体及びその製造方法
US20130308274A1 (en) * 2012-05-21 2013-11-21 Triquint Semiconductor, Inc. Thermal spreader having graduated thermal expansion parameters
US9028628B2 (en) 2013-03-14 2015-05-12 International Business Machines Corporation Wafer-to-wafer oxide fusion bonding
US9058974B2 (en) 2013-06-03 2015-06-16 International Business Machines Corporation Distorting donor wafer to corresponding distortion of host wafer
KR20170054958A (ko) * 2015-11-10 2017-05-18 주식회사 기가레인 고주파 전력 증폭기
WO2024101163A1 (ja) * 2022-11-08 2024-05-16 日本碍子株式会社 電気化学セル

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339742B2 (enExample) 1971-11-08 1978-10-23
JPS63261863A (ja) * 1987-04-20 1988-10-28 Hitachi Cable Ltd 表面実装用基板
JPH08222658A (ja) * 1995-02-17 1996-08-30 Sumitomo Electric Ind Ltd 半導体素子用パッケージ及びその製造方法
JPH1079405A (ja) 1996-09-04 1998-03-24 Hitachi Ltd 半導体装置およびそれが実装された電子部品
JPH10163386A (ja) * 1996-12-03 1998-06-19 Toshiba Corp 半導体装置、半導体パッケージおよび実装回路装置
US6291899B1 (en) * 1999-02-16 2001-09-18 Micron Technology, Inc. Method and apparatus for reducing BGA warpage caused by encapsulation
US6696748B1 (en) * 2002-08-23 2004-02-24 Micron Technology, Inc. Stress balanced semiconductor packages, method of fabrication and modified mold segment
US7164200B2 (en) * 2004-02-27 2007-01-16 Agere Systems Inc. Techniques for reducing bowing in power transistor devices

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