JP2006228856A - Wiring board for packaging light emitting device - Google Patents

Wiring board for packaging light emitting device Download PDF

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JP2006228856A
JP2006228856A JP2005038775A JP2005038775A JP2006228856A JP 2006228856 A JP2006228856 A JP 2006228856A JP 2005038775 A JP2005038775 A JP 2005038775A JP 2005038775 A JP2005038775 A JP 2005038775A JP 2006228856 A JP2006228856 A JP 2006228856A
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layer
light
light emitting
wiring board
cavity
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JP2006228856A5 (en
JP4436265B2 (en
Inventor
Hisashi Wakako
久 若子
Atsushi Uchida
敦士 内田
Makoto Nagai
誠 永井
Masahito Morita
雅仁 森田
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Priority to JP2005038775A priority Critical patent/JP4436265B2/en
Priority to KR1020050116162A priority patent/KR101154801B1/en
Priority to US11/291,965 priority patent/US7648775B2/en
Priority to EP05026495A priority patent/EP1670295B1/en
Priority to EP11007897.9A priority patent/EP2405723B1/en
Publication of JP2006228856A publication Critical patent/JP2006228856A/en
Publication of JP2006228856A5 publication Critical patent/JP2006228856A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board for packaging a light emitting device capable of surely improving light emission efficiency of the light emitting device to be packaged. <P>SOLUTION: The wiring board 1 for packaging light emitting device comprises a board body 2 of ceramics (insulating material) which has a front surface 3 and a rear surface 4, a cavity 5 which is opened on the front surface 3 of the board body 2 and in which a light emitting device 8 is packaged on its bottom surface 7, and a light reflecting layer 10 formed on a tilted side surface 6 of the cavity 5. The thickness of an Ag layer included on the light reflecting layer 10 is more than 3 μm to 10 μm. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、例えば発光ダイオードのような発光素子を実装するための発光素子実装用配線基板に関する。   The present invention relates to a light emitting element mounting wiring board for mounting a light emitting element such as a light emitting diode.

発光素子を実装する配線基板においては、かかる発光素子を実装するキャビティの側面に金属からなる光反射層を形成すると共に、当該キャビティ内に封止用樹脂を表面が平坦になるようにして充填することで、上記発光素子から発光された光を鮮明なものとすることができる。
そこで、発光素子からの光を外部に効率良く反射するため、セラミックからなる基体の上面に貫通孔を内側に有し且つセラミックからなる枠体を接合し、前記貫通孔の内面に、WおよびMoを含む金属層を被着し、かかる金属層の上にNiメッキ層およびAgメッキ層あるいはAuメッキ層を順次被着する発光素子収納用パッケージが提案されている(例えば、特許文献1参照)。
In a wiring board on which a light emitting element is mounted, a light reflecting layer made of metal is formed on a side surface of a cavity in which the light emitting element is mounted, and a sealing resin is filled in the cavity so that the surface is flat. Thus, the light emitted from the light emitting element can be made clear.
Therefore, in order to efficiently reflect the light from the light emitting element to the outside, a frame body having a through hole inside and a ceramic body is bonded to the upper surface of the ceramic substrate, and W and Mo are bonded to the inner surface of the through hole. There has been proposed a light-emitting element storage package in which a metal layer containing is deposited, and a Ni plating layer and an Ag plating layer or an Au plating layer are sequentially deposited on the metal layer (see, for example, Patent Document 1).

特開2004−207672号公報(第1〜8頁、図1,4)JP 2004-207672 A (pages 1 to 8, FIGS. 1 and 4)

しかしながら、前記発光素子収納用パッケージでは、発光素子から発光された光を直に反射すべく表層に位置するAgメッキ層あるいはAuメッキ層の厚みが0.1〜3μmであるため、例えば、メッキの厚みが不均一によるメッキムラによって、下地のNiメッキ層や前記金属層が貫通孔の内面に露出するおそれがある。この結果、実装した発光素子からの光を効率良く反射できなくなる、という問題点があった。   However, in the light emitting element storage package, the thickness of the Ag plating layer or the Au plating layer located on the surface layer to directly reflect the light emitted from the light emitting element is 0.1 to 3 μm. Due to uneven plating due to uneven thickness, the underlying Ni plating layer or the metal layer may be exposed on the inner surface of the through hole. As a result, there has been a problem that light from the mounted light emitting element cannot be efficiently reflected.

本発明は、前述した背景技術における問題点を解決し、実装すべき発光素子の発光効率を確実に向上し得る発光素子実装用配線基板を提供する、ことを課題とする。   An object of the present invention is to solve the problems in the background art described above and to provide a wiring board for mounting a light emitting element that can surely improve the light emission efficiency of the light emitting element to be mounted.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、発光素子を底面に実装する基板本体のキャビティの側面に形成する光反射層に含まれ、且つ上記発光素子からの光を反射するAg層の厚み、光沢度、あるいは、表面粗さを所定の範囲に規定する、ことに着目して成されたものである。
即ち、本発明の発光素子実装用配線基板(請求項1)は、表面および裏面を有し且つ絶縁材からなる基板本体と、かかる基板本体の表面に開口し且つ底面に発光素子を実装するキャビティと、かかるキャビティの側面に形成される光反射層と、を含み、上記光反射層に含まれるAg層の厚みは、3μm超〜10μmの範囲にある、ことを特徴とする。
In order to solve the above problems, the present invention includes a light reflecting layer formed on a side surface of a cavity of a substrate body on which a light emitting element is mounted on a bottom surface, and a thickness and gloss of an Ag layer that reflects light from the light emitting element. This is made by paying attention to the degree or the surface roughness within a predetermined range.
That is, a wiring board for mounting a light emitting element according to the present invention (Claim 1) has a substrate body having a front surface and a back surface and made of an insulating material, and a cavity that opens on the surface of the substrate body and mounts the light emitting element on the bottom surface And a light reflection layer formed on the side surface of the cavity, wherein the Ag layer included in the light reflection layer has a thickness in the range of more than 3 μm to 10 μm.

上記Ag層の厚みが3μm以下になると、例えばメッキムラにより、被着部分を生じるおそれがあり、一方、Ag層の厚みが10μmを越えると、コスト高になるため、上記範囲とした。かかるAg層の厚みは、望ましくは4μm〜10μm、より望ましくは6μm〜10μmの範囲である。
これによれば、キャビティの側面に形成される光反射層に含まれるAg層の厚みが3μm超〜10μmの範囲にあるため、かかるAg層が例えばメッキによって形成されていても、メッキムラを低減でき且つ比較的均一な厚みでキャビティの側面に形成される。従って、追ってキャビティの底面上に実装する発光素子から発光される光を効率良く反射して外部に放射することが可能となる。
If the thickness of the Ag layer is 3 μm or less, there is a possibility that a deposit portion is generated due to, for example, uneven plating. On the other hand, if the thickness of the Ag layer is more than 10 μm, the cost is increased. The thickness of the Ag layer is desirably in the range of 4 μm to 10 μm, and more desirably in the range of 6 μm to 10 μm.
According to this, since the thickness of the Ag layer included in the light reflecting layer formed on the side surface of the cavity is in the range of more than 3 μm to 10 μm, uneven plating can be reduced even if the Ag layer is formed by plating, for example. In addition, it is formed on the side surface of the cavity with a relatively uniform thickness. Therefore, it becomes possible to efficiently reflect and emit the light emitted from the light emitting element mounted on the bottom surface of the cavity.

尚、前記基板本体を形成する絶縁材は、例えばアルミナを主成分とするセラミック、低温焼成セラミックであるガラス−セラミック、あるいエポキシ系を初めとする各種の樹脂である。また、前記キャビティは、円形、楕円形、または長円形の底面の周囲から傾斜して基板本体の表面に向けて広がる側面を有する全体がほぼ円錐形、ほぼ楕円錐形、あるいは、ほぼ長円錐形のほか、円筒形、楕円筒形、または長円筒形の側面を有する全体が円柱形、楕円柱形、または長円柱形の形態も含まれる。更に、前記発光素子には、発光ダイオードのほか、半導体レーザも含まれる。加えて、前記Ag層は、メッキ、蒸着、スパッタリングなどにより形成される。   The insulating material forming the substrate body is, for example, a ceramic mainly composed of alumina, a glass-ceramic that is a low-temperature fired ceramic, or various resins such as epoxy. The cavity has a substantially conical shape, a substantially elliptical cone shape, or a substantially long conical shape having side surfaces that are inclined from the periphery of a circular, elliptical, or oval bottom surface and extend toward the surface of the substrate body. In addition, a cylindrical shape, an elliptic cylindrical shape, or an overall cylindrical shape having a side surface of a long cylindrical shape is also included. Further, the light emitting element includes a semiconductor laser in addition to the light emitting diode. In addition, the Ag layer is formed by plating, vapor deposition, sputtering, or the like.

また、本発明には、前記Ag層の光沢度は、0.2以上である、発光素子実装用配線基板(請求項2)も含まれる。
これによれば、上記光沢度のAg層に所定の角度で照射された光のほとんどが正反射するため、追ってキャビティの底面上に実装する発光素子から発光される光を一層効率良く確実に反射することが可能となる。
尚、上記Ag層の光沢度が0.2未満になると、照射される光の正反射する割合が少なくなるため、かかる範囲を除外した。かかるAg層の光沢度は、望ましくは0.4〜1.9、より望ましくは0.9〜1.9の範囲である。かかる光沢度は、後述するように、そのGAM値が2に近いほど高く且つGAM値が0に近いほど低いことを示す。
The present invention also includes a wiring board for mounting a light-emitting element (Aspect 2), wherein the Ag layer has a glossiness of 0.2 or more.
According to this, since most of the light irradiated to the glossy Ag layer at a predetermined angle is specularly reflected, the light emitted from the light emitting element mounted on the bottom surface of the cavity is reflected more efficiently and reliably. It becomes possible to do.
In addition, when the glossiness of the Ag layer was less than 0.2, the ratio of regular reflection of the irradiated light was reduced, so this range was excluded. The glossiness of such an Ag layer is desirably in the range of 0.4 to 1.9, more desirably 0.9 to 1.9. As will be described later, the glossiness is higher as the GAM value is closer to 2 and lower as the GAM value is closer to 0.

更に、本発明には、前記Ag層の表面粗さは、Ra(中心線平均粗さ)で3μm以下である、発光素子実装用配線基板(請求項3)も含まれる。
これによれば、上記表面粗さのAg層に所定の角度で照射された光は、かかるAg層の平滑な表面によって、ほとんどの光が正反射するため、追ってキャビティの底面上に実装する発光素子から発光される光を一層効率良く確実に反射することが可能となる。
尚、上記Ag層の表面粗さ(Ra)が3μmを越えると、照射される光のうち相当量が乱反射するため、かかる範囲を除外した。かかるAg層の表面粗さ(Ra)は、望ましくは1.5μm以下、より望ましくは1μm以下の範囲である。
Furthermore, the present invention includes a light emitting element mounting wiring board (Claim 3) in which the surface roughness of the Ag layer is 3 μm or less in terms of Ra (center line average roughness).
According to this, most of the light irradiated to the Ag layer having the above surface roughness at a predetermined angle is specularly reflected by the smooth surface of the Ag layer. It becomes possible to reflect light emitted from the element more efficiently and reliably.
When the surface roughness (Ra) of the Ag layer exceeds 3 μm, a considerable amount of the irradiated light is irregularly reflected, so this range is excluded. The surface roughness (Ra) of the Ag layer is desirably 1.5 μm or less, more desirably 1 μm or less.

付言すれば、本発明には、前記光反射層に含まれるAg層の厚みを3μm超〜10μm、望ましくは4μm〜10μm、より望ましくは6μm〜10μmの範囲とし、上記Ag層の光沢度を0.2以上、望ましくは0.4〜1.9、より望ましくは0.9〜1.9の範囲とする、発光素子実装用配線基板も含まれ得る。
また、本発明には、前記光反射層に含まれるAg層の厚みを3μm超〜10μm、望ましくは4μm〜10μm、より望ましくは6μm〜10μmの範囲とし、上記Ag層の表面粗さをRaで3μm以下、望ましくは1.5μm以下、より望ましくは1μm以下の範囲とする、発光素子実装用配線基板も含まれ得る。
これらによる場合、前記発光素子から発光される光を、一層効率良く確実に反射することが可能となる。
In other words, in the present invention, the thickness of the Ag layer included in the light reflection layer is set to be in the range of more than 3 μm to 10 μm, preferably 4 μm to 10 μm, more preferably 6 μm to 10 μm, and the glossiness of the Ag layer is 0. It is also possible to include a light emitting element mounting wiring board that is .2 or more, preferably 0.4 to 1.9, more preferably 0.9 to 1.9.
In the present invention, the thickness of the Ag layer contained in the light reflection layer is in the range of more than 3 μm to 10 μm, preferably 4 μm to 10 μm, more preferably 6 μm to 10 μm, and the surface roughness of the Ag layer is Ra. A light-emitting element mounting wiring board having a range of 3 μm or less, desirably 1.5 μm or less, and more desirably 1 μm or less may be included.
In these cases, the light emitted from the light emitting element can be more efficiently and reliably reflected.

以下において、本発明を実施するための最良の形態について説明する。
図1は、本発明による発光素子実装用配線基板(以下、単に配線基板と称する)1を示す垂直断面図、図2は、図1中の一点鎖線部分Xの部分拡大図である。
配線基板1は、図1に示すように、表面3および裏面4を有する基板本体2と、かかる基板本体2の表面3に開口し且つ底面7に発光ダイオード(発光素子)8を実装するキャビティ5と、かかるキャビティ5の傾斜した側面6に形成される光反射層10と、を含んでいる。
上記基板本体2は、一体に積層された例えばアルミナ系のセラミック(絶縁材)層s1〜s7からなり、平面視が約5mm角の正方形で約1mmの厚みを有する。
In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a vertical sectional view showing a light emitting element mounting wiring board (hereinafter simply referred to as a wiring board) 1 according to the present invention, and FIG. 2 is a partially enlarged view of an alternate long and short dash line portion X in FIG.
As shown in FIG. 1, the wiring substrate 1 includes a substrate body 2 having a front surface 3 and a back surface 4, and a cavity 5 that opens to the front surface 3 of the substrate body 2 and mounts a light emitting diode (light emitting element) 8 on the bottom surface 7. And a light reflecting layer 10 formed on the inclined side surface 6 of the cavity 5.
The substrate body 2 is composed of, for example, alumina-based ceramic (insulating material) layers s1 to s7 laminated together, and has a square of about 5 mm square in plan view and a thickness of about 1 mm.

尚、前記セラミック層s1〜s7に替えて、ガラス−セラミック(絶縁材)層、あるいは例えばBT樹脂やエポキシ系樹脂などの樹脂(絶縁材)層を用いても良い。上記ガラス−セラミックは、焼成温度が1000℃以下のガラス−アルミナ系などの低温焼成セラミックである。
図1に示すように、キャビティ5は、平面視が円形の底面7と、かかる底面7の周囲から傾斜しつつセラミック層s5〜s7を貫通し且つ基板本体2の表面3に向けて広がる側面6と、を有し、全体がほぼ円錐形を呈する。尚、側面6の仰角は、30度以上で且つ80度以下の範囲において適宜選定される。また、上記キャビティ5は、焼成によりセラミック層s5〜s7となる3層の単位グリーンシートまたは大版のグリーンシートを積層して得られた上側グリーンシート積層体に、所要のクリアランスを介する打ち抜き加工、あるいは予め形成した円柱形の貫通孔に円錐形の金型を押し込んで、側面がほぼ円錐形の貫通孔を形成し、その下に焼成によりセラミック層s1〜s4となる下側グリーンシート積層体を積層することで形成される。
Instead of the ceramic layers s1 to s7, a glass-ceramic (insulating material) layer or a resin (insulating material) layer such as a BT resin or an epoxy resin may be used. The glass-ceramic is a low-temperature fired ceramic such as a glass-alumina system having a firing temperature of 1000 ° C. or lower.
As shown in FIG. 1, the cavity 5 has a circular bottom surface 7 in plan view, and a side surface 6 that extends from the periphery of the bottom surface 7 through the ceramic layers s <b> 5 to s <b> 7 toward the surface 3 of the substrate body 2. And the whole has a substantially conical shape. The elevation angle of the side surface 6 is appropriately selected within a range of 30 degrees or more and 80 degrees or less. Further, the cavity 5 is formed by punching through a required clearance on an upper green sheet laminate obtained by laminating three unit green sheets or large green sheets that become ceramic layers s5 to s7 by firing, Alternatively, a conical mold is pushed into a cylindrical through-hole formed in advance to form a through-hole having a substantially conical side surface, and a lower green sheet laminate that becomes ceramic layers s1 to s4 by firing is formed thereunder. It is formed by stacking.

図1に示すように、前記キャビティ5の側面6のほぼ全面には、後述するAg層16などを含む光反射層10がほぼ円錐形にして形成されている。
尚、かかる光反射層10の下地には、基板本体2の絶縁材に前記アルミナ系セラミックを用いる際には、例えばWやMoのような高融点合金が適用され、前記ガラス−セラミックを用いる際には、同時焼成が可能なAgやCuが適用される。また、基板本体2の絶縁材に、前記エポキシ系樹脂などを用いる際には、公知のフォトグラフィ技術(例えばサブトラクティブ法など)によりパターン形成が可能なCuなどが適用される。
また、図1に示すように、キャビティ5の底面7上には、W、Mo、Ag、またはCuからなり且つ互いに異なる回路を形成する一対のパッド17が、底面7中央に位置する発光ダイオード8の実装エリアを挟んで離間しつつ形成されている。
As shown in FIG. 1, a light reflecting layer 10 including a later-described Ag layer 16 and the like is formed in a substantially conical shape on almost the entire side surface 6 of the cavity 5.
When the alumina-based ceramic is used as the insulating material of the substrate body 2 as the base of the light reflecting layer 10, for example, a refractory alloy such as W or Mo is applied, and the glass-ceramic is used. In this case, Ag or Cu capable of simultaneous firing is applied. Moreover, when using the said epoxy resin etc. for the insulating material of the board | substrate body 2, Cu etc. which can form a pattern by a well-known photography technique (for example, subtractive method etc.) are applied.
Further, as shown in FIG. 1, on the bottom surface 7 of the cavity 5, a pair of pads 17 made of W, Mo, Ag, or Cu and forming different circuits are located at the center of the bottom surface 7. The mounting areas are spaced apart from each other.

キャビティ5の底面7上には、追って、ロウ材9またはエポキシ系樹脂の接着剤を介して、発光ダイオード8が実装される。その際に、一対のパッド17との間でボンディングワイヤwが個別に結線される。かかるキャビティ5内には、固化前の封止用樹脂が充填され、その表面が基板本体2の表面3と面一にして固化される。尚、上記ロウ材9は、例えば、Sn−Ag系などの低融点合金からなる。
更に、図1に示すように、前記一対のパッド17には、セラミック層s1〜s4を貫通する一対のビア導体18の上端が個別に接続され、各ビア導体18の下端は、基板本体2の裏面4に形成される一対の裏面電極19に個別に接続されている。各ビア導体18には、セラミック層s1〜s4間に形成される図示しない配線層と個別に接続されている。尚、図1で左右対称に位置するパッド17、ビア導体18、および裏面電極19からなる2組の回路は、例えば一方が接地回路で他方が信号回路を構成している。また、ビア導体18、上記配線層、および裏面電極19は、W、Mo、Ag、またはCuからなる。更に、セラミック層s5〜s7間にも、各回路に導通する図示しない配線層やビア導体が形成されている。
A light emitting diode 8 is mounted on the bottom surface 7 of the cavity 5 via a brazing material 9 or an epoxy resin adhesive. At that time, the bonding wires w are individually connected between the pair of pads 17. The cavity 5 is filled with a sealing resin before solidification, and the surface thereof is solidified with the surface 3 of the substrate body 2. The brazing material 9 is made of a low melting point alloy such as Sn—Ag.
Further, as shown in FIG. 1, the upper ends of a pair of via conductors 18 penetrating the ceramic layers s1 to s4 are individually connected to the pair of pads 17, and the lower ends of the via conductors 18 are connected to the substrate body 2. The pair of back surface electrodes 19 formed on the back surface 4 are individually connected. Each via conductor 18 is individually connected to a wiring layer (not shown) formed between the ceramic layers s1 to s4. In FIG. 1, for example, one of the two sets of the circuit composed of the pad 17, the via conductor 18 and the back electrode 19 which are positioned symmetrically forms a ground circuit and the other constitutes a signal circuit. The via conductor 18, the wiring layer, and the back electrode 19 are made of W, Mo, Ag, or Cu. Further, between the ceramic layers s5 to s7, wiring layers and via conductors (not shown) that are connected to the respective circuits are formed.

光反射層10は、図2に示すように、キャビティ5の側面6の上に形成されるW、Mo、Ag、またはCuからなる下地の金属層11、その上に形成されるNiメッキ層12、かかるNiメッキ層12の上に形成されるAuメッキ層15、およびかかるAuメッキ層15の上に形成されるAgメッキ層(Ag層)16からなる。
上記金属層11は、前記セラミック層s1〜s7と同時焼成されるWまたはMoであるか、あるいはガラス−セラミックと同時焼成されるCuまたはAgであり、約10〜数10μmの厚みを有する。尚、基板本体2の絶縁材がエポキシ系樹脂などからなる場合には、上記金属層11は、Cuメッキ層となる。
As shown in FIG. 2, the light reflecting layer 10 includes a base metal layer 11 made of W, Mo, Ag, or Cu formed on the side surface 6 of the cavity 5, and a Ni plating layer 12 formed thereon. The Au plating layer 15 formed on the Ni plating layer 12 and the Ag plating layer (Ag layer) 16 formed on the Au plating layer 15.
The metal layer 11 is W or Mo co-fired with the ceramic layers s1 to s7, or Cu or Ag co-fired with the glass-ceramic, and has a thickness of about 10 to several tens of micrometers. When the insulating material of the substrate body 2 is made of an epoxy resin or the like, the metal layer 11 is a Cu plating layer.

また、前記Niメッキ層12は、金属メッキの下地層であり、図2に示すように、厚みが0.5〜2μmの第1Niメッキ層13と、その上に位置し且つ厚みが1〜9μmの第2Niメッキ層14とからなり、全体の厚みの範囲は、1.5〜11μmである。第1Niメッキ層13は、無電解Niメッキまたは電解Niメッキにより形成され、第2Niメッキ層14は、電解Niメッキにより形成される。
更に、前記Auメッキ層15は、主に第2Niメッキ層14とAgメッキ層16との密着性を十分なものとするために被覆され、電解Auメッキによって、厚みを0.03〜0.2μmの範囲にして形成される。
The Ni plating layer 12 is an underlayer for metal plating. As shown in FIG. 2, the Ni plating layer 13 having a thickness of 0.5 to 2 μm and a thickness of 1 to 9 μm are disposed on the first Ni plating layer 13. 2nd Ni plating layer 14, and the range of the whole thickness is 1.5 to 11 μm. The first Ni plating layer 13 is formed by electroless Ni plating or electrolytic Ni plating, and the second Ni plating layer 14 is formed by electrolytic Ni plating.
Furthermore, the Au plating layer 15 is mainly coated to ensure sufficient adhesion between the second Ni plating layer 14 and the Ag plating layer 16, and the thickness is 0.03 to 0.2 μm by electrolytic Au plating. It is formed in the range of

前記Agメッキ層16は、前記発光ダイオード8から発光される光を直に反射する層であり、電解Agメッキにより、厚みを3〜10μmの範囲にして形成される。尚、かかるAgメッキ層16の望ましい厚みは4〜10μm、より望ましくは6〜10μmの範囲である。また、光反射層10の上・下端付近では、Agメッキ層16の厚みが薄くなり易いので、上記厚みの下限値は、少なくとも光反射層10の上・下端付近において満たすようにされる。
また、Agメッキ層16の表面粗さ(Ra)は、3μm以下、望ましくは1.5μm以下、より望ましくは1μm以下の範囲である。
更に、上記Agメッキ層16の光沢度(GAM値)は、0.2以上、望ましくは0.4〜1.9、より望ましくは0.9〜1.9の範囲である。
尚、上記光沢度(GAM値)は、数式1により算出される。
The Ag plating layer 16 is a layer that directly reflects the light emitted from the light emitting diode 8, and is formed by electrolytic Ag plating to have a thickness in the range of 3 to 10 μm. The desirable thickness of the Ag plating layer 16 is in the range of 4 to 10 [mu] m, more preferably 6 to 10 [mu] m. Further, since the thickness of the Ag plating layer 16 tends to be thin near the upper and lower ends of the light reflecting layer 10, the lower limit value of the thickness is satisfied at least near the upper and lower ends of the light reflecting layer 10.
The surface roughness (Ra) of the Ag plating layer 16 is 3 μm or less, desirably 1.5 μm or less, and more desirably 1 μm or less.
Further, the gloss (GAM value) of the Ag plating layer 16 is 0.2 or more, desirably 0.4 to 1.9, more desirably 0.9 to 1.9.
The glossiness (GAM value) is calculated by Equation 1.

Figure 2006228856
Figure 2006228856

前記光沢度(GAM値)は、図3に示す方法により測定される。
予め、図示しない定盤の上にAgメッキ層16を含む前記光反射層10を、Agメッキ層16を上にして固定する。また、図3に示すように、上記定盤の上方には、斜め45度で投光器20を、垂直方向に沿って受光器22を配置しておく。
次に、上記光反射層10に対し、投光器20から45度の入射角度で光Aを放射する。かかる光Aは、光反射層10の表層に位置するAgメッキ層16に正反射するため、その大半が45度の反射角度の光Cとなる。しかし、一部の光Bは、Agメッキ層16の表面におけるうねりや表面粗さにより、乱反射する光Bとなって受光器22に受光される。かかる光Bの量を当該受光器22などで測定する。
前記数式1で示すように、光Bが少なくなるほど、光沢度は2に近付き、且つ光Bが多くなるほど、光沢度は0に近付くことになる。
The glossiness (GAM value) is measured by the method shown in FIG.
The light reflecting layer 10 including the Ag plating layer 16 is fixed in advance on a surface plate (not shown) with the Ag plating layer 16 facing upward. Further, as shown in FIG. 3, the projector 20 is disposed at an angle of 45 degrees above the surface plate, and the light receiver 22 is disposed along the vertical direction.
Next, light A is emitted from the projector 20 at an incident angle of 45 degrees with respect to the light reflecting layer 10. Since the light A is regularly reflected by the Ag plating layer 16 located on the surface layer of the light reflecting layer 10, most of the light A becomes light C having a reflection angle of 45 degrees. However, a part of the light B is received by the light receiver 22 as light B which is irregularly reflected due to the undulation and surface roughness on the surface of the Ag plating layer 16. The amount of the light B is measured by the light receiver 22 or the like.
As shown in Equation 1, the smaller the light B is, the closer the glossiness is to 2, and the more the light B is, the closer the glossiness is to 0.

即ち、前記光沢度が0.2以上、望ましくは0.4〜1.9、より望ましくは0.9〜1.9の範囲の範囲にあるAgメッキ層16は、前記厚みおよび表面粗さ(Ra)と併せて、表面がかなり平滑で且つ均一な厚みを有することが理解される。このため、前記厚み、光沢度、および表面粗さ(Ra)の範囲にあるAgメッキ層16を含む光反射層10は、前記キャビティ5の側面6に形成されているため、追って底面7上に実装される発光ダイオード8から発光される光を効率良く確実に反射して外部に放射する。
従って、以上のような配線基板1によれば、追ってキャビティ5の底面7上に実装されるダイオード8の光を、効率良く確実に反射することができる。
That is, the Ag plating layer 16 having the glossiness of 0.2 or more, desirably 0.4 to 1.9, more desirably 0.9 to 1.9, has the thickness and surface roughness ( In conjunction with Ra), it is understood that the surface has a fairly smooth and uniform thickness. For this reason, since the light reflection layer 10 including the Ag plating layer 16 in the range of the thickness, the glossiness, and the surface roughness (Ra) is formed on the side surface 6 of the cavity 5, the light reflection layer 10 is formed on the bottom surface 7 later. The light emitted from the mounted light emitting diode 8 is efficiently and reliably reflected and radiated to the outside.
Therefore, according to the wiring substrate 1 as described above, the light of the diode 8 mounted on the bottom surface 7 of the cavity 5 can be reflected efficiently and reliably.

図4は、異なる形態の配線基板1aを示す前記と同様の垂直断面図である。
配線基板1aは、図4に示すように、表面3および裏面4を有する前記同様の基板本体2aと、かかる基板本体2aの表面3に開口し且つ底面7に発光ダイオード8を実装するキャビティ5aと、かかるキャビティ5aの垂直な側面6aに形成される光反射層10と、を含んでいる。
尚、以下においては、前記配線基板1と相違する部分について説明する。
キャビティ5aは、図4に示すように、平面視が円形の底面7と、かかる底面7の周囲から垂直に立設し且つセラミック層s8〜s10を貫通する円筒形の側面6aとを有し、全体が円柱形を呈する。
FIG. 4 is a vertical sectional view similar to the above showing a wiring board 1a of a different form.
As shown in FIG. 4, the wiring board 1 a includes a substrate body 2 a having the front surface 3 and the back surface 4, a cavity 5 a that opens on the surface 3 of the substrate body 2 a and mounts the light emitting diode 8 on the bottom surface 7. And a light reflection layer 10 formed on the vertical side surface 6a of the cavity 5a.
In the following description, portions different from the wiring board 1 will be described.
As shown in FIG. 4, the cavity 5a has a bottom surface 7 that is circular in plan view, and a cylindrical side surface 6a that stands vertically from the periphery of the bottom surface 7 and penetrates the ceramic layers s8 to s10. The whole is cylindrical.

尚、前記キャビティ5aは、焼成によりセラミック層s8〜s10となる3層のグリーンシートを、最小限クリアランスを介するパンチとダイとによる打ち抜き加工で、側面が円筒形の貫通孔を有する上側グリーンシート積層体を形成し、これと前記下側グリーンシート積層体とを積層することで形成される。
円筒形の側面6aに、前記図2で示したように、W、Mo、Ag、またはCuからなる金属層11、Niメッキ層12(13,14)、Auメッキ層15、およびAgメッキ層(Ag層)16からなる円筒形の光反射層10が、前記同様にして形成されている。
以上のような配線基板1aによっても、前記配線基板1と同様に作用を発揮し且つ効果を奏することが可能である。
The cavity 5a is formed by punching a three-layer green sheet, which becomes ceramic layers s8 to s10 by firing, by punching with a punch and a die through a minimum clearance, and an upper side green sheet laminate having a cylindrical through hole on the side surface. The body is formed, and this and the lower green sheet laminate are laminated.
On the cylindrical side surface 6a, as shown in FIG. 2, the metal layer 11 made of W, Mo, Ag, or Cu, the Ni plating layer 12 (13, 14), the Au plating layer 15, and the Ag plating layer ( A cylindrical light reflection layer 10 made of (Ag layer) 16 is formed in the same manner as described above.
Even with the wiring board 1a as described above, the same effects as those of the wiring board 1 can be exhibited and the effects can be achieved.

図5は、前記配線基板1aの応用形態である配線基板1bを示す前記と同様の垂直断面図、図6は、図5中の一点鎖線部分Yの部分拡大図である。
配線基板1bは、図5に示すように、表面3および裏面4を有する前記同様の基板本体2bと、かかる基板本体2bの表面3に開口し且つやや大径の底面7に発光ダイオード8を実装するキャビティ5bと、かかるキャビティ5bの垂直な側面6bと底面7とにまたがって形成される光反射層10bと、を含んでいる。
尚、以下においては、前記配線基板1aと相違する部分について説明する。
FIG. 5 is a vertical sectional view similar to the above showing a wiring board 1b which is an application form of the wiring board 1a, and FIG. 6 is a partially enlarged view of a one-dot chain line portion Y in FIG.
As shown in FIG. 5, the wiring board 1b has the same substrate body 2b having the front surface 3 and the back surface 4, and a light emitting diode 8 mounted on the bottom surface 7 that opens to the front surface 3 of the substrate body 2b and has a slightly larger diameter. And a light reflecting layer 10b formed across the vertical side surface 6b and the bottom surface 7 of the cavity 5b.
In the following description, parts different from the wiring board 1a will be described.

図5,図6に示すように、光反射層10bは、平面視がリング形で且つ垂直断面がほぼ直角三角形を呈し、キャビティ5bの底面7と側面6bとに沿ってほぼL字形に形成されるW、Mo、Ag、またはCuからなる金属層11と、その内側に沿ってほぼL字形に形成される第1Niメッキ層13と、を含み、金属層11は、セラミック層s4,s8間に沿って水平に延びる配線部11bを含んでいる。
図6に示すように、ほぼL字形を呈する第1Niメッキ層13の内隅側には、断面がほぼ直角三角形のAgロウ材16bが形成されている。
As shown in FIGS. 5 and 6, the light reflecting layer 10b has a ring shape in plan view and a vertical section of a substantially right triangle, and is formed in an approximately L shape along the bottom surface 7 and the side surface 6b of the cavity 5b. A metal layer 11 made of W, Mo, Ag, or Cu, and a first Ni plating layer 13 formed in an approximately L shape along the inside thereof. The metal layer 11 is interposed between the ceramic layers s4 and s8. The wiring part 11b extended horizontally is included.
As shown in FIG. 6, an Ag brazing material 16 b having a substantially right-angled cross section is formed on the inner corner side of the first Ni plating layer 13 having an approximately L shape.

図6に示すように、上記Agロウ材16bの傾斜した外側面と、その上下に露出する第1Niメッキ層13の上・下端部にまたがって、第2Niメッキ層14が形成され、その上にAuメッキ層15およびAgメッキ層(Ag層)16が、前記同様の厚みで順次形成されている。かかるAg層16も、前記範囲の厚み、光沢度、および表面粗さ(Ra)を備えている。尚、図6に示すように、Ag層16の上・下端部は、その厚みが薄くなり易いので、前記3μm以上の厚みは、少なくともかかる位置に適用される。
以上のような配線基板1bによっても、前記配線基板1,1aと同様に作用を発揮し且つ効果を奏することが可能である。
As shown in FIG. 6, the second Ni plating layer 14 is formed across the inclined outer surface of the Ag brazing material 16b and the upper and lower ends of the first Ni plating layer 13 exposed above and below the Ag brazing material 16b. An Au plating layer 15 and an Ag plating layer (Ag layer) 16 are sequentially formed with the same thickness as described above. The Ag layer 16 also has the thickness, glossiness, and surface roughness (Ra) within the above ranges. As shown in FIG. 6, the upper and lower end portions of the Ag layer 16 are likely to be thin. Therefore, the thickness of 3 μm or more is applied at least to such a position.
Also with the wiring board 1b as described above, it is possible to exert the same effect as the wiring boards 1 and 1a and to achieve the effect.

本発明は、以上において説明した各家遺体に限定されるものではない。
キャビティは、全体がほぼ長円錐形、ほぼ楕円錐形、長円柱形、楕円柱形を呈する形態とすると共に、それらの側面に、前記光反射層10,10bを形成しても良い。あるいは、平面視が正方形で且つ全体がほぼ正四角錐形、あるいは平面視が長方形で且つ全体がほぼ四角錐形を呈するキャビティとし、それらの隣接する各側面間のコーナに表面が凹んでカーブするようにロウ材を充填すると共に、かかるロウ材と各側面とに前記光反射層10,10bを形成しても良い。
また、キャビティは、1つの基板本体に複数個を併設して形成しても良い。あるいは、同一の基板本体に異なる形状のキャビティを併設して形成しても良い。
更に、前記Niメッキ層12(13,14)やAuメッキ層15も、蒸着やスパッタリングにより形成されるNi層やAu層としても良い。
The present invention is not limited to the individual remains described above.
The entire cavity may have a substantially conical shape, a substantially elliptical cone shape, a long cylindrical shape, or an elliptical columnar shape, and the light reflecting layers 10 and 10b may be formed on the side surfaces thereof. Alternatively, the cavity may have a square shape in plan view and a substantially regular pyramid shape, or a rectangular shape in plan view and a substantially quadrangular pyramid shape, and the surface may be curved at a corner between adjacent sides. The light reflecting layers 10 and 10b may be formed on the brazing material and each side surface.
Further, a plurality of cavities may be formed on a single substrate body. Alternatively, cavities having different shapes may be provided on the same substrate body.
Further, the Ni plating layer 12 (13, 14) and the Au plating layer 15 may be Ni layers or Au layers formed by vapor deposition or sputtering.

本発明における一形態の配線基板を示す垂直断面図。The vertical sectional view showing the wiring board of one form in the present invention. 図1中の一点鎖線部分Xの部分拡大図。The elements on larger scale of the dashed-dotted line part X in FIG. 光沢度の測定方法を示す概略図。Schematic which shows the measuring method of glossiness. 異なる形態の配線基板を示す垂直断面図。The vertical sectional view which shows the wiring board of a different form. 上記配線基板の応用形態を示す垂直断面図。The vertical sectional view which shows the application form of the said wiring board. 図5中の一点鎖線部分Yの部分拡大図。The elements on larger scale of the dashed-dotted line part Y in FIG.

符号の説明Explanation of symbols

1,1a,1b…発光素子実装用配線基板
2,2a,2b…基板本体
3…………………表面
4…………………裏面
5,5a,5b…キャビティ
6,6a,6b…側面
7…………………底面
8…………………発光ダイオード(発光素子)
10,10b……光反射層
16………………Agメッキ層(Ag層)
DESCRIPTION OF SYMBOLS 1, 1a, 1b ... Light-emitting-element mounting wiring board 2, 2a, 2b ... Substrate main body 3 ............... Front side 4 ............... Back side 5, 5a, 5b ... Cavity 6, 6a, 6b … Side 7 ………………… Bottom 8 ………………… Light Emitting Diode (Light Emitting Element)
10, 10b …… Light reflecting layer 16 ……………… Ag plating layer (Ag layer)

Claims (3)

表面および裏面を有し且つ絶縁材からなる基板本体と、
上記基板本体の表面に開口し且つ底面に発光素子を実装するキャビティと、
上記キャビティの側面に形成される光反射層と、を含み、
上記光反射層に含まれるAg層の厚みは、3μm超〜10μmの範囲にある、
ことを特徴とする発光素子実装用配線基板。
A substrate body having a front surface and a back surface and made of an insulating material;
A cavity that opens on the surface of the substrate body and mounts the light emitting element on the bottom surface;
A light reflecting layer formed on a side surface of the cavity,
The thickness of the Ag layer contained in the light reflecting layer is in the range of more than 3 μm to 10 μm.
A wiring board for mounting a light-emitting element.
前記Ag層の光沢度は、0.2以上である、
ことを特徴とする請求項1に記載の発光素子実装用配線基板。
The glossiness of the Ag layer is 0.2 or more.
The wiring board for mounting a light emitting element according to claim 1.
前記Ag層の表面粗さは、Raで3μm以下である、
ことを特徴とする請求項1または2に記載の発光素子実装用配線基板。
The surface roughness of the Ag layer is 3 μm or less in Ra.
The wiring board for mounting a light-emitting element according to claim 1 or 2.
JP2005038775A 2004-12-03 2005-02-16 Light-emitting element mounting wiring board Expired - Fee Related JP4436265B2 (en)

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JP2005038775A JP4436265B2 (en) 2005-02-16 2005-02-16 Light-emitting element mounting wiring board
KR1020050116162A KR101154801B1 (en) 2004-12-03 2005-12-01 Ceramic package for receiving ceramic substrate and light emitting device
US11/291,965 US7648775B2 (en) 2004-12-03 2005-12-02 Ceramic substrate, ceramic package for housing light emitting element
EP05026495A EP1670295B1 (en) 2004-12-03 2005-12-05 Ceramic substrate, ceramic package for housing light emitting element
EP11007897.9A EP2405723B1 (en) 2004-12-03 2005-12-05 Ceramic package for housing light emitting element

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JP2011040668A (en) * 2009-08-18 2011-02-24 Shin-Etsu Chemical Co Ltd Optical semiconductor device
JP2011216588A (en) * 2010-03-31 2011-10-27 Toshiba Corp Light emitting element module-substrate, light emitting element module, and lighting device
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US8378369B2 (en) 2008-09-09 2013-02-19 Showa Denko K.K. Light emitting unit, light emitting module, and display device
JP2010067720A (en) * 2008-09-09 2010-03-25 Showa Denko Kk Light emitting device and light emitting module
WO2010029872A1 (en) * 2008-09-09 2010-03-18 昭和電工株式会社 Light emitting unit, light emitting module, and display device
TWI425655B (en) * 2008-09-09 2014-02-01 Showa Denko Kk A light emitting device, a light emitting module, and a display device
JP2010067862A (en) * 2008-09-11 2010-03-25 Showa Denko Kk Light emitting device, light emitting module, and display device
JP2010067863A (en) * 2008-09-11 2010-03-25 Showa Denko Kk Light emitting device, and light emitting module
JP2011040668A (en) * 2009-08-18 2011-02-24 Shin-Etsu Chemical Co Ltd Optical semiconductor device
JP2011216588A (en) * 2010-03-31 2011-10-27 Toshiba Corp Light emitting element module-substrate, light emitting element module, and lighting device
JP2013051449A (en) * 2010-11-25 2013-03-14 Kyocera Corp Substrate for mounting light emitting element and light emitting device
US9170003B2 (en) 2010-11-25 2015-10-27 Kyocera Corporation Light-emitting element mounting substrate and light-emitting device
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WO2019059690A3 (en) * 2017-09-22 2019-05-16 엘지이노텍 주식회사 Light-emitting device package
US11322667B2 (en) 2017-09-22 2022-05-03 Suzhou Lekin Semiconductor Co., Ltd. Light-emitting device package

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