JP2006148044A - フラッシュメモリ素子の製造方法 - Google Patents
フラッシュメモリ素子の製造方法 Download PDFInfo
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- JP2006148044A JP2006148044A JP2005150605A JP2005150605A JP2006148044A JP 2006148044 A JP2006148044 A JP 2006148044A JP 2005150605 A JP2005150605 A JP 2005150605A JP 2005150605 A JP2005150605 A JP 2005150605A JP 2006148044 A JP2006148044 A JP 2006148044A
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000137 annealing Methods 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 238000009279 wet oxidation reaction Methods 0.000 claims description 7
- 230000001351 cycling effect Effects 0.000 abstract description 28
- 238000005121 nitriding Methods 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 29
- 238000005468 ion implantation Methods 0.000 description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229920005591 polysilicon Polymers 0.000 description 20
- 229910052757 nitrogen Inorganic materials 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 12
- 239000007789 gas Substances 0.000 description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 210000003323 beak Anatomy 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H10B—ELECTRONIC MEMORY DEVICES
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
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- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】 フラッシュメモリ素子の製造方法は、半導体基板上に酸化膜を形成する段階と、N2ガス雰囲気でプレアニーリング工程を行う段階と、流量5〜15slmのN2O雰囲気で10〜60分間メインアニーリング工程を行って前記酸化膜を窒化させ、窒化酸化膜を形成する段階と、N2ガス雰囲気でポストアニーリング工程を行う段階とを含む。
【選択図】 図4
Description
12 第1酸化膜
14 窒化酸化膜
16 第1ポリシリコン膜
18 第2ポリシリコン膜
20 ONO膜
22 第3ポリシリコン膜
24 タングステン膜
26 ハードマスク膜
28a 高電圧素子用ゲート
28b セルゲート
30 ソース及びドレイン接合
Claims (9)
- (a)半導体基板上に酸化膜を形成する段階と、
(b)N2ガス雰囲気でプレアニーリング工程を行う段階と、
(c)流量5〜15slmのN2O雰囲気で10〜60分間メインアニーリング工程を行って前記酸化膜を窒化させ、窒化酸化膜を形成する段階と、
(d)N2ガス雰囲気でポストアニーリング工程を行う段階とを含むことを特徴とするフラッシュメモリ素子の製造方法。 - 前記(a)段階は、湿式酸化工程を行う段階と、
N2ガス雰囲気でアニーリングを行って前記酸化膜を形成する段階とからなることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。 - 前記湿式酸化工程の温度は750〜850℃であることを特徴とする請求項2に記載のフラッシュメモリ素子の製造方法。
- 前記N2ガス雰囲気のアニーリング工程を900〜910℃の温度で20〜30分間行うことを特徴とする請求項2に記載のフラッシュメモリ素子の製造方法。
- 前記酸化膜の厚さは60〜90Åであることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記プレアニーリング工程の温度は850〜950℃であり、工程時間は5〜30分であることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記メインアニーリング工程の温度は850〜950℃であることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記窒化酸化膜の厚さは70〜100Åであることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記ポストアニーリング工程の温度は950〜1000℃であり、工程時間は5〜30分であることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-0097158 | 2004-11-24 | ||
KR1020040097158A KR100673205B1 (ko) | 2004-11-24 | 2004-11-24 | 플래쉬 메모리소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006148044A true JP2006148044A (ja) | 2006-06-08 |
JP4875856B2 JP4875856B2 (ja) | 2012-02-15 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005150605A Expired - Fee Related JP4875856B2 (ja) | 2004-11-24 | 2005-05-24 | フラッシュメモリ素子の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7268090B2 (ja) |
JP (1) | JP4875856B2 (ja) |
KR (1) | KR100673205B1 (ja) |
DE (1) | DE102005021988A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010517306A (ja) * | 2007-01-26 | 2010-05-20 | フリースケール セミコンダクター インコーポレイテッド | 高電圧トランジスタ、不揮発性メモリトランジスタ、およびロジックトランジスタを備えた半導体デバイスを製造する方法 |
US7821828B2 (en) | 2008-02-11 | 2010-10-26 | Samsung Electronics Co., Ltd. | Memory device and memory device heat treatment method |
US7872295B2 (en) | 2008-06-23 | 2011-01-18 | Samsung Electronics Co., Ltd. | Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100678632B1 (ko) * | 2005-06-23 | 2007-02-05 | 삼성전자주식회사 | 반도체 집적 회로 장치의 제조 방법 |
JP2007180482A (ja) * | 2005-12-28 | 2007-07-12 | Hynix Semiconductor Inc | フラッシュメモリ素子の製造方法 |
US7439134B1 (en) * | 2007-04-20 | 2008-10-21 | Freescale Semiconductor, Inc. | Method for process integration of non-volatile memory cell transistors with transistors of another type |
KR100870297B1 (ko) * | 2007-04-27 | 2008-11-25 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR101283574B1 (ko) | 2007-08-09 | 2013-07-08 | 삼성전자주식회사 | 질소를 함유하는 절연막 형성 방법 및 그것을 포함하는플래시 메모리 소자의 제조 방법 |
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2004
- 2004-11-24 KR KR1020040097158A patent/KR100673205B1/ko active IP Right Grant
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2005
- 2005-05-09 DE DE102005021988A patent/DE102005021988A1/de not_active Withdrawn
- 2005-05-16 US US11/129,939 patent/US7268090B2/en active Active
- 2005-05-24 JP JP2005150605A patent/JP4875856B2/ja not_active Expired - Fee Related
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JP2010517306A (ja) * | 2007-01-26 | 2010-05-20 | フリースケール セミコンダクター インコーポレイテッド | 高電圧トランジスタ、不揮発性メモリトランジスタ、およびロジックトランジスタを備えた半導体デバイスを製造する方法 |
US7821828B2 (en) | 2008-02-11 | 2010-10-26 | Samsung Electronics Co., Ltd. | Memory device and memory device heat treatment method |
US7872295B2 (en) | 2008-06-23 | 2011-01-18 | Samsung Electronics Co., Ltd. | Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same |
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KR100673205B1 (ko) | 2007-01-22 |
US7268090B2 (en) | 2007-09-11 |
DE102005021988A1 (de) | 2006-06-01 |
US20060110942A1 (en) | 2006-05-25 |
KR20060057958A (ko) | 2006-05-29 |
JP4875856B2 (ja) | 2012-02-15 |
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