JP2006134912A - 半導体モジュールおよびその製造方法、ならびにフィルムインターポーザ - Google Patents
半導体モジュールおよびその製造方法、ならびにフィルムインターポーザ Download PDFInfo
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- JP2006134912A JP2006134912A JP2004318891A JP2004318891A JP2006134912A JP 2006134912 A JP2006134912 A JP 2006134912A JP 2004318891 A JP2004318891 A JP 2004318891A JP 2004318891 A JP2004318891 A JP 2004318891A JP 2006134912 A JP2006134912 A JP 2006134912A
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004318891A JP2006134912A (ja) | 2004-11-02 | 2004-11-02 | 半導体モジュールおよびその製造方法、ならびにフィルムインターポーザ |
| US11/262,758 US20060091524A1 (en) | 2004-11-02 | 2005-11-01 | Semiconductor module, process for producing the same, and film interposer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004318891A JP2006134912A (ja) | 2004-11-02 | 2004-11-02 | 半導体モジュールおよびその製造方法、ならびにフィルムインターポーザ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006134912A true JP2006134912A (ja) | 2006-05-25 |
| JP2006134912A5 JP2006134912A5 (enExample) | 2007-06-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| JP2004318891A Withdrawn JP2006134912A (ja) | 2004-11-02 | 2004-11-02 | 半導体モジュールおよびその製造方法、ならびにフィルムインターポーザ |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20060091524A1 (enExample) |
| JP (1) | JP2006134912A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015192555A (ja) * | 2014-03-28 | 2015-11-02 | 株式会社東芝 | 半導体装置 |
| JPWO2013168196A1 (ja) * | 2012-05-10 | 2015-12-24 | ユニテクノ株式会社 | 半導体搬送テスト治具 |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI289947B (en) * | 2006-03-17 | 2007-11-11 | Ind Tech Res Inst | Bendable solid state planar light source, a flexible substrate therefor, and a manufacturing method therewith |
| DE102006032073B4 (de) * | 2006-07-11 | 2016-07-07 | Intel Deutschland Gmbh | Elektrisch leitfähiger Verbund aus einem Bauelement und einer Trägerplatte |
| TWI375999B (en) * | 2007-06-07 | 2012-11-01 | Advanced Semiconductor Eng | Substrate with bumps process and structure |
| US20090159128A1 (en) * | 2007-12-21 | 2009-06-25 | Gill Shook | Leadframe receiver package for solar concentrator |
| US8505805B2 (en) * | 2008-10-09 | 2013-08-13 | Honeywell International Inc. | Systems and methods for platinum ball bonding |
| US20100149773A1 (en) * | 2008-12-17 | 2010-06-17 | Mohd Hanafi Mohd Said | Integrated circuit packages having shared die-to-die contacts and methods to manufacture the same |
| US9570376B2 (en) | 2010-06-29 | 2017-02-14 | General Electric Company | Electrical interconnect for an integrated circuit package and method of making same |
| US8653670B2 (en) | 2010-06-29 | 2014-02-18 | General Electric Company | Electrical interconnect for an integrated circuit package and method of making same |
| DE102011077614B4 (de) * | 2011-06-16 | 2023-08-17 | Osram Gmbh | Verfahren zur Herstellung einer Leuchtvorrichtung und Leuchtvorrichtung |
| JP5985846B2 (ja) * | 2011-06-29 | 2016-09-06 | Flexceed株式会社 | 発光素子搭載用基板及びledパッケージ |
| JP2013033910A (ja) * | 2011-06-29 | 2013-02-14 | Hitachi Cable Ltd | 発光素子搭載用基板、ledパッケージ、及びledパッケージの製造方法 |
| JP2013033909A (ja) * | 2011-06-29 | 2013-02-14 | Hitachi Cable Ltd | 発光素子搭載用基板及びledパッケージ |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745984A (en) * | 1995-07-10 | 1998-05-05 | Martin Marietta Corporation | Method for making an electronic module |
| JPH09162320A (ja) * | 1995-12-08 | 1997-06-20 | Shinko Electric Ind Co Ltd | 半導体パッケージおよび半導体装置 |
| KR100298827B1 (ko) * | 1999-07-09 | 2001-11-01 | 윤종용 | 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법 |
| US6154366A (en) * | 1999-11-23 | 2000-11-28 | Intel Corporation | Structures and processes for fabricating moisture resistant chip-on-flex packages |
| JP3865989B2 (ja) * | 2000-01-13 | 2007-01-10 | 新光電気工業株式会社 | 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置 |
| JP2001320171A (ja) * | 2000-05-08 | 2001-11-16 | Shinko Electric Ind Co Ltd | 多層配線基板及び半導体装置 |
| US6680529B2 (en) * | 2002-02-15 | 2004-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor build-up package |
| JP3542350B2 (ja) * | 2002-05-31 | 2004-07-14 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
-
2004
- 2004-11-02 JP JP2004318891A patent/JP2006134912A/ja not_active Withdrawn
-
2005
- 2005-11-01 US US11/262,758 patent/US20060091524A1/en not_active Abandoned
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2013168196A1 (ja) * | 2012-05-10 | 2015-12-24 | ユニテクノ株式会社 | 半導体搬送テスト治具 |
| US9529039B2 (en) | 2012-05-10 | 2016-12-27 | Unitechno, Inc. | Semiconductor transporting and testing fixture |
| JP2015192555A (ja) * | 2014-03-28 | 2015-11-02 | 株式会社東芝 | 半導体装置 |
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| Publication number | Publication date |
|---|---|
| US20060091524A1 (en) | 2006-05-04 |
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