JP2005524231A - 集積回路デバイス内のルーティングの容量性と誘導性の両方の信号結合効果を除去するための給電および接地シールド・メッシュ - Google Patents
集積回路デバイス内のルーティングの容量性と誘導性の両方の信号結合効果を除去するための給電および接地シールド・メッシュ Download PDFInfo
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- 230000001939 inductive effect Effects 0.000 title claims abstract description 18
- 230000001808 coupling effect Effects 0.000 title abstract description 12
- 230000008878 coupling Effects 0.000 claims abstract description 23
- 238000010168 coupling process Methods 0.000 claims abstract description 23
- 238000005859 coupling reaction Methods 0.000 claims abstract description 23
- 230000000694 effects Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 42
- 238000013459 approach Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
Claims (20)
- a)基板に配置された複数の信号線と、
b)前記基板上に配置され、かつ第1の厚さを有する複数の給電線と前記第1の厚さを有する複数の接地線を含む、前記基板の回路に給電と接地を供給するための給電グリッドと、
c)前記基板上に配置され、かつ第2の厚さを有する複数の給電線と前記第2の厚さを有する複数の接地線を含むシールド・メッシュとを含み、前記複数の信号線のうちのそれぞれの信号線が前記シールド・メッシュのそれぞれの給電線と前記シールド・メッシュのそれぞれの接地線の間に配置され、前記シールド・メッシュが前記複数の信号線のうちの近接信号線間の電子工学的クロストークの影響を削減する集積回路デバイス。 - 前記第2の厚さが前記第1の厚さよりも薄い請求項1に記載の集積回路。
- 前記複数の信号線のうちの前記信号線が前記第2の厚さと同じ厚さである請求項2に記載の集積回路。
- 前記シールド・メッシュの前記給電線と接地線が交互に配置され、前記基板の単一の金属層において互いに平行である請求項1に記載の集積回路。
- 前記シールド・メッシュの前記給電線と接地線が基板のグリッドの線と位置合わせされる請求項3に記載の集積回路。
- 前記シールド・メッシュの前記給電線と接地線が前記基板の第1の金属層内で第1の方向に互いに平行で交互に配置され、前記シールド・メッシュの前記給電線と接地線がやはり前記基板の第2の金属層内で第2の方向に互いに平行で交互に配置され、前記第2の金属層が前記第1の金属層の下にあり、前記第1と第2の方向が90度異なっている請求項1に記載の集積回路。
- 前記電子工学的クロストークが容量結合と誘導結合を含む請求項1に記載の集積回路。
- a)基板内部に配置された複数の信号線と、
b)前記基板上に配置され、かつ第1の厚さを有して第1の電圧レベルを供給するための複数の第1の線と前記第1の厚さを有して第2の電圧レベルを供給するための複数の第2の線を含み、前記基板の回路に電力を供給する給電グリッドと、
c)前記基板上に配置され、かつ第2の厚さを有して前記第1の電圧レベルを供給する複数の第3の線と前記第2の厚さを有して前記第2の電圧レベルを供給する複数の第4の線を含むシールド・メッシュとを含み、前記複数の信号線のうちのそれぞれの信号線が前記シールド・メッシュのそれぞれの第3の線と前記シールド・メッシュのそれぞれの第4の線の間に配置され、前記シールド・メッシュが前記複数の信号線のうちの近接信号線間の電子工学的クロストークの影響を削減する集積回路デバイス。 - 前記第2の厚さが前記第1の厚さよりも小さい請求項8に記載の集積回路。
- 前記複数の信号線のうちの前記信号線が前記第2の厚さと同じ厚さである請求項9に記載の集積回路。
- 前記シールド・メッシュの前記第3と第4の線が交互に配置され、前記基板の単一の金属層の内部で互いに平行である請求項8に記載の集積回路。
- 前記シールド・メッシュの前記第3と第4の線が基板のグリッドの線と位置合わせされる請求項10に記載の集積回路。
- 前記シールド・メッシュの前記第3と第4の線が前記基板の第1の金属層内で第1の方向に互いに平行で交互に配置され、前記シールド・メッシュの前記第3と第4の線がやはり前記基板の第2の金属層内で第2の方向に互いに平行で交互に配置され、前記第2の金属層が前記第1の金属層の下にあり、前記第1と第2の方向が90度異なっている請求項8に記載の集積回路。
- 前記第1の金属層の第3の線と前記第2の金属層の第3の線が第1の接続を使用して一体に結合される請求項13に記載の集積回路。
- 前記第1の金属層の第4の線と前記第2の金属層の第4の線が第2の接続を使用して一体に結合される請求項14に記載の集積回路。
- 前記電子工学的クロストークが容量結合と誘導結合を含む請求項8に記載の集積回路。
- 前記シールド・メッシュが前記基板の利用可能面積の実質的に50%を消費する請求項8に記載の集積回路。
- a)基板内部に配置された複数の信号線と、
b)前記基板上に配置され、かつ第1の厚さを有する複数の給電線と前記第1の厚さを有する複数の接地線を含む、前記基板の回路に給電と接地を供給するための給電グリッドと、
c)前記基板上に配置され、かつ第2の厚さを有する複数の第1の線と前記第2の厚さを有する複数の第2の線を含むシールド・メッシュとを含み、前記複数の信号線のうちのそれぞれの信号線が前記シールド・メッシュのそれぞれの第1の線と前記シールド・メッシュのそれぞれの第2の線の間に配置され、前記シールド・メッシュが前記複数の信号線のうちの近接信号線間の電子工学的クロストークの影響を削減する集積回路デバイス。 - 前記シールド・メッシュの前記第1と第2の線が交互に配置され、前記基板の単一の金属層の内部で互いに平行である請求項18に記載の集積回路。
- 前記シールド・メッシュの前記第1と第2の線が前記基板の第1の金属層内で第1の方向に互いに平行で交互に配置され、前記シールド・メッシュの前記第1と第2の線がやはり前記基板の第2の金属層内で第2の方向に互いに平行で交互に配置され、前記第2の金属層が前記第1の金属層の下にあり、前記第1と第2の方向が90度間隔を置かれている請求項18に記載の集積回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/132,996 US6734472B2 (en) | 2002-04-25 | 2002-04-25 | Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device |
PCT/US2002/024267 WO2003092070A2 (en) | 2002-04-25 | 2002-07-29 | Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device |
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JP2005524231A true JP2005524231A (ja) | 2005-08-11 |
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JP2004500331A Pending JP2005524231A (ja) | 2002-04-25 | 2002-07-29 | 集積回路デバイス内のルーティングの容量性と誘導性の両方の信号結合効果を除去するための給電および接地シールド・メッシュ |
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US (5) | US6734472B2 (ja) |
EP (1) | EP1497864B1 (ja) |
JP (1) | JP2005524231A (ja) |
AU (1) | AU2002326482A1 (ja) |
DE (1) | DE60227290D1 (ja) |
TW (1) | TWI285953B (ja) |
WO (1) | WO2003092070A2 (ja) |
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2002
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- 2002-07-29 JP JP2004500331A patent/JP2005524231A/ja active Pending
- 2002-07-29 AU AU2002326482A patent/AU2002326482A1/en not_active Abandoned
- 2002-07-29 WO PCT/US2002/024267 patent/WO2003092070A2/en active Application Filing
- 2002-07-29 EP EP02761202A patent/EP1497864B1/en not_active Expired - Lifetime
- 2002-07-29 DE DE60227290T patent/DE60227290D1/de not_active Expired - Lifetime
- 2002-08-09 TW TW091118025A patent/TWI285953B/zh not_active IP Right Cessation
-
2004
- 2004-03-26 US US10/810,748 patent/US7217887B2/en not_active Expired - Lifetime
-
2007
- 2007-01-25 US US11/698,330 patent/US7436008B2/en not_active Expired - Lifetime
-
2008
- 2008-10-02 US US12/244,608 patent/US7774186B2/en not_active Expired - Lifetime
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2010
- 2010-08-02 US US12/848,979 patent/US8692297B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009054760A (ja) * | 2007-08-27 | 2009-03-12 | Nec Electronics Corp | 半導体装置、配線設計方法、配線設計装置、及びプログラム |
JP2012142434A (ja) * | 2010-12-28 | 2012-07-26 | Toshiba Corp | 半導体集積回路の配線方法、半導体回路配線装置および半導体集積回路 |
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US6734472B2 (en) | 2004-05-11 |
US7217887B2 (en) | 2007-05-15 |
EP1497864B1 (en) | 2008-06-25 |
US20040178424A1 (en) | 2004-09-16 |
EP1497864A2 (en) | 2005-01-19 |
WO2003092070A3 (en) | 2004-06-17 |
AU2002326482A1 (en) | 2003-11-10 |
US8692297B2 (en) | 2014-04-08 |
US20090032846A1 (en) | 2009-02-05 |
US7436008B2 (en) | 2008-10-14 |
US20070120261A1 (en) | 2007-05-31 |
US20030201472A1 (en) | 2003-10-30 |
DE60227290D1 (de) | 2008-08-07 |
TWI285953B (en) | 2007-08-21 |
US7774186B2 (en) | 2010-08-10 |
US20100301397A1 (en) | 2010-12-02 |
WO2003092070A2 (en) | 2003-11-06 |
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