JP2005347369A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2005347369A
JP2005347369A JP2004162854A JP2004162854A JP2005347369A JP 2005347369 A JP2005347369 A JP 2005347369A JP 2004162854 A JP2004162854 A JP 2004162854A JP 2004162854 A JP2004162854 A JP 2004162854A JP 2005347369 A JP2005347369 A JP 2005347369A
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Prior art keywords
chip
leads
semiconductor device
semiconductor
component
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JP2004162854A
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Japanese (ja)
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JP2005347369A5 (enExample
Inventor
Toshio Sasaki
敏夫 佐々木
Fujio Ito
富士夫 伊藤
Hiromichi Suzuki
博通 鈴木
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2004162854A priority Critical patent/JP2005347369A/ja
Priority to US11/140,394 priority patent/US20050263863A1/en
Publication of JP2005347369A publication Critical patent/JP2005347369A/ja
Publication of JP2005347369A5 publication Critical patent/JP2005347369A5/ja
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
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    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1304—Transistor
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2004162854A 2004-06-01 2004-06-01 半導体装置およびその製造方法 Pending JP2005347369A (ja)

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JP2004162854A JP2005347369A (ja) 2004-06-01 2004-06-01 半導体装置およびその製造方法
US11/140,394 US20050263863A1 (en) 2004-06-01 2005-05-31 Semiconductor device and a method of manufacturing the same

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JP2020113656A (ja) * 2019-01-11 2020-07-27 株式会社デンソー 電子装置およびその製造方法

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US8824165B2 (en) * 2008-02-18 2014-09-02 Cyntec Co. Ltd Electronic package structure
KR100954981B1 (ko) * 2008-03-31 2010-04-29 권구만 다양한 지형선택이 가능한 골프연습기구
US7847391B2 (en) * 2008-07-01 2010-12-07 Texas Instruments Incorporated Manufacturing method for integrating a shunt resistor into a semiconductor package
US8241965B2 (en) * 2009-10-01 2012-08-14 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
JP5341717B2 (ja) 2009-11-10 2013-11-13 ルネサスエレクトロニクス株式会社 半導体パッケージ及びシステム
JP2013110314A (ja) * 2011-11-22 2013-06-06 Elpida Memory Inc 半導体装置
US11342260B2 (en) * 2019-10-15 2022-05-24 Win Semiconductors Corp. Power flat no-lead package
US11380631B2 (en) * 2019-11-27 2022-07-05 Texas Instruments Incorporated Lead frame for multi-chip modules with integrated surge protection
JP7779690B2 (ja) * 2021-09-24 2025-12-03 ローム株式会社 半導体装置、及び半導体モジュール
DE102021125489A1 (de) * 2021-10-01 2023-04-06 Tdk-Micronas Gmbh Integriertes Zwei-Chip Schaltkreissystem in einem integrierten Schaltkreisgehäuse mit zwei separaten Versorgungsgebieten
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JP3137749B2 (ja) * 1992-06-30 2001-02-26 株式会社日立製作所 半導体集積回路装置
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Publication number Priority date Publication date Assignee Title
JP2007173712A (ja) * 2005-12-26 2007-07-05 Hitachi Metals Ltd Ｄｃ−ｄｃコンバータ
JP2020113656A (ja) * 2019-01-11 2020-07-27 株式会社デンソー 電子装置およびその製造方法
JP7172617B2 (ja) 2019-01-11 2022-11-16 株式会社デンソー 電子装置およびその製造方法

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