JP2005216955A - Multilayer ceramic capacitor and its manufacturing method - Google Patents

Multilayer ceramic capacitor and its manufacturing method Download PDF

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JP2005216955A
JP2005216955A JP2004018781A JP2004018781A JP2005216955A JP 2005216955 A JP2005216955 A JP 2005216955A JP 2004018781 A JP2004018781 A JP 2004018781A JP 2004018781 A JP2004018781 A JP 2004018781A JP 2005216955 A JP2005216955 A JP 2005216955A
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JP4501437B2 (en
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Ichiro Nakaso
一朗 中祖
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently manufacture a multilayer ceramic capacitor surely detecting the positional displacement of an internal electrode and having desired characteristics. <P>SOLUTION: The multilayer ceramic capacitor is composed of a first rectangular region 41 and second regions 42 continuously connected on both sides of the first region 41. In the second regions, ceramic green sheets forming a plurality of internal-electrode patterns 40 are laminated, and mother blocks under the state in which the places of the internal-electrode patterns are displaced alternately in the continuous connecting directions of the first region, and the second regions at every ceramic green sheet are formed. The multilayer ceramic capacitor has main internal-electrode patterns 32 for forming an electrostatic capacity containing the first region, one of the second regions and a part of the other of the second regions and dummy-electrode patterns 33 formed of a part of the other second region by cutting the mother blocks. The multilayer ceramic capacitor is constituted by a division into unbaked ceramic laminated elements 1a in which the main internal-electrode patterns and the dummy-electrode patterns are led out alternately to one end faces and the other end faces. Internal-electrode patterns 40 have a shape that widths are changed continuously towards the direction of the increase of distances from the first regions in this case. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本願発明は積層セラミックコンデンサおよびその製造方法に関し、詳しくは、内部電極パターンが形成されたセラミックグリーンシートを積層することにより形成されたマザーブロック（積層体）を切断し、焼成する工程を経て製造される積層セラミックコンデンサおよびその製造方法に関する。   The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same, and more specifically, manufactured through a process of cutting and firing a mother block (laminated body) formed by laminating ceramic green sheets on which internal electrode patterns are formed. The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

積層セラミックコンデンサは、例えば、図１１に示すように、セラミック積層素子５１の内部に、セラミック層５２を介して複数の内部電極５３ａ，５３ｂが互いに対向するように配設され、かつ、その一端側が交互にセラミック積層素子５１の異なる側の端面５５ａ，５５ｂに引き出されているとともに、セラミック積層素子５１の両端側に、内部電極５３ａ，５３ｂと導通するように一対の外部電極５４ａ，５４ｂが配設された構造を有している。   For example, as shown in FIG. 11, the multilayer ceramic capacitor is disposed in a ceramic multilayer element 51 so that a plurality of internal electrodes 53a and 53b face each other with a ceramic layer 52 interposed therebetween, and one end side thereof is A pair of external electrodes 54 a and 54 b are arranged alternately on the end faces 55 a and 55 b on different sides of the ceramic multilayer element 51, and are connected to the internal electrodes 53 a and 53 b on both ends of the ceramic multilayer element 51. Has a structured.

そして、このような積層セラミックコンデンサは、通常、セラミックグリーンシートの表面に、導電成分である金属粉末を分散させた導電ペーストを印刷、塗布することにより内部電極パターンを形成し、このセラミックグリーンシート（電極印刷シート）を積層するとともに、その上下両面側に内部電極パターンを形成していないセラミックグリーンシートを所定枚数積層・圧着することにより得られるマザーブロックを、所定の位置でカットして個々の素子（セラミック積層素子）に分割し、焼成した後、外部電極を形成することにより製造されている。   Such a multilayer ceramic capacitor usually forms an internal electrode pattern by printing and applying a conductive paste in which metal powder as a conductive component is dispersed on the surface of the ceramic green sheet. Electrode printing sheets) are laminated, and a mother block obtained by laminating and pressing a predetermined number of ceramic green sheets without internal electrode patterns on both the upper and lower sides is cut at predetermined positions to obtain individual elements. It is manufactured by forming an external electrode after dividing into (ceramic multilayer element) and firing.

ところで、上述のようにして製造される積層セラミックコンデンサにおいては、電極印刷シートを積層する際に、積層ずれやカットずれに起因する内部電極の位置ずれが生じると、内部電極の有効面積（誘電体層を介して対向する内部電極の重なり面積）が減少して所望の静電容量を取得することができなくなるという問題点がある。   By the way, in the multilayer ceramic capacitor manufactured as described above, when the electrode print sheet is stacked, if the position shift of the internal electrode due to stacking shift or cut shift occurs, the effective area of the internal electrode (dielectric material) There is a problem that a desired capacitance cannot be obtained because the overlapping area of the internal electrodes facing each other through the layer is reduced.

そこで、位置ずれの有無や位置ずれの大きさを確認することができるように、内部電極パターンとダミー電極パターンを配設したセラミックグリーンシートを用い、このセラミックグリーンシートを所定枚数積層・圧着することによりマザーブロックを形成し、得られるマザーブロックを、所定の位置でカットした場合に、切断端面へのダミー電極パターンの露出位置や露出態様により、位置ずれ量を確認することができるようにした積層セラミックコンデンサの製造方法が知られている。   Therefore, a ceramic green sheet with an internal electrode pattern and a dummy electrode pattern is used, and a predetermined number of ceramic green sheets are laminated and pressure-bonded so that the presence or absence of displacement and the magnitude of the displacement can be confirmed. The mother block is formed by the above, and when the obtained mother block is cut at a predetermined position, the amount of displacement can be confirmed by the exposure position and exposure mode of the dummy electrode pattern on the cut end face A method of manufacturing a ceramic capacitor is known.

図１２(ａ)，(ｂ)，(ｃ)は、そのような方法で製造される積層セラミックコンデンサ（の製造方法）の一例を示す図である（特許文献１）。なお、図１２(ａ)，(ｂ)は、セラミック積層素子５１中において、セラミック層を介して対向する一対の内部電極やダミー電極の形状などを示す平面図、図１２(ｃ)は一対の内部電極を互いに対向するように重ね合わせた状態を示す平面図である。   12 (a), 12 (b), and 12 (c) are diagrams showing an example of a multilayer ceramic capacitor (manufacturing method) manufactured by such a method (Patent Document 1). 12A and 12B are plan views showing the shapes of a pair of internal electrodes and dummy electrodes facing each other through the ceramic layer in the ceramic multilayer element 51, and FIG. It is a top view which shows the state which accumulated the internal electrode so that it might mutually oppose.

この積層セラミックコンデンサにおいては、セラミック積層素子５１中に、図１２(ａ)，(ｂ)に示すように、容量形成用の矩形状の内部電極５３ａ、５３ｂと、引き出し方向に向かって幅が変化するような形状を有するダミー電極６４ａ、、６４ｂを配設し、マザーブロックを、所定の位置でカットした場合に、セラミック積層素子５１の端面に露出したダミー電極６４ａ、６４ｂの幅を調べることにより、製造工程において、セラミック積層素子５１を破壊することなく、位置ずれ量を確認することができるようにしている。   In this multilayer ceramic capacitor, as shown in FIGS. 12A and 12B, the ceramic multilayer element 51 has a rectangular inner electrode 53a, 53b for capacity formation, and the width changes in the lead-out direction. The dummy electrodes 64a, 64b having such a shape are disposed, and when the mother block is cut at a predetermined position, the width of the dummy electrodes 64a, 64b exposed on the end face of the ceramic multilayer element 51 is examined. In the manufacturing process, the positional deviation amount can be confirmed without destroying the ceramic multilayer element 51.

しかしながら、この方法では、意図した態様でセラミックグリーンシートが積層されているときにはカットずれを検出することができるが、セラミックグリーンシートの積層ずれと、カットずれとが重なると、セラミック積層素子５１の端面に露出したダミー電極６４ａ、６４ｂの幅が、積層ずれおよびカットずれのない良品と同じになってしまう場合があり、不良を検出することができない場合が生じ、所望の静電容量を取得できない製品も良品と判定されてしまうという問題点がある。   However, in this method, the cut deviation can be detected when the ceramic green sheets are laminated in an intended manner. However, when the lamination deviation of the ceramic green sheets and the cut deviation overlap, the end face of the ceramic multilayer element 51 is detected. The width of the dummy electrodes 64a and 64b exposed to the same may be the same as a good product without stacking deviation and cut deviation, and it may not be possible to detect a defect, so that a desired capacitance cannot be obtained. However, there is a problem that it is judged as a non-defective product.

また、図１３に示すように、セラミック素体６１上に、スクリーン印刷によって内部電極となる電極パターン６２を形成すると同時に、積層ずれの検査を行なうためのチェックマーク６３を形成することにより、切断線Ｌで切断する工程を経て製造される積層セラミックコンデンサをその一方から検査することにより、長さ方向および／または幅方向の積層ずれの量を確認することができるようにした方法がある（特許文献２）。   Further, as shown in FIG. 13, by forming an electrode pattern 62 to be an internal electrode by screen printing on the ceramic body 61, and simultaneously forming a check mark 63 for inspecting a stacking deviation, a cutting line is formed. There is a method in which the amount of stacking deviation in the length direction and / or the width direction can be confirmed by inspecting a multilayer ceramic capacitor manufactured through a process of cutting at L from one side (Patent Document) 2).

しかし、この方法の場合、チェックマーク６３を形成するための領域が必要となるため、静電容量形成用の内部電極パターンの面積が、特にその幅方向に狭くなり、小型化が妨げられるという問題点がある。
また、チェックマーク６３を形成するために、電極材料が余分に必要になるためコストの増大を招くという問題点がある。
特開２０００−１０６３２１号公報 特開平６−２２４００２号公報 However, in this method, since a region for forming the check mark 63 is necessary, the area of the internal electrode pattern for forming the capacitance is narrowed particularly in the width direction, and miniaturization is prevented. There is a point.
Further, since extra electrode material is required to form the check mark 63, there is a problem that the cost is increased.
JP 2000-106321 A JP-A-6-224002

本願発明は、上記問題点を解決するものであり、原因のいかんにかかわらず（すなわち、積層ずれとカットずれのいずれか一方が生じた場合や、積層ずれとカットずれの両方が生じた場合にも）、内部電極の位置ずれを確実に検出することが可能で、所望の特性を備えた積層セラミックコンデンサを効率よく、しかも経済的に製造することが可能な積層セラミックコンデンサの製造方法およびかかる製造方法により製造される信頼性の高い積層セラミックコンデンサを提供することを課題とする。   The present invention solves the above-mentioned problems, regardless of the cause (i.e., when either a stacking shift or a cut shift occurs, or when both a stacking shift and a cut shift occur). In addition, it is possible to reliably detect misalignment of the internal electrodes, and it is possible to efficiently and economically manufacture a multilayer ceramic capacitor having desired characteristics, and a method for manufacturing such a multilayer ceramic capacitor. It is an object of the present invention to provide a highly reliable multilayer ceramic capacitor manufactured by the method.

上記課題を解決するため、本願発明（請求項１）の積層セラミックコンデンサは、
セラミック積層素子の内部に、静電容量形成用の複数の主内部電極および静電容量の形成に寄与しないダミー電極がセラミック層を介して配設され、かつ、主内部電極およびダミー電極は、セラミック積層素子の一方端面および他方端面のうちの互いに逆側の端面に引き出されているとともに、一層ごとに逆側の端面に引き出され、セラミック積層素子の両端側には、少なくとも主内部電極と導通するように一対の外部電極が配設された構造を有する積層セラミックコンデンサであって、
主内部電極は、矩形形状の第１部分と、第１部分の両側に連設された第２部分から構成され、主内部電極の第２部分は、引き出し端面に向かって連続的に幅が変化する形状を有しており、
ダミー電極は、主内部電極と同一平面に並置され、かつ、引き出し端面に向かって連続的に幅が変化する形状を有していること
を特徴としている。 In order to solve the above problems, the multilayer ceramic capacitor of the present invention (Claim 1) is:
A plurality of main internal electrodes for forming a capacitance and a dummy electrode that does not contribute to the formation of the capacitance are disposed inside the ceramic multilayer element via a ceramic layer, and the main internal electrode and the dummy electrode are made of ceramic. The multilayer element is drawn to the opposite end face of the one end face and the other end face, and is drawn to the opposite end face for each layer, and at least both ends of the ceramic multilayer element are electrically connected to the main internal electrode. A multilayer ceramic capacitor having a structure in which a pair of external electrodes are arranged as follows:
The main internal electrode is composed of a rectangular first portion and second portions connected to both sides of the first portion, and the width of the second portion of the main internal electrode continuously changes toward the lead end surface. Has a shape to
The dummy electrodes are characterized by being juxtaposed in the same plane as the main internal electrode and having a shape whose width continuously changes toward the leading end face.

また、請求項２の積層セラミックコンデンサは、主内部電極の第２部分、およびダミー電極の引き出し端面に向かって連続的に幅が変化する部分が、直線形状または曲線形状を有していることを特徴としている。   The multilayer ceramic capacitor according to claim 2 is characterized in that the second portion of the main internal electrode and the portion whose width continuously changes toward the leading end surface of the dummy electrode have a linear shape or a curved shape. It is a feature.

また、本願発明（請求項３）の積層セラミックコンデンサの製造方法は、
セラミック積層素子の内部に、静電容量形成用の複数の主内部電極および静電容量の形成に寄与しないダミー電極がセラミック層を介して配設され、かつ、主内部電極およびダミー電極は、セラミック積層素子の一方端面および他方端面のうちの互いに逆側の端面に引き出されているとともに、一層ごとに逆側の端面に引き出され、セラミック積層素子の両端側には、少なくとも主内部電極と導通するように一対の外部電極が配設された構造を有する積層セラミックコンデンサの製造方法であって、
(ａ)セラミックグリーンシート上に、矩形形状の第１領域と、第１領域の両側に連設された第２領域から構成され、第２領域は、第１領域からの距離が大きくなる方向に向かって連続的に幅が変化する形状を有する複数の内部電極パターンをマトリックス状に形成する工程と、
(ｂ)内部電極パターンが形成されたセラミックグリーンシートを積層することにより、内部電極パターンの位置が、各セラミックグリーンシートごとに交互に、第１領域と第２領域の連設方向にずれた状態のマザーブロックを形成する工程と、
(ｃ)マザーブロックを、内部電極パターンが一方の第２領域で分割される位置で切断して、第１領域と、２つの第２領域のうちの一方の第２領域と、他方の第２領域の一部とを含む静電容量形成用の主内部電極パターンと、他方の第２領域の一部から形成される静電容量の形成に寄与しないダミー電極パターンがセラミックグリーンシート層を介して配設され、かつ、主内部電極パターンと、ダミー電極パターンがセラミック積層素子の一方端面および他方端面のうちの互いに逆側の端面に引き出されているとともに、一層ごとに逆側の端面に引き出された個々の未焼成のセラミック積層素子に分割する工程と、
(ｄ)セラミック積層素子を焼成する工程と、
(ｅ)セラミック積層素子に、少なくとも主内部電極と導通するように一対の外部電極を形成する工程と
を具備することを特徴としている。 In addition, the manufacturing method of the multilayer ceramic capacitor of the present invention (Claim 3)
A plurality of main internal electrodes for forming a capacitance and a dummy electrode that does not contribute to the formation of the capacitance are disposed inside the ceramic multilayer element via a ceramic layer, and the main internal electrode and the dummy electrode are made of ceramic. The multilayer element is drawn to the opposite end face of the one end face and the other end face, and is drawn to the opposite end face for each layer, and at least both ends of the ceramic multilayer element are electrically connected to the main internal electrode. A method for manufacturing a multilayer ceramic capacitor having a structure in which a pair of external electrodes is disposed as follows:
(a) On a ceramic green sheet, it is composed of a rectangular first region and second regions connected to both sides of the first region, and the second region is in a direction in which the distance from the first region increases. Forming a plurality of internal electrode patterns having a shape whose width continuously changes toward the matrix,
(b) A state in which the positions of the internal electrode patterns are alternately shifted in the connecting direction of the first region and the second region by stacking the ceramic green sheets on which the internal electrode patterns are formed. Forming a mother block of
(c) The mother block is cut at a position where the internal electrode pattern is divided by one second region, and the first region, one second region of the two second regions, and the other second region. A main internal electrode pattern for forming a capacitance including a part of the region and a dummy electrode pattern that does not contribute to the formation of a capacitance formed from a part of the other second region through the ceramic green sheet layer The main internal electrode pattern and the dummy electrode pattern are drawn to the opposite end faces of the one end face and the other end face of the ceramic multilayer element, and are drawn to the opposite end face for each layer. Dividing into individual unfired ceramic laminate elements;
(d) firing the ceramic multilayer element;
(e) forming a pair of external electrodes so as to be electrically connected to at least the main internal electrode in the ceramic multilayer element.

また、請求項４の積層セラミックコンデンサの製造方法は、内部電極パターンの矩形形状の第１領域と、その両側に連設された第２領域から構成される内部電極パターンの形状が、第１領域を挟んで対称の形状を有していることを特徴としている。   According to a fourth aspect of the present invention, there is provided a method for manufacturing a multilayer ceramic capacitor, wherein the shape of the internal electrode pattern composed of a rectangular first region of the internal electrode pattern and second regions connected to both sides thereof is the first region. It is characterized by having a symmetric shape across the surface.

また、請求項５の積層セラミックコンデンサの製造方法は、内部電極パターンの第２領域の、第１領域からの距離が大きくなる方向に向かって連続的に幅が変化する部分が、直線形状または曲線形状を有していることを特徴としている。   According to a fifth aspect of the present invention, there is provided a method for manufacturing a multilayer ceramic capacitor, wherein a portion of the second region of the internal electrode pattern whose width continuously changes in a direction in which the distance from the first region increases is linear or curved. It is characterized by having a shape.

本願発明（請求項１）の積層セラミックコンデンサは、主内部電極を、矩形形状の第１部分と、第１部分の両側に連設された第２部分から構成するとともに、主内部電極の第２部分は、引き出し端面（一方端面および他方端面）に向かって連続的に幅が変化する形状とし、ダミー電極を、主内部電極と同一平面に並置し、かつ、引き出し端面に向かって連続的に幅が変化する形状としているので、セラミック積層素子の引き出し端面に露出した主内部電極の（第２部分の）幅と、ダミー電極の幅の両方を確認することにより、原因のいかんにかかわらず（すなわち、積層ずれおよびカットずれのいずれか一方が発生した場合、あるいは両方が同時に発生した場合を問わずに）、主内部電極の位置ずれの有無を検出することが可能になる。   In the multilayer ceramic capacitor of the present invention (claim 1), the main internal electrode is composed of a rectangular first portion and second portions connected to both sides of the first portion, and the second main internal electrode. The portion has a shape in which the width continuously changes toward the leading end face (one end face and the other end face), the dummy electrode is juxtaposed in the same plane as the main internal electrode, and continuously wide toward the leading end face Therefore, by checking both the width of the main internal electrode (second portion) exposed on the lead end face of the ceramic multilayer element and the width of the dummy electrode, regardless of the cause (i.e., It is possible to detect whether or not the main internal electrode is misaligned, regardless of whether any one of stacking misalignment and cut misalignment occurs, or both occur simultaneously.

すなわち、本願発明においては、ダミー電極だけではなく、主内部電極にも、主内部電極の位置を検出する機能と、位置ずれの量を検出する機能を持たせるようにしているので、セラミック積層素子の引き出し端面（一方端面および他方端面）に露出した主内部電極の第２部分の幅と、ダミー電極の幅の両方を確認することにより、積層ずれと、カットずれの両方が発生し、例えば、セラミック積層素子の引き出し端面に露出したダミー電極の長さが良品（正常品）と同じになるようにカットされた場合においても、引き出し端面に露出した主内部電極の長さを良品とは異ならせることが可能になり（同様に、主内部電極の長さが良品と同じになるようにカットされた場合にも、ダミー電極の長さを良品とは異ならせることが可能になる）、確実に主内部電極の位置ずれを検出することが可能になる。
なお、本願発明において、主内部電極の第２部分の、引き出し端面に向かって連続的に幅が変化する形状は、引き出し端面に向かって幅が小さくなるものであってもよく、また、幅が大きくなるものであってもよい。 That is, in the present invention, not only the dummy electrode but also the main internal electrode is provided with a function of detecting the position of the main internal electrode and a function of detecting the amount of displacement. By confirming both the width of the second portion of the main internal electrode exposed on the leading end face (one end face and the other end face) and the width of the dummy electrode, both stacking deviation and cut deviation occur. Even when the length of the dummy electrode exposed on the lead end face of the ceramic multilayer element is cut to be the same as a non-defective product (normal product), the length of the main internal electrode exposed on the lead end surface is different from the non-defective product. (Similarly, even when the main internal electrode is cut to have the same length as the non-defective product, the length of the dummy electrode can be different from the non-defective product) It is possible to detect the positional deviation of the downright main internal electrodes.
In the present invention, the shape of the second portion of the main internal electrode, the width of which continuously changes toward the leading end surface, may be such that the width decreases toward the leading end surface. It may be larger.

また、請求項２の積層セラミックコンデンサのように、主内部電極の第２部分、およびダミー電極の、引き出し端面に向かって連続的に幅が変化する部分を、直線形状または曲線形状とすることにより、位置ずれ量に応じて、セラミック積層素子の引き出し端面に露出する主内部電極およびダミー電極の長さを確実に、かつ、連続的に変化させることが可能になり、引き出し端面への主内部電極の第２部分、およびダミー電極の露出部分の長さから、積層ずれおよびカットずれのいずれか一方が発生した場合、あるいは両方が同時に発生した場合を問わずに、より確実に主内部電極の位置ずれの有無を検出することが可能になる。   Further, as in the multilayer ceramic capacitor according to claim 2, by forming the second portion of the main internal electrode and the portion of the dummy electrode, the width of which continuously changes toward the lead end surface, into a linear shape or a curved shape. The length of the main internal electrode and the dummy electrode exposed on the lead end face of the ceramic multilayer element can be changed surely and continuously according to the amount of displacement, and the main internal electrode to the lead end face can be changed. The position of the main internal electrode is more reliably determined from the length of the second portion of the first electrode and the exposed portion of the dummy electrode, regardless of whether one of the stacking deviation and the cutting deviation occurs or both occur simultaneously. It becomes possible to detect the presence or absence of deviation.

また、本願発明（請求項３）の積層セラミックコンデンサの製造方法は、セラミックグリーンシート上に、矩形形状の第１領域と、その両側に連設された第２領域から構成され、第２領域は、第１領域からの距離が大きくなる方向に向かって連続的に幅が変化する形状を有する複数の内部電極パターンをマトリックス状に形成し、このセラミックグリーンシートを積層して、内部電極パターンの位置が、各セラミックグリーンシートごとに交互に、第１領域と第２領域の連設方向にずれた状態のマザーブロックを形成し、このマザーブロックを、内部電極パターンが一方の第２領域で分割される位置で切断して、第１領域と、第２領域の一方と、第２領域の他方の一部を含む静電容量形成用の主内部電極パターンと、他方の第２領域の一部から形成される静電容量の形成に寄与しないダミー電極パターンがセラミックグリーンシート層を介して配設され、かつ、主内部電極パターンおよびダミー電極パターンが、セラミック積層素子の一方端面および他方端面のうちの互いに逆側の端面に引き出されているとともに、一層ごとに逆側の端面に引き出された個々の未焼成のセラミック積層素子に分割し、得られるセラミック積層素子を焼成した後、セラミック積層素子に、主内部電極と導通するように一対の外部電極を形成するようにしているので、セラミック積層素子の引き出し端面に露出した主内部電極パターン（主内部電極）の第２領域の幅と、ダミー電極パターン（ダミー電極）の幅の両方を確認することにより、積層ずれおよびカットずれのいずれか一方が発生した場合、あるいは両方が同時に発生した場合を問わずに、主内部電極パターン（主内部電極）の位置ずれの有無を確実に検出することが可能になる。   Moreover, the method for manufacturing a multilayer ceramic capacitor according to the present invention (Claim 3) includes a rectangular first region and second regions continuously provided on both sides of the ceramic green sheet. A plurality of internal electrode patterns having a shape whose width continuously changes in a direction in which the distance from the first region increases is formed in a matrix shape, and the ceramic green sheets are stacked to position the internal electrode patterns However, alternately, each ceramic green sheet forms a mother block that is shifted in the connecting direction of the first region and the second region, and the inner electrode pattern is divided into one second region. The first internal region, one of the second regions, the main internal electrode pattern for forming the capacitance including the other part of the second region, and a part of the other second region. A dummy electrode pattern that does not contribute to the formation of the formed capacitance is disposed via the ceramic green sheet layer, and the main internal electrode pattern and the dummy electrode pattern are formed on one end surface and the other end surface of the ceramic multilayer element. After being drawn to the opposite end faces and divided into individual unfired ceramic laminate elements drawn to the opposite end face for each layer, after firing the resulting ceramic laminate element, to the ceramic laminate element, Since the pair of external electrodes are formed so as to be electrically connected to the main internal electrode, the width of the second region of the main internal electrode pattern (main internal electrode) exposed on the lead end face of the ceramic multilayer element, and the dummy electrode pattern (Dummy electrode) By confirming both widths, if either stacking misalignment or cut misalignment occurs, Rui regardless of the case where both occur at the same time, it is possible to reliably detect the presence or absence of positional deviation in the main internal electrode patterns (main internal electrodes).

すなわち、本願発明（請求項３）の積層セラミックコンデンサの製造方法によれば、内部電極の位置ずれが生じた不良品を確実に除去して、信頼性の高い積層セラミックコンデンサ、すなわち、本願請求項１記載の積層セラミックコンデンサを確実に製造することが可能になる。
なお、本願発明において、主内部電極パターンの第２領域の、引き出し端面に向かって連続的に幅が変化する形状は、引き出し端面に向かって幅が小さくなるものであってもよく、また、幅が大きくなるものであってもよい。 That is, according to the method for manufacturing a multilayer ceramic capacitor of the present invention (Claim 3), a defective product in which the displacement of the internal electrodes is reliably removed is reliably removed, that is, the highly reliable multilayer ceramic capacitor, that is, the present claim. It becomes possible to reliably manufacture the monolithic ceramic capacitor described in 1.
In the present invention, the shape of the second region of the main internal electrode pattern, the width of which continuously changes toward the leading end face, may be such that the width decreases toward the leading end face. May be larger.

また、請求項４の積層セラミックコンデンサの製造方法のように、内部電極パターンの矩形形状の第１領域と、その両側に連設された第２領域から構成される内部電極パターンの形状を、第１領域を挟んで対称の形状とすることにより、かかる内部電極パターンの形成されたセラミックグリーンシートを所定の態様で積層し、所定の位置で切断して、個々の素子に分割することにより、主内部電極パターンが、矩形形状の第１領域と、その両側に連設された第２領域から構成され、かつ、主内部電極パターンの第２領域が、引き出し端面に向かって連続的に幅が変化する形状を有し、かつ、ダミー電極パターンが、主内部電極パターンと同一平面に並置され、かつ、引き出し端面に向かって連続的に幅が変化する形状を有するセラミック積層素子を効率よく形成することが可能になり、セラミック積層素子の引き出し端面に露出した主内部電極パターンの第２領域の幅と、ダミー電極パターンの幅の両方を確認することにより、積層ずれおよびカットずれのいずれか一方が発生した場合、あるいは両方が同時に発生した場合を問わずに、より確実に主内部電極パターンの位置ずれの有無を検出することが可能になり、本願発明をより実効あらしめることが可能になる。   Further, as in the method of manufacturing a multilayer ceramic capacitor according to claim 4, the shape of the internal electrode pattern constituted by the rectangular first region of the internal electrode pattern and the second region continuously provided on both sides thereof is By forming a symmetrical shape across one region, the ceramic green sheets on which such internal electrode patterns are formed are laminated in a predetermined manner, cut at a predetermined position, and divided into individual elements. The internal electrode pattern is composed of a rectangular first region and second regions continuously provided on both sides thereof, and the width of the second region of the main internal electrode pattern changes continuously toward the leading end surface. Ceramic laminate having a shape in which the dummy electrode pattern is juxtaposed in the same plane as the main internal electrode pattern and the width continuously changes toward the leading end surface It is possible to efficiently form a child, and by confirming both the width of the second region of the main internal electrode pattern exposed on the lead end face of the ceramic multilayer element and the width of the dummy electrode pattern, stacking deviation and cut Regardless of whether one of the deviations occurs or both occur at the same time, it becomes possible to more reliably detect the presence or absence of the positional deviation of the main internal electrode pattern, making the present invention more effective. It becomes possible.

また、請求項５の積層セラミックコンデンサの製造方法のように、内部電極パターンの第２領域の、第１領域からの距離が大きくなる方向に向かって連続的に幅が変化する部分を、直線形状または曲線形状とすることにより、位置ずれ量に応じて、セラミック積層素子の引き出し端面に露出する主内部電極パターンの第２領域およびダミー電極パターンの長さを確実に、かつ、連続的に変化させることが可能になり、引き出し端面への主内部電極パターンの第２領域、およびダミー電極パターンの露出部分の長さから、積層ずれおよびカットずれのいずれか一方が発生した場合、あるいは両方が同時に発生した場合を問わずに、さらに確実に主内部電極パターンの位置ずれの有無を検出することが可能になる。   In addition, as in the method of manufacturing a multilayer ceramic capacitor according to claim 5, a portion of the second region of the internal electrode pattern whose width continuously changes in a direction in which the distance from the first region increases becomes a linear shape. Alternatively, by adopting a curved shape, the length of the second region of the main internal electrode pattern and the dummy electrode pattern exposed on the lead end face of the ceramic multilayer element can be changed reliably and continuously in accordance with the amount of displacement. If either one of stacking misalignment or cut misalignment occurs, or both occur simultaneously, based on the length of the second region of the main internal electrode pattern on the lead end face and the exposed portion of the dummy electrode pattern Regardless of the case, it is possible to more reliably detect the presence or absence of the positional deviation of the main internal electrode pattern.

以下に本願発明の実施例を示して、本願発明の特徴とするところをさらに詳しく説明する。   The features of the present invention will be described in more detail below with reference to examples of the present invention.

図１は、本願発明の一実施例にかかる積層セラミックコンデンサの構造を示す図であり、(ａ)は正面断面図、(ｂ)は外部電極を形成する前のセラミック積層素子の左側面（左端面）を示す図、(ｃ)は外部電極を形成する前のセラミック積層素子の右側面（右端面）を示す図である。
また、図２(ａ)は、図１の積層セラミックコンデンサを構成する一対の内部電極およびダミー電極のうちの、一方の内部電極およびダミー電極の形状を示す図、図２(ｂ)は、他方の内部電極およびダミー電極の形状を示す図、図２(ｃ)は、図２(ａ)と図２(ｂ)の内部電極およびダミー電極の積層の態様を示す透視平面図である。 1A and 1B are diagrams showing the structure of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 1A is a front sectional view, and FIG. 1B is a left side (left end) of a ceramic multilayer element before forming external electrodes. (C) is a figure which shows the right side surface (right end surface) of the ceramic laminated element before forming an external electrode.
2A is a view showing the shape of one internal electrode and dummy electrode of the pair of internal electrodes and dummy electrodes constituting the multilayer ceramic capacitor of FIG. 1, and FIG. FIG. 2 (c) is a perspective plan view showing a stacked state of the internal electrodes and dummy electrodes of FIGS. 2 (a) and 2 (b).

この積層セラミックコンデンサは、図１(ａ)，(ｂ)，(ｃ)に示すように、セラミック積層素子１の内部に、静電容量形成用の複数の主内部電極２ａ，２ｂおよび静電容量の形成に寄与しないダミー電極３ａ，３ｂがセラミック層４を介して配設され、かつ、主内部電極２ａ，２ｂおよびダミー電極３ａ，３ｂはいずれも、その一端側が交互にセラミック積層素子１の一方端面（引き出し端面）５ａおよび他方端面（引き出し端面）５ｂに引き出されて（図２(ｃ)参照）いるとともに、セラミック積層素子１の両端側に、少なくとも主内部電極２ａ，２ｂと導通するように一対の外部電極６ａ，６ｂが配設された構造を有している。   As shown in FIGS. 1A, 1B, and 1C, this multilayer ceramic capacitor has a plurality of main internal electrodes 2a, 2b for forming capacitance and electrostatic capacitance inside the ceramic multilayer element 1. Dummy electrodes 3a and 3b that do not contribute to the formation of the ceramic multilayer element 1 are disposed via the ceramic layer 4, and the main internal electrodes 2a and 2b and the dummy electrodes 3a and 3b are alternately arranged at one end side of the ceramic multilayer element 1. It is drawn out to the end face (drawing end face) 5a and the other end face (drawing end face) 5b (see FIG. 2 (c)), and is connected to at least the main internal electrodes 2a and 2b at both ends of the ceramic multilayer element 1. A pair of external electrodes 6a, 6b is provided.

主内部電極２ａ，２ｂは、図２(ａ)，(ｂ)に示すように、矩形形状の第１部分１１と、その両側に連設された第２部分１２ａ，１２ｂから構成されている。そして、主内部電極２ａ，２ｂの第２部分１２ａ，１２ｂは、引き出し端面５ａ，５ｂに向かって連続的に幅が変化する（小さくなる）ような形状、例えば、辺２２が直線である台形形状を有している。   As shown in FIGS. 2 (a) and 2 (b), the main internal electrodes 2a and 2b are composed of a rectangular first portion 11 and second portions 12a and 12b connected to both sides thereof. The second portions 12a and 12b of the main internal electrodes 2a and 2b have a shape whose width continuously changes (becomes smaller) toward the lead-out end surfaces 5a and 5b, for example, a trapezoidal shape whose side 22 is a straight line. have.

また、ダミー電極３ａ，３ｂは、図２(ａ)，(ｂ)に示すように、主内部電極２ａ，２ｂと同一平面に並置され、かつ、引き出し端面５ａ，５ｂに向かって連続的に幅が変化する（幅が大きくなる）ような形状、例えば、辺２３が直線である台形形状を有している。   Further, as shown in FIGS. 2A and 2B, the dummy electrodes 3a and 3b are juxtaposed in the same plane as the main internal electrodes 2a and 2b, and have continuous widths toward the leading end surfaces 5a and 5b. Has a shape that changes (the width increases), for example, a trapezoidal shape in which the side 23 is a straight line.

上述のように、この積層セラミックコンデンサにおいては、主内部電極２ａ，２ｂを、矩形形状の第１部分１１と、その両側に連設された第２部分１２ａ，１２ｂから構成するとともに、主内部電極２ａ，２ｂの第２部分１２ａ，１２ｂは、引き出し端面５ａ，５ｂに向かって連続的に幅が変化する（小さくなる）ような形状とし、ダミー電極３ａ，３ｂを、主内部電極２ａ，２ｂと同一平面に並置し、かつ、引き出し端面５ａ，５ｂに向かって連続的に幅が変化する（大きくなる）ような形状としているので、セラミック積層素子１の引き出し端面５ａおよび５ｂに露出した主内部電極２ａ，２ｂ（詳しくは第２部分１２ａ，１２ｂ）の幅と、ダミー電極３ａ，３ｂの幅の両方を確認することにより、原因のいかんにかかわらず（すなわち、積層ずれおよびカットずれのいずれか一方が発生した場合、あるいは両方が同時に発生した場合を問わずに）、主内部電極２ａ，２ｂの位置ずれの有無を検出することが可能になり、不良品の混入を防止して、信頼性の高い積層セラミックコンデンサを効率よく製造することが可能になる。   As described above, in this multilayer ceramic capacitor, the main internal electrodes 2a and 2b are composed of the first portion 11 having a rectangular shape and the second portions 12a and 12b connected to both sides thereof, and the main internal electrodes The second portions 12a and 12b of 2a and 2b are shaped so that the width continuously changes (becomes smaller) toward the leading end surfaces 5a and 5b, and the dummy electrodes 3a and 3b are connected to the main internal electrodes 2a and 2b. The main internal electrodes exposed on the lead-out end faces 5a and 5b of the ceramic multilayer element 1 because they are juxtaposed on the same plane and have a shape whose width continuously changes (increases) toward the lead-out end faces 5a and 5b. By confirming both the widths of 2a and 2b (specifically, the second portions 12a and 12b) and the widths of the dummy electrodes 3a and 3b, regardless of the cause (that is, It is possible to detect whether or not the main internal electrodes 2a and 2b are misaligned, regardless of whether any one of stacking misalignment and cut misalignment occurs, or both occur simultaneously. Mixing is prevented, and a highly reliable multilayer ceramic capacitor can be efficiently manufactured.

なお、上記積層セラミックコンデンサにおいては、主内部電極２ａ，２ｂの第２部分１２ａ，１２ｂの辺２２、および、ダミー電極３ａ，３ｂの辺２３が直線である場合を例にとって説明したが、辺２２および２３は、図８，図１０に示すように曲線とすることも可能である。   In the multilayer ceramic capacitor, the case where the side 22 of the second portions 12a and 12b of the main internal electrodes 2a and 2b and the side 23 of the dummy electrodes 3a and 3b are straight lines has been described as an example. And 23 can be curved as shown in FIGS.

次に、本願発明の積層セラミックコンデンサの製造方法について説明するとともに、製造工程における主内部電極（パターン）の位置ずれの検出方法について説明する。   Next, a method for manufacturing the multilayer ceramic capacitor of the present invention will be described, and a method for detecting the displacement of the main internal electrode (pattern) in the manufacturing process will be described.

(１)まず、セラミックグリーンシート上に、矩形形状の第１領域４１と、その両側に連設された第２領域４２から構成され、第２領域４２は、第１領域４１からの距離が大きくなる方向に向かって連続的に幅が変化する形状を有する複数の内部電極パターン４０をマトリックス状に形成し、所定のパターンとなるように打ち抜くことにより、図３(ａ)に示すようなパターンＡの電極印刷シート３１ａと、図３(ｂ)に示すようなパターンＢの電極印刷シート３１ｂを形成する。なお、内部電極パターン４０を構成する第１領域４１の両側の第２領域４２，４２（右側の第２領域と左側の第２領域）とは対称形状となるように構成されている。
なお、同じパターンとなるように打ち抜かれた電極印刷シートを位置をずらして積層した後、所定の位置でマザーブロックをカットするように構成することも可能である。 (1) First, a rectangular first region 41 and second regions 42 connected to both sides thereof are formed on a ceramic green sheet, and the second region 42 has a large distance from the first region 41. A plurality of internal electrode patterns 40 having a shape whose width continuously changes in a certain direction are formed in a matrix shape and punched out into a predetermined pattern, whereby a pattern A as shown in FIG. The electrode print sheet 31a and the electrode print sheet 31b having the pattern B as shown in FIG. 3B are formed. Note that the second regions 42 and 42 (the second region on the right side and the second region on the left side) on both sides of the first region 41 constituting the internal electrode pattern 40 are configured to be symmetrical.
It is also possible to configure such that the mother block is cut at a predetermined position after the electrode print sheets punched out so as to have the same pattern are stacked while being shifted in position.

(２)それから、この電極印刷シート３１ａ，３１ｂを図３(ｃ)に示すような態様で積層し、これを繰り返して所定枚数の電極印刷シート３１ａ，３１ｂを交互に積層し、圧着することにより、内部電極パターン４０の位置が、各セラミックグリーンシートごとに交互に、第１領域４１と第２領域４２の連設方向（図３(ａ)の矢印Ｘの方向）にずれた状態のマザーブロックを形成する。   (2) Then, the electrode printing sheets 31a and 31b are stacked in the manner as shown in FIG. 3C, and this is repeated to alternately stack a predetermined number of electrode printing sheets 31a and 31b and press-bond them. The mother block in a state in which the position of the internal electrode pattern 40 is alternately shifted in the connecting direction of the first region 41 and the second region 42 (the direction of the arrow X in FIG. 3A) alternately for each ceramic green sheet. Form.

(３)そして、得られたマザーブロックを所定の位置で切断することにより、図３(ｄ)に左側面図、図３(ｅ)に右側面図、図３(ｆ)に正面断面図をそれぞれ模式的に示すような個々の素子（未焼成のセラミック積層素子）１ａに分割する。
これによって、個々のセラミック積層素子１ａの右端面には、Ａパターンの電極印刷シートの、内部電極パターン４０の引き出し部となる第２領域４２と、Ｂパターンの電極印刷シートの、内部電極パターン４０から切り離されたダミー電極パターン３３（３３ｂ）が露出する。
同様に、個々のセラミック素子１ａの左端面には、Ａパターンの電極印刷シートの、内部電極パターン４０から切り離されたダミー電極パターン３３（３３ａ）と、Ｂパターンの電極印刷シートの、内部電極パターン４０の引き出し部となる第２領域４２が露出する。
すなわち、マザーブロックを、内部電極パターン４０が一方の第２領域４２で分割される位置で切断して、図３(ｃ)，図３(ｆ)などに示すように、一方の第２領域４２の一部と、第１領域４１と、他方の第２領域４２を含む静電容量形成用の主内部電極パターン３２および他方の第２領域４２の一部から形成される静電容量の形成に寄与しないダミー電極パターン３３がセラミックグリーンシート層３４を介して配設され、かつ、主内部電極パターン３２およびダミー電極パターン３３がいずれも、その一端側が交互に一方端面および他方端面に引き出された個々の未焼成のセラミック積層素子１ａに分割する。
なお、図３(ｄ)，(ｅ)，(ｆ)は、内部電極の積層数が３層である場合を示しているが、実際には、通常、数十層〜数百層の内部電極層と誘電体層が積層されることになる。 (3) By cutting the mother block obtained at a predetermined position, a left side view is shown in FIG. 3 (d), a right side view is shown in FIG. 3 (e), and a front sectional view is shown in FIG. 3 (f). Each element is divided into individual elements (unfired ceramic laminated elements) 1a as schematically shown.
As a result, on the right end surface of each ceramic multilayer element 1a, the second region 42 serving as a lead-out portion of the internal electrode pattern 40 of the A pattern electrode print sheet and the internal electrode pattern 40 of the B pattern electrode print sheet are provided. The dummy electrode pattern 33 (33b) separated from the exposed portion is exposed.
Similarly, on the left end surface of each ceramic element 1a, the dummy electrode pattern 33 (33a) of the A pattern electrode print sheet separated from the internal electrode pattern 40 and the internal electrode pattern of the B pattern electrode print sheet are provided. The second region 42 serving as the lead-out portion 40 is exposed.
That is, the mother block is cut at a position where the internal electrode pattern 40 is divided by the one second region 42, and as shown in FIGS. 3C, 3F, etc., the one second region 42 is obtained. A first region 41, a main internal electrode pattern 32 for forming a capacitance including the other second region 42, and a capacitance formed from a part of the other second region 42. The non-contributing dummy electrode pattern 33 is disposed through the ceramic green sheet layer 34, and each of the main internal electrode pattern 32 and the dummy electrode pattern 33 has one end side alternately drawn to one end face and the other end face. The green ceramic multilayer element 1a is divided.
3 (d), (e), and (f) show the case where the number of laminated internal electrodes is three. In practice, however, the internal electrodes usually have several tens to several hundreds of layers. The layer and the dielectric layer are laminated.

(４)そして、セラミック積層素子１ａを焼成した後、その両端面に、主内部電極と導通するように一対の外部電極を形成する。これにより、図１に示すような積層セラミックコンデンサが得られる。   (4) Then, after firing the ceramic multilayer element 1a, a pair of external electrodes is formed on both end faces so as to be electrically connected to the main internal electrode. Thereby, a multilayer ceramic capacitor as shown in FIG. 1 is obtained.

そして、上記の積層セラミックコンデンサの製造方法においては、上記(３)の工程で、図３(ｃ)に示すように、所望の態様で、パターンＡ，およびパターンＢの電極印刷シート３１ａ，３１ｂを位置ずれなく積層し、かつ、所定の位置（カットラインＬ0の位置）で、マザーブロックを位置ずれなくカットした場合、図３(ｄ)に示すように、左端面の電極の露出パターンは、主内部電極パターン３２ａが短く、ダミー電極パターン３３ａが長いパターンとなり、図３(ｅ)に示すように、右端面の電極の露出パターンは、主内部電極パターン３２ｂが長く、ダミー電極パターン３３ｂが短いパターンとなる。 In the method of manufacturing the multilayer ceramic capacitor, the electrode print sheets 31a and 31b of the pattern A and the pattern B are formed in the desired manner as shown in FIG. 3 (c) in the step (3). When stacking without misalignment and cutting the mother block at a predetermined position (the position of the cut line L 0 ) without misalignment, as shown in FIG. The main internal electrode pattern 32a is short and the dummy electrode pattern 33a is long. As shown in FIG. 3E, the exposed pattern of the electrode on the right end surface is long in the main internal electrode pattern 32b and short in the dummy electrode pattern 33b. It becomes a pattern.

一方、図４(ａ)，(ｂ)，(ｃ)に示すように、パターンＡ，およびパターンＢの電極印刷シート３１ａ，３１ｂが位置ずれなく積層されていても、例えば、図４(ｃ)に示すように、本来のカット位置であるカットラインＬ0から、カットラインＬにカット位置がずれた場合（カット位置が全体的に右側にずれた場合）（図４（ｇ）参照）には、図４(ｄ)に示すように、左端面の電極の露出パターンは、主内部電極パターン３２ａが長く、ダミー電極パターン３３ａが短いパターンとなり、図４(ｅ)に示すように、右端面の電極の露出パターンは、主内部電極パターン３２ｂが短く、ダミー電極パターン３３ｂが長いパターンとなる。
したがって、図３(ｄ)，図３(ｅ)、および図４（ｈ）に示す、積層ずれおよびカットずれのない場合の電極の露出パターンと比較することにより、個々の素子において、内部電極の位置ずれが生じて いることが分かる。
なお、図４(ａ)〜(ｈ)において図３(ａ)〜(ｆ)と同一符号を付した部分は、同一部分、または相当部分を示している。 On the other hand, as shown in FIGS. 4A, 4B, and 4C, even if the electrode print sheets 31a and 31b of the pattern A and the pattern B are stacked without misalignment, for example, FIG. As shown in FIG. 4, when the cut position is shifted from the original cut position L 0 to the cut line L (when the cut position is shifted to the right as a whole) (see FIG. 4G). As shown in FIG. 4 (d), the exposed pattern of the electrode on the left end face is a pattern in which the main internal electrode pattern 32a is long and the dummy electrode pattern 33a is short, and as shown in FIG. The electrode exposure pattern is such that the main internal electrode pattern 32b is short and the dummy electrode pattern 33b is long.
Therefore, by comparing with the exposed pattern of the electrode when there is no stacking shift and cut shift shown in FIGS. 3D, 3E, and 4H, in each element, the internal electrode It can be seen that misalignment has occurred.
4 (a) to 4 (h), the same reference numerals as those in FIGS. 3 (a) to 3 (f) denote the same or corresponding parts.

また、例えば、図５(ａ)，(ｂ)，(ｃ)に示すように、パターンＡ，およびパターンＢの電極印刷シート３１ａ，３１ｂが位置ずれなく積層されていても、例えば、図５(ｃ)に示すように、中央部から右側の、カットラインＬ1およびＬ2の位置で、本来のカット位置であるカットラインＬ0よりも右側にカット位置がずれた場合（図５（ｇ）参照）、図５(ｄ)に示すように、左端面の電極の露出パターンは、主内部電極パターン３２ａが短く、ダミー電極パターン３３ａが長いパターンとなり、図５(ｅ)に示すように、右端面の電極の露出パターンも、主内部電極パターン３２ｂが短く、ダミー電極パターン３３ｂが長いパターンとなる。
この場合も、図３(ｄ)，図３(ｅ) 、および図５（ｈ）に示す、積層ずれおよびカットずれのない場合の電極の露出パターンと異なっていることから、個々の素子において、内部電極の位置ずれが生じていることが分かる。
なお、図５(ａ)〜(ｈ)において図３(ａ)〜(ｆ)と同一符号を付した部分は、同一部分、または相当部分を示している。 Further, for example, as shown in FIGS. 5A, 5B, and 5C, even if the electrode print sheets 31a and 31b of the pattern A and the pattern B are laminated without misalignment, for example, FIG. As shown in c), when the cut position is shifted to the right side of the cut line L 0 that is the original cut position at the positions of the cut lines L 1 and L 2 on the right side from the center (FIG. 5G). As shown in FIG. 5 (d), the exposed pattern of the electrode on the left end surface is a pattern in which the main internal electrode pattern 32a is short and the dummy electrode pattern 33a is long, and as shown in FIG. 5 (e), the right end The exposed pattern of the electrodes on the surface also has a pattern in which the main internal electrode pattern 32b is short and the dummy electrode pattern 33b is long.
Also in this case, since it differs from the exposed pattern of the electrode when there is no stacking shift and cut shift shown in FIGS. 3 (d), 3 (e), and 5 (h), in each element, It can be seen that the internal electrodes are misaligned.
5A to 5H, the same reference numerals as those in FIGS. 3A to 3F denote the same or corresponding parts.

また、例えば、図６(ａ)，(ｂ)，(ｃ)に示すように、カットずれはないが、パターンＡ，およびパターンＢの電極印刷シート３１ａ，３１ｂの積層状態に位置ずれ（積層ずれ）が生じている場合、例えば、図６(ｃ)に示すように、カットラインＬ0の位置でカットされる場合、図６(ｄ)に示すように、左端面の電極の露出パターンは、主内部電極パターン３２ａが短く、ダミー電極パターン３３ａが著しく長いパターンとなり、図６(ｅ)に示すように、右端面の電極の露出パターンは、主内部電極パターン３２ｂが著しく長く、ダミー電極パターン３３ｂが短いパターンとなる。
したがって、図３(ｄ)，図３(ｅ)、および図６（ｇ）に示す、積層ずれおよびカットずれのない場合の電極の露出パターン（同一端面に露出する内部電極パターンとダミー電極パターンの長さの比率）の差異から、個々の素子において、内部電極の位置ずれが生じていることが分かる。
なお、図６(ａ)〜(ｇ)において図３(ａ)〜(ｆ)と同一符号を付した部分は、同一部分、または相当部分を示している。 Further, for example, as shown in FIGS. 6A, 6B, and 6C, there is no cut shift, but the positional shift (lamination shift) occurs in the stacked state of the electrode print sheets 31a and 31b of the pattern A and the pattern B. If) occurs, for example, as shown in FIG. 6 (c), when it is cut at the position of the cut line L 0, as shown in FIG. 6 (d), the exposure pattern of the electrode of the left end surface, The main internal electrode pattern 32a is short and the dummy electrode pattern 33a becomes a very long pattern. As shown in FIG. 6E, the exposed pattern of the electrode on the right end surface is that the main internal electrode pattern 32b is remarkably long and the dummy electrode pattern 33b. Becomes a short pattern.
Accordingly, as shown in FIGS. 3D, 3E, and 6G, the exposed pattern of the electrode without the misalignment and cut (the internal electrode pattern exposed on the same end surface and the dummy electrode pattern). From the difference in length ratio, it can be seen that the position shift of the internal electrode occurs in each element.
6A to 6G, the same reference numerals as those in FIGS. 3A to 3F denote the same or corresponding parts.

また、例えば、図７(ａ)，(ｂ)，(ｃ)に示すように、パターンＡ，およびパターンＢの電極印刷シート３１ａ，３１ｂの積層状態に位置ずれ（積層ずれ）が生じている場合において、カットずれも生じた場合、例えば、図７(ｃ)に示すように、中央部から右側の、カットラインＬ1およびＬ2の位置で、本来のカット位置であるカットラインＬ0よりも右側にカット位置がずれた場合（図７（ｇ）参照）、カットラインＬ1およびＬ2の位置でカットされると、図７(ｄ)に示すように、左端面の電極の露出パターンは、主内部電極パターン３２ａが短く、ダミー電極パターン３３ａが著しく長いパターンとなり、図７(ｅ)に示すように、右端面の電極の露出パターンは、主内部電極パターン３２ｂと、ダミー電極パターン３３ｂが同じ長さのパターンとなる。
したがって、図３(ｄ)，図３(ｅ)および図７(ｈ)に示す、位置ずれおよびカットずれのない場合の電極の露出パターンとの差異から、個々の素子において、内部電極の位置ずれが生じていることが分かる。
なお、図７(ａ)〜(ｈ)において図３(ａ)〜(ｆ)と同一符号を付した部分は、同一部分、または相当部分を示している。 Further, for example, as shown in FIGS. 7A, 7B, and 7C, when a positional shift (lamination shift) occurs in the stacked state of the electrode print sheets 31a and 31b of the pattern A and the pattern B. In FIG. 7C, for example, as shown in FIG. 7C, the cut lines L 1 and L 2 on the right side from the center are located at the positions of the cut lines L 1 and L 2 than the cut line L 0 that is the original cut position. When the cut position is shifted to the right side (see FIG. 7G), when the cut is made at the positions of the cut lines L 1 and L 2 , the exposed pattern of the electrode on the left end face is as shown in FIG. The main internal electrode pattern 32a is short and the dummy electrode pattern 33a becomes a very long pattern. As shown in FIG. 7E, the exposed pattern of the electrode on the right end surface is the main internal electrode pattern 32b and the dummy electrode pattern 33b. Same length pattern It becomes.
Therefore, the position shift of the internal electrode in each element is determined from the difference from the exposed pattern of the electrode when there is no position shift and cut shift shown in FIGS. 3 (d), 3 (e) and 7 (h). It can be seen that
7A to 7H, the same reference numerals as those in FIGS. 3A to 3F denote the same or corresponding parts.

このように、本願発明の積層セラミックコンデンサの製造方法によれば、原因のいかんによらず、確実に主内部電極の位置ずれの有無を検出することが可能になり、不良品の混入がなく、信頼性の高い積層セラミックコンデンサを効率よく製造することができる。   As described above, according to the method for manufacturing a multilayer ceramic capacitor of the present invention, it is possible to reliably detect the presence or absence of misalignment of the main internal electrode regardless of the cause, and there is no mixing of defective products. A highly reliable multilayer ceramic capacitor can be manufactured efficiently.

なお、上記実施例１では、主内部電極の第２部分、およびダミー電極の、引き出し端面に向かって連続的に幅が変化する部分が台形形状で、引き出し端面に向かって幅が狭くなるような形状としたが、主内部電極の第２部分およびダミー電極の、引き出し端面に向かって連続的に幅が変化する部分の形状に特別の制約はなく、例えば、図８(ａ)，(ｂ)，(ｃ)に示すように、主内部電極の第２部分、およびダミー電極の、引き出し端面に向かって連続的に幅が変化する部分の形状を丸みを有する曲線形状とすることも可能である。   In the first embodiment, the second portion of the main internal electrode and the portion of the dummy electrode whose width continuously changes toward the leading end surface are trapezoidal and the width becomes narrower toward the leading end surface. However, there is no particular limitation on the shape of the second portion of the main internal electrode and the portion of the dummy electrode whose width continuously changes toward the lead-out end face. For example, FIGS. 8 (a) and 8 (b) , (C), it is also possible to make the shape of the second portion of the main internal electrode and the portion of the dummy electrode whose width continuously changes toward the lead-out end surface into a rounded curved shape. .

また、図９(ａ)，(ｂ)に示すように、主内部電極２ａ，２ｂの第２部分１２ａ，１２ｂ、およびダミー電極３ａ，３ｂの、引き出し端面５ａ，５ｂに向かって連続的に幅が変化する部分が台形形状で、第２部分１２ａ，１２ｂでは引き出し端面５ａ，５ｂに向かって幅が広くなり、ダミー電極３ａ，３ｂでは引き出し端面５ａ，５ｂに向かって幅が狭くなるような形状とすることも可能である。   Further, as shown in FIGS. 9A and 9B, the second portions 12a and 12b of the main internal electrodes 2a and 2b and the widths of the dummy electrodes 3a and 3b continuously toward the leading end surfaces 5a and 5b. Is a trapezoidal shape, the second portions 12a and 12b are wider toward the leading end surfaces 5a and 5b, and the dummy electrodes 3a and 3b are narrower toward the leading end surfaces 5a and 5b. It is also possible.

また、図１０(ａ)，(ｂ)に示すように、図９(ａ)，(ｂ)の主内部電極２ａ，２ｂの第２部分、およびダミー電極３ａ，３ｂに相当する、主内部電極２ａ，２ｂの第２部分１２ａ，１２ｂ（図１０(ａ)，(ｂ)）、およびダミー電極３ａ，３ｂ（図１０(ａ)，(ｂ)）の、引き出し端面５ａ，５ｂに向かって連続的に幅が変化する部分の形状を丸みを有する曲線形状とすることも可能である。   Further, as shown in FIGS. 10A and 10B, the main internal electrodes corresponding to the second portions of the main internal electrodes 2a and 2b and the dummy electrodes 3a and 3b in FIGS. 9A and 9B. The second portions 12a and 12b of 2a and 2b (FIGS. 10 (a) and (b)) and the dummy electrodes 3a and 3b (FIGS. 10 (a) and (b)) continue toward the leading end surfaces 5a and 5b. In particular, the shape of the portion where the width changes can be a curved shape having a round shape.

なお、本願発明は上記実施例に限定されるものではなく、主内部電極およびダミー電極、特に、主内部電極の第２部分、およびダミー電極の、引き出し端面に向かって連続的に幅が変化する部分の具体的な形状、電極やセラミック層の積層数などに関し発明の範囲内において、種々の応用、変形を加えることが可能である。   The present invention is not limited to the above-described embodiments, and the width continuously changes toward the leading end surface of the main internal electrode and the dummy electrode, particularly the second portion of the main internal electrode and the dummy electrode. Various applications and modifications can be made within the scope of the invention with respect to the specific shape of the portion, the number of stacked electrodes and ceramic layers, and the like.

上述のように、本願発明によれば、原因のいかんにかかわらず（すなわち、積層ずれとカットずれのいずれか一方が生じた場合や、積層ずれとカットずれの両方が生じた場合にも）、内部電極の位置ずれを確実に検出することが可能で、所望の特性を備えた積層セラミックコンデンサを効率よく、しかも経済的に製造することが可能になる。
したがって、本願発明は、内部電極パターンが形成されたセラミックグリーンシートを積層することにより形成されたマザーブロック（積層体）を切断し、焼成する工程を経て製造される積層セラミックコンデンサおよびその製造方法に広く適用することが可能である。 As described above, according to the present invention, regardless of the cause (that is, when either one of the stacking shift and the cut shift occurs, or when both the stacking shift and the cut shift occur), The positional deviation of the internal electrodes can be reliably detected, and a multilayer ceramic capacitor having desired characteristics can be manufactured efficiently and economically.
Accordingly, the present invention relates to a multilayer ceramic capacitor manufactured through a process of cutting and firing a mother block (laminated body) formed by laminating ceramic green sheets on which internal electrode patterns are formed, and a method for manufacturing the same. It can be widely applied.

本願発明の一実施例にかかる積層セラミックコンデンサの構造を示す図であり、(ａ)は正面断面図、(ｂ)は外部電極を形成する前のセラミック積層素子の左側面（左端面）を示す図、(ｃ)は外部電極を形成する前のセラミック積層素子の右側面（右端面）を示す図である。It is a figure which shows the structure of the multilayer ceramic capacitor concerning one Example of this invention, (a) is front sectional drawing, (b) shows the left side surface (left end surface) of the ceramic multilayer element before forming an external electrode. FIG. 4C is a diagram showing the right side surface (right end surface) of the ceramic multilayer element before forming the external electrode. (ａ)は、図１の積層セラミックコンデンサを構成する一対の内部電極およびダミー電極のうちの、一方の内部電極およびダミー電極の形状を示す図、(ｂ)は、他方の内部電極およびダミー電極の形状を示す図、(ｃ)は(ａ)と(ｂ)の内部電極およびダミー電極の積層の態様を示す透視平面図である。(a) is a figure which shows the shape of one internal electrode and dummy electrode of a pair of internal electrode and dummy electrode which comprise the multilayer ceramic capacitor of FIG. 1, (b) is the other internal electrode and dummy electrode. FIG. 7C is a perspective plan view showing a stacking mode of internal electrodes and dummy electrodes of FIGS. (ａ)および(ｂ)は、本願発明の積層セラミックコンデンサを製造するのに用いた異なるパターンの一対の電極印刷シートを示す平面図、(ｃ)は電極印刷シートを積層した状態を示す図、(ｄ)はマザーブロックをカットすることにより得られる個々の素子の左側面図、(ｅ)はその右側面図、(ｆ)はその正面断面図である。(a) and (b) is a plan view showing a pair of electrode printing sheets of different patterns used to produce the multilayer ceramic capacitor of the present invention, (c) is a diagram showing a state in which the electrode printing sheets are laminated, (d) is a left side view of each element obtained by cutting the mother block, (e) is a right side view thereof, and (f) is a front sectional view thereof. (ａ)〜(ｈ)は、本願発明の積層セラミックコンデンサの製造方法の一工程で、カットずれが生じた場合の挙動の一態様を説明する図である。(a)-(h) is a figure explaining the one aspect | mode of the behavior at the time of cut | offset | difference arising in one process of the manufacturing method of the multilayer ceramic capacitor of this invention. (ａ)〜(ｈ)は、本願発明の積層セラミックコンデンサの製造方法の一工程で、カットずれが生じた場合の挙動の他の態様を説明する図である。(a)-(h) is a figure explaining the other aspect of the behavior when cut shift | offset | difference arises at 1 process of the manufacturing method of the multilayer ceramic capacitor of this invention. (ａ)〜(ｇ)は、本願発明の積層セラミックコンデンサの製造方法の一工程で、積層ずれが生じた場合の挙動の一態様を説明する図である。(a)-(g) is a figure explaining the one aspect | mode of the behavior when a lamination | stacking shift | offset | difference arises at one process of the manufacturing method of the multilayer ceramic capacitor of this invention. (ａ)〜(ｈ)は、本願発明の積層セラミックコンデンサの製造方法の一工程で、積層ずれおよびカットずれが生じた場合の挙動の一態様を説明する図である。(a)-(h) is a figure explaining one aspect | mode of the behavior when a lamination | stacking shift | offset | difference and cut shift | offset | difference have arisen at one process of the manufacturing method of the multilayer ceramic capacitor of this invention. (ａ)〜(ｃ)は、本願発明の変形例を示す図である。(a)-(c) is a figure which shows the modification of this invention. (ａ)，(ｂ)は、本願発明の他の変形例を示す図である。(a), (b) is a figure which shows the other modification of this invention. (ａ)，(ｂ)は、本願発明のさらに他の変形例を示す図である。(a), (b) is a figure which shows the further another modification of this invention. 従来の積層セラミックコンデンサを示す断面図である。It is sectional drawing which shows the conventional multilayer ceramic capacitor. (ａ)，(ｂ)，(ｃ)は、従来の積層セラミックコンデンサ（の製造方法）の一例を示す図であり、 (ａ)，(ｂ)は、セラミック積層素子５１中において、セラミック層を介して対向する一対の内部電極やダミー電極の形状などを示す平面図、(ｃ)は一対の内部電極を互いに対向するように重ね合わせた状態を示す平面図である。(a), (b), (c) is a figure which shows an example of the conventional multilayer ceramic capacitor (manufacturing method), (a), (b) is a ceramic layer in the ceramic multilayer element 51. FIG. 4C is a plan view showing the shape of a pair of internal electrodes and dummy electrodes facing each other through the gap, and FIG. 5C is a plan view showing a state in which the pair of internal electrodes are stacked so as to face each other. 従来の他の積層セラミックコンデンサの製造方法を示す図である。It is a figure which shows the manufacturing method of the other conventional multilayer ceramic capacitor.

符号の説明Explanation of symbols

１ セラミック積層素子
１ａ 個々の素子（未焼成のセラミック積層素子）
２ａ，２ｂ 主内部電極
３ａ，３ｂ ダミー電極
４ セラミック層
５ａ セラミック積層素子の一方端面（引き出し端面）
５ｂ セラミック積層素子の他方端面（引き出し端面）
６ａ，６ｂ 外部電極
１１ 主内部電極の第１部分
１２ａ，１２ｂ 主内部電極の第２部分
２２ 辺
２３ ダミー電極の辺
３１ａ パターンＡの電極印刷シート
３１ｂ パターンＢの電極印刷シート
３２（３２ａ，３２ｂ） 主内部電極パターン
３３（３３ａ，３３ｂ） ダミー電極パターン
３４ セラミックグリーンシート層
４０ 内部電極パターン
４１ 内部電極パターンの第１領域
４２ 内部電極パターンの第２領域
Ｌ，Ｌ1，Ｌ2 カットライン
Ｌ0 本来のカットライン
Ｘ 第１領域と第２領域の連設方向 1 Ceramic multilayer element 1a Individual element (unfired ceramic multilayer element)
2a, 2b Main internal electrode 3a, 3b Dummy electrode 4 Ceramic layer 5a One end face (leading end face) of ceramic multilayer element
5b The other end face (drawer end face) of the ceramic multilayer element
6a, 6b External electrode 11 Main internal electrode first portion 12a, 12b Main internal electrode second portion 22 Side 23 Dummy electrode side 31a Pattern A electrode print sheet 31b Pattern B electrode print sheet 32 (32a, 32b) Main internal electrode pattern 33 (33a, 33b) Dummy electrode pattern 34 Ceramic green sheet layer 40 Internal electrode pattern 41 First region of internal electrode pattern 42 Second region of internal electrode pattern L, L 1 , L 2 cut line L 0 Original Cut line X Direction of connection between the first and second areas

Claims (5)

セラミック積層素子の内部に、静電容量形成用の複数の主内部電極および静電容量の形成に寄与しないダミー電極がセラミック層を介して配設され、かつ、主内部電極およびダミー電極は、セラミック積層素子の一方端面および他方端面のうちの互いに逆側の端面に引き出されているとともに、一層ごとに逆側の端面に引き出され、セラミック積層素子の両端側には、少なくとも主内部電極と導通するように一対の外部電極が配設された構造を有する積層セラミックコンデンサであって、
主内部電極は、矩形形状の第１部分と、第１部分の両側に連設された第２部分から構成され、主内部電極の第２部分は、引き出し端面に向かって連続的に幅が変化する形状を有しており、
ダミー電極は、主内部電極と同一平面に並置され、かつ、引き出し端面に向かって連続的に幅が変化する形状を有していること
を特徴とする積層セラミックコンデンサ。 A plurality of main internal electrodes for forming a capacitance and a dummy electrode that does not contribute to the formation of the capacitance are disposed inside the ceramic multilayer element via a ceramic layer, and the main internal electrode and the dummy electrode are made of ceramic. The multilayer element is drawn to the opposite end face of the one end face and the other end face, and is drawn to the opposite end face for each layer, and at least both ends of the ceramic multilayer element are electrically connected to the main internal electrode. A multilayer ceramic capacitor having a structure in which a pair of external electrodes are arranged as follows:
The main internal electrode is composed of a rectangular first portion and second portions connected to both sides of the first portion, and the width of the second portion of the main internal electrode continuously changes toward the lead end surface. Has a shape to
The multilayer ceramic capacitor, wherein the dummy electrode is juxtaposed in the same plane as the main internal electrode, and has a shape whose width continuously changes toward the leading end face. 主内部電極の第２部分、およびダミー電極の引き出し端面に向かって連続的に幅が変化する部分が、直線形状または曲線形状を有していることを特徴とする請求項１記載の積層セラミックコンデンサ。   2. The multilayer ceramic capacitor according to claim 1, wherein the second portion of the main internal electrode and the portion whose width continuously changes toward the leading end face of the dummy electrode have a linear shape or a curved shape. . セラミック積層素子の内部に、静電容量形成用の複数の主内部電極および静電容量の形成に寄与しないダミー電極がセラミック層を介して配設され、かつ、主内部電極およびダミー電極は、セラミック積層素子の一方端面および他方端面のうちの互いに逆側の端面に引き出されているとともに、一層ごとに逆側の端面に引き出され、セラミック積層素子の両端側には、少なくとも主内部電極と導通するように一対の外部電極が配設された構造を有する積層セラミックコンデンサの製造方法であって、
(ａ)セラミックグリーンシート上に、矩形形状の第１領域と、第１領域の両側に連設された第２領域から構成され、第２領域は、第１領域からの距離が大きくなる方向に向かって連続的に幅が変化する形状を有する複数の内部電極パターンをマトリックス状に形成する工程と、
(ｂ)内部電極パターンが形成されたセラミックグリーンシートを積層することにより、内部電極パターンの位置が、各セラミックグリーンシートごとに交互に、第１領域と第２領域の連設方向にずれた状態のマザーブロックを形成する工程と、
(ｃ)マザーブロックを、内部電極パターンが一方の第２領域で分割される位置で切断して、第１領域と、２つの第２領域のうちの一方の第２領域と、他方の第２領域の一部とを含む静電容量形成用の主内部電極パターンと、他方の第２領域の一部から形成される静電容量の形成に寄与しないダミー電極パターンがセラミックグリーンシート層を介して配設され、かつ、主内部電極パターンと、ダミー電極パターンがセラミック積層素子の一方端面および他方端面のうちの互いに逆側の端面に引き出されているとともに、一層ごとに逆側の端面に引き出された個々の未焼成のセラミック積層素子に分割する工程と、
(ｄ)セラミック積層素子を焼成する工程と、
(ｅ)セラミック積層素子に、少なくとも主内部電極と導通するように一対の外部電極を形成する工程と
を具備することを特徴とする積層セラミックコンデンサの製造方法。 A plurality of main internal electrodes for forming a capacitance and a dummy electrode that does not contribute to the formation of the capacitance are disposed inside the ceramic multilayer element via a ceramic layer, and the main internal electrode and the dummy electrode are made of ceramic. The multilayer element is drawn to the opposite end face of the one end face and the other end face, and is drawn to the opposite end face for each layer, and at least both ends of the ceramic multilayer element are electrically connected to the main internal electrode. A method for manufacturing a multilayer ceramic capacitor having a structure in which a pair of external electrodes is disposed as follows:
(a) On a ceramic green sheet, it is composed of a rectangular first region and second regions connected to both sides of the first region, and the second region is in a direction in which the distance from the first region increases. Forming a plurality of internal electrode patterns having a shape whose width continuously changes toward the matrix,
(b) A state in which the positions of the internal electrode patterns are alternately shifted in the connecting direction of the first region and the second region by stacking the ceramic green sheets on which the internal electrode patterns are formed. Forming a mother block of
(c) The mother block is cut at a position where the internal electrode pattern is divided by one second region, and the first region, one second region of the two second regions, and the other second region. A main internal electrode pattern for forming a capacitance including a part of the region and a dummy electrode pattern that does not contribute to the formation of a capacitance formed from a part of the other second region through the ceramic green sheet layer The main internal electrode pattern and the dummy electrode pattern are drawn to the opposite end faces of the one end face and the other end face of the ceramic multilayer element, and are drawn to the opposite end face for each layer. Dividing into individual unfired ceramic laminate elements;
(d) firing the ceramic multilayer element;
(e) forming a pair of external electrodes in the ceramic multilayer element so as to be electrically connected to at least the main internal electrode. 内部電極パターンの矩形形状の第１領域と、その両側に連設された第２領域から構成される内部電極パターンの形状が、第１領域を挟んで対称の形状を有していることを特徴とする請求項３記載の積層セラミックコンデンサの製造方法。   The shape of the internal electrode pattern composed of the rectangular first region of the internal electrode pattern and the second region continuously provided on both sides thereof has a symmetric shape across the first region. The method for producing a multilayer ceramic capacitor according to claim 3. 内部電極パターンの第２領域の、第１領域からの距離が大きくなる方向に向かって連続的に幅が変化する部分が、直線形状または曲線形状を有していることを特徴とする請求項３または４記載の積層セラミックコンデンサの製造方法。   The portion of the internal electrode pattern in which the width continuously changes in the direction in which the distance from the first region increases in the second region has a linear shape or a curved shape. Or the manufacturing method of the multilayer ceramic capacitor of 4.
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JP7148343B2 (en) 2018-02-09 2022-10-05 太陽誘電株式会社 Multilayer ceramic electronic component manufacturing method and multilayer ceramic electronic component
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