JP5278476B2 - Multilayer capacitor - Google Patents

Multilayer capacitor Download PDF

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JP5278476B2
JP5278476B2 JP2011075356A JP2011075356A JP5278476B2 JP 5278476 B2 JP5278476 B2 JP 5278476B2 JP 2011075356 A JP2011075356 A JP 2011075356A JP 2011075356 A JP2011075356 A JP 2011075356A JP 5278476 B2 JP5278476 B2 JP 5278476B2
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尚 鈴木
友由喜 谷川
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TDK Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked capacitor that reduces a product-specific variation in capacitance while suppressing penetration of a plating solution. <P>SOLUTION: In a stacked capacitor 100, an internal electrode layer 7 includes a first internal electrode 20 and a second internal electrode 30, and each internal electrode 20, 30 includes an active electrode portion 21, 31 of a fixed width positioned far from an end face and a lead electrode portion 22, 32 of a fixed width narrower than the active electrode portion 21, 31 and positioned near to the end face. An intermediate internal electrode layer 8 includes a third internal electrode 40, and the third internal electrode 40 has a shape extending in an X direction with overlaps on a part 22a of the lead electrode portion 22 of the first internal electrode 20 and a part 32a of the lead electrode portion 32 of the second internal electrode 30 and wider than the width w1 of the active electrode portion 21, 31 of each internal electrode 20, 30. <P>COPYRIGHT: (C)2013,JPO&amp;INPIT

Description

本発明は積層コンデンサに関する。   The present invention relates to a multilayer capacitor.

従来、電極パターンが設けられた複数の誘電体層を積層して形成される積層コンデンサが知られており、たとえば下記特許文献1に開示されている。特許文献1に開示された積層コンデンサは、内部電極層とフロート電極層とが誘電体層を介して交互に積層された素体を有しており、内部電極とフロート電極とにより直列コンデンサ成分が形成されている。   2. Description of the Related Art Conventionally, a multilayer capacitor formed by laminating a plurality of dielectric layers provided with an electrode pattern is known, and for example, disclosed in Patent Document 1 below. The multilayer capacitor disclosed in Patent Document 1 has an element body in which internal electrode layers and float electrode layers are alternately stacked via dielectric layers, and a series capacitor component is formed by the internal electrodes and the float electrodes. Is formed.

特開平7−135124号公報JP-A-7-135124

上述のような積層コンデンサを作製する際、電極パターンが形成された誘電体層を積層する工程において、積層方向に直交する方向における位置ズレ(積層ズレ)が上下に重なる誘電体層間で生じることがある。このような積層ズレは、積層コンデンサの製品間での静電容量のばらつきにつながる。特に、近年の数ギガヘルツ帯の高周波フィルタに用いられる小さい静電容量(たとえば10pF程度)の積層コンデンサにおいては、その静電容量のばらつきの低減が、非常に重要な技術的課題となっている。   When the multilayer capacitor as described above is manufactured, in the step of laminating the dielectric layers on which the electrode patterns are formed, a positional deviation (lamination misalignment) in a direction orthogonal to the laminating direction may occur between the dielectric layers that overlap one above the other. is there. Such a misalignment leads to variations in capacitance among the multilayer capacitor products. In particular, in a multilayer capacitor having a small capacitance (for example, about 10 pF) used in a recent high frequency filter of several gigahertz band, reduction of variation in the capacitance has become a very important technical problem.

また、積層コンデンサの素体の端面には、端子電極がめっき形成されるが、そのめっき形成の際に用いられるめっき液が、素体内に侵入した場合には、積層コンデンサの信頼性の低下につながることが知られている。   In addition, the terminal electrode is plated on the end face of the multilayer capacitor element, but if the plating solution used in the plating formation penetrates into the element body, the reliability of the multilayer capacitor is reduced. It is known to connect.

本発明は、上述の課題を解決するためになされたものであり、めっき液の浸入を抑制しつつ、製品間における静電容量のばらつきの低減が図られた積層コンデンサを提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer capacitor in which variation in capacitance among products is reduced while suppressing infiltration of a plating solution. To do.

本発明に係る積層コンデンサは、内部電極層と中間内部電極層とが誘電体層を介して交互に積層された素体を備える積層コンデンサであって、素体の互いに対面する第1の端面および第2の端面には、第1の端子電極および第2の端子電極がそれぞれ設けられ、内部電極層は、第1の端子電極と電気的に接続されるとともに第1の端面の側から第2の端面方向に延びる第1の内部電極と、第2の端子電極と電気的に接続されるとともに第2の端面の側から第1の端面方向に延びる第2の内部電極とを含み、第1の内部電極および第2の内部電極がそれぞれ、端面から遠い側に位置する同幅の活性電極部と、活性電極部より幅狭であり、活性電極部より端面に近い側に位置する同幅の引出電極部とを含み、中間内部電極層は、第1の端子電極および第2の端子電極のいずれとも接続されず、第1の内部電極および第2の内部電極との間で直列に接続された複数の容量成分を形成する第3の内部電極を含み、第3の内部電極は、第1の内部電極の引出電極部の一部および第2の内部電極の引出電極部の一部と重畳するように、第1の端面と第2の端面との対面方向に延在し、かつ、第1の内部電極および第2の内部電極の活性電極部の幅よりも幅広の形状を有する。   A multilayer capacitor in accordance with the present invention is a multilayer capacitor including an element body in which internal electrode layers and intermediate internal electrode layers are alternately stacked via dielectric layers, the first end face of the element body facing each other, and The second end face is provided with a first terminal electrode and a second terminal electrode, respectively, and the internal electrode layer is electrically connected to the first terminal electrode and second from the first end face side. A first internal electrode extending in the end face direction, and a second internal electrode electrically connected to the second terminal electrode and extending from the second end face side in the first end face direction, The inner electrode and the second inner electrode are each of an active electrode portion having the same width located on the side farther from the end face, and the same width being narrower than the active electrode portion and closer to the end face than the active electrode portion And an intermediate internal electrode layer is formed on the first terminal electrode. And a third internal electrode that is not connected to any of the second terminal electrodes and forms a plurality of capacitance components connected in series between the first internal electrode and the second internal electrode, The internal electrode of the first internal electrode overlaps with a part of the extraction electrode part of the first internal electrode and a part of the extraction electrode part of the second internal electrode in a facing direction between the first end surface and the second end surface. It extends and has a shape wider than the width of the active electrode portion of the first internal electrode and the second internal electrode.

この積層コンデンサにおいては、内部電極層と中間内部電極層との間に、第3の内部電極の幅方向に関する積層ズレが生じた場合、第1の内部電極および第2の内部電極の活性電極部の幅よりも第3の内部電極が幅広の形状を有するため、第3の内部電極の幅方向に関する積層ズレに起因する静電容量の変化を抑えることができる。また、内部電極層と中間内部電極層との間に、第3の内部電極の延在方向(すなわち、第1の端面と第2の端面との対面方向)に関する積層ズレが生じた場合でも、第1の内部電極と第2の内部電極とが同幅の活性電極部および引出電極部を含むため、第3の内部電極の延在方向に関する積層ズレに起因する静電容量の変化も抑えることができる。特に、引出電極部の幅が活性電極部の幅よりも狭くなっているため、幅狭の引出電極部が形成されていない場合に比べて、第3の内部電極の延在方向に関する積層ズレの際に、第1の内部電極と第3の内部電極との対向面積の変化および第2の内部電極と第3の内部電極との対向面積の変化が低減され、その結果、第1の内部電極、第2の内部電極および第3の内部電極で形成される、直列に接続された複数の容量成分の合成容量の変化が低減される。このように、本発明に係る積層コンデンサは、積層ズレが生じた場合であっても、静電容量の変化を抑えることができるため、製品間における静電容量のばらつき低減が実現される。   In this multilayer capacitor, when a misalignment in the width direction of the third internal electrode occurs between the internal electrode layer and the intermediate internal electrode layer, the active electrode portions of the first internal electrode and the second internal electrode Since the third internal electrode has a shape wider than the width of the third internal electrode, it is possible to suppress a change in capacitance caused by stacking misalignment in the width direction of the third internal electrode. In addition, even when a stacking misalignment between the internal electrode layer and the intermediate internal electrode layer occurs in the extending direction of the third internal electrode (that is, the facing direction between the first end surface and the second end surface), Since the first internal electrode and the second internal electrode include the active electrode portion and the extraction electrode portion having the same width, it is possible to suppress a change in capacitance due to stacking misalignment in the extending direction of the third internal electrode. Can do. In particular, since the width of the extraction electrode portion is narrower than the width of the active electrode portion, the stacking deviation in the extending direction of the third internal electrode is smaller than when the narrow extraction electrode portion is not formed. In this case, the change in the facing area between the first internal electrode and the third internal electrode and the change in the facing area between the second internal electrode and the third internal electrode are reduced, and as a result, the first internal electrode The change in the combined capacitance of the plurality of capacitance components connected in series formed by the second internal electrode and the third internal electrode is reduced. As described above, since the multilayer capacitor according to the present invention can suppress the change in capacitance even when the multilayer deviation occurs, the variation in capacitance among products can be reduced.

加えて、第1の内部電極および第2の内部電極においては、各引出電極部の幅が各活性電極部の幅よりも狭いため、素体の第1の端面および第2の端面に第1の端子電極および第2の端子電極をめっき形成する際にめっき液が浸入しにくく、めっき液の浸入による積層コンデンサの信頼性低下を抑制することができる。   In addition, in the first internal electrode and the second internal electrode, since the width of each extraction electrode portion is narrower than the width of each active electrode portion, the first end face and the second end face of the element body have first When the terminal electrode and the second terminal electrode are formed by plating, it is difficult for the plating solution to enter, and a decrease in the reliability of the multilayer capacitor due to the penetration of the plating solution can be suppressed.

また、第1の内部電極および第2の内部電極の活性電極部の幅方向における端部位置と、第3の内部電極の幅方向における端部位置との差が、第1の内部電極または第2の内部電極の活性電極部の延在方向の端部位置と、第3の内部電極の延在方向の端部位置との差よりも大きい態様であってもよい。この場合、第3の内部電極の延在方向における積層ズレに比べて、幅方向における積層ズレに起因する静電容量の変化を効果的に抑えることができる。   The difference between the end position in the width direction of the active electrode portion of the first internal electrode and the second internal electrode and the end position in the width direction of the third internal electrode is the difference between the first internal electrode or the first internal electrode and the second internal electrode. The aspect larger than the difference of the edge part position of the extending direction of the active electrode part of 2 internal electrodes and the extending direction of the 3rd internal electrode may be sufficient. In this case, it is possible to effectively suppress the change in the capacitance due to the stacking misalignment in the width direction as compared with the stacking misalignment in the extending direction of the third internal electrode.

また、複数の内部電極層のうち、素体の積層方向における最も外側に位置する内部電極層が、中間内部電極層よりも素体の積層方向における外側に位置する態様であってもよい。中間内部電極層が、内部電極層よりも素体の積層方向における外側に位置する場合には、第1の端子電極および第2の端子電極と中間内部電極層の第3の内部電極との間で浮遊容量が生じてしまうが、上記態様にすることにより、この浮遊容量の発生を回避することができる。   Moreover, the aspect which an internal electrode layer located in the outermost direction in the lamination direction of an element body among several internal electrode layers may be located in the outer side in the lamination direction of an element body rather than an intermediate | middle internal electrode layer may be sufficient. When the intermediate internal electrode layer is located outside the internal electrode layer in the stacking direction of the element body, it is between the first terminal electrode and the second terminal electrode and the third internal electrode of the intermediate internal electrode layer. However, stray capacitance can be avoided by adopting the above embodiment.

本発明によれば、めっき液の浸入を抑制しつつ、製品間における静電容量のばらつきの低減が図られた積層コンデンサが提供される。   ADVANTAGE OF THE INVENTION According to this invention, the multilayer capacitor by which the dispersion | variation in the electrostatic capacitance between products was aimed at was suppressed, suppressing the penetration | invasion of plating solution.

図1は、本発明の実施形態に係る積層コンデンサを示す斜視図である。FIG. 1 is a perspective view showing a multilayer capacitor according to an embodiment of the present invention. 図2は、図1に示す積層コンデンサのII−II線に沿った断面図である。2 is a cross-sectional view taken along the line II-II of the multilayer capacitor shown in FIG. 図3は、図2に示す積層コンデンサのIII−III線に沿った断面図である。3 is a cross-sectional view taken along line III-III of the multilayer capacitor shown in FIG. 図4は、図1の積層コンデンサの素体を誘電体層ごとに展開した展開図である。FIG. 4 is a development view in which the element body of the multilayer capacitor of FIG. 1 is developed for each dielectric layer. 図5は、内部電極層の第1の内部電極および第2の内部電極を積層方向から見た図である。FIG. 5 is a view of the first internal electrode and the second internal electrode of the internal electrode layer as seen from the stacking direction. 図6は、中間内部電極層の第3の内部電極を積層方向から見た図である。FIG. 6 is a view of the third internal electrode of the intermediate internal electrode layer as viewed from the stacking direction. 図7は、従来技術に係る積層コンデンサの内部電極層を積層方向から見た図である。FIG. 7 is a view of the internal electrode layer of the multilayer capacitor according to the prior art as viewed from the lamination direction. 図8は、最外内部電極層を積層方向から見た図である。FIG. 8 is a view of the outermost internal electrode layer as viewed from the stacking direction.

以下、添付図面を参照して、本発明の好適な実施形態について詳細に説明する。なお、説明において、同一要素又は同一機能を有する要素には、同一符号を用いることとし、重複する説明は省略する。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

図1〜4を参照しつつ、本発明の実施形態に係る積層コンデンサ100の構成について説明する。図1は、積層コンデンサ100を示す斜視図である。図2は、図1に示す積層コンデンサ100のII−II線に沿った断面図である。図3は、図2に示す積層コンデンサ100のIII−III線に沿った断面図である。図4は、積層コンデンサ100の素体1を誘電体層ごとに展開した展開図である。   The configuration of the multilayer capacitor 100 according to the embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a perspective view showing the multilayer capacitor 100. FIG. 2 is a cross-sectional view taken along the line II-II of the multilayer capacitor 100 shown in FIG. 3 is a cross-sectional view of the multilayer capacitor 100 shown in FIG. 2 taken along the line III-III. FIG. 4 is a development view in which the element body 1 of the multilayer capacitor 100 is developed for each dielectric layer.

図1に示すように、積層コンデンサ100は、複数の長方形板状の誘電体層を積層して一体化することによって略直方体形状に構成された素体1と、第1の端子電極2および第2の端子電極3を備えている。積層コンデンサ100は、長さ0.4〜5.7mm、幅0.2〜5.0mm、厚さ0.2〜3.2mm程度である。   As shown in FIG. 1, the multilayer capacitor 100 includes a base body 1 configured in a substantially rectangular parallelepiped shape by stacking and integrating a plurality of rectangular plate-shaped dielectric layers, a first terminal electrode 2, and a first terminal electrode 2. 2 terminal electrodes 3 are provided. The multilayer capacitor 100 has a length of about 0.4 to 5.7 mm, a width of 0.2 to 5.0 mm, and a thickness of about 0.2 to 3.2 mm.

第1の端子電極2は、素体1の長手方向(図のX方向)の第1の端面1aに形成された外部電極であり、素体1の第1の端面1aを覆うと共に、当該端面に隣接する4つの側面の一部を一体的に覆うように形成されている。また、第2の端子電極3は、第1の端面1aに対面する反対側の端面(第2の端面)1bに形成された外部電極であり、素体1の第2の端面1bを覆うと共に、当該端面に隣接する4つの側面の一部を一体的に覆うように形成されている。   The first terminal electrode 2 is an external electrode formed on the first end face 1a in the longitudinal direction (X direction in the figure) of the element body 1 and covers the first end face 1a of the element body 1 and the end face Is formed so as to integrally cover a part of four side surfaces adjacent to each other. The second terminal electrode 3 is an external electrode formed on the opposite end surface (second end surface) 1b facing the first end surface 1a and covers the second end surface 1b of the element body 1. The four side surfaces adjacent to the end surface are integrally covered.

第1の端子電極2および第2の端子電極3は、素体1にめっき形成される。具体的には、素体1の外面にCuやNi、あるいはAg、Pd等を主成分とする導電性ペーストをディップなどによって付着させた後に所定温度(例えば、700℃程度)にて焼き付け、更に電気めっきを施すことにより、形成される。電気めっきには、Ni、Sn等を用いることができる。第1の端子電極2および第2の端子電極3の厚さは、20〜700μm程度に設定される。   The first terminal electrode 2 and the second terminal electrode 3 are plated on the element body 1. Specifically, a conductive paste mainly composed of Cu, Ni, Ag, Pd or the like is attached to the outer surface of the element body 1 by dipping or the like, and then baked at a predetermined temperature (for example, about 700 ° C.). It is formed by applying electroplating. Ni, Sn, etc. can be used for electroplating. The thicknesses of the first terminal electrode 2 and the second terminal electrode 3 are set to about 20 to 700 μm.

素体1は、図2および図3に示すように、複数の長方形板状の誘電体層6と、複数の内部電極層7および複数の中間内部電極層8とが積層された積層体として構成されている。内部電極層7と中間内部電極層8とは、素体1内において誘電体層6の積層方向(図のZ方向)(以下、単に「積層方向」と称する。)に沿ってそれぞれ一層ずつ配置されており、少なくとも一層の誘電体層6を挟むように対向配置されている。素体1においては、内部電極層7と中間内部電極層8とは誘電体層6を介して交互に積層されている。なお、複数の内部電極層7のうち、積層方向における最も外側に位置する内部電極層を、最外内部電極層9として区別する。   As shown in FIGS. 2 and 3, the element body 1 is configured as a laminated body in which a plurality of rectangular plate-like dielectric layers 6, a plurality of internal electrode layers 7, and a plurality of intermediate internal electrode layers 8 are stacked. Has been. The internal electrode layer 7 and the intermediate internal electrode layer 8 are arranged one by one in the element body 1 along the stacking direction (Z direction in the figure) of the dielectric layer 6 (hereinafter simply referred to as “stacking direction”). Are disposed so as to sandwich at least one dielectric layer 6 therebetween. In the element body 1, the internal electrode layers 7 and the intermediate internal electrode layers 8 are alternately stacked via the dielectric layers 6. Of the plurality of internal electrode layers 7, the outermost internal electrode layer in the stacking direction is distinguished as the outermost internal electrode layer 9.

実際には、積層コンデンサ100の素体1における複数の誘電体層6は、互いの間の境界が視認できない程度に一体化されている。素体1は、図4に示すように、10枚のセラミックグリーシートを重ね合わせて焼成して一体化することによって形成される。具体的には、10枚のセラミックグリーンシートは、上から順に、電極パターンが形成されていないシート10、最外内部電極層9の電極パターンが形成されたシート13、中間内部電極層8の電極パターンが形成されたシート12、内部電極層7の電極パターンが形成されたシート11、中間内部電極層8の電極パターンが形成されたシート12、内部電極層7の電極パターンが形成されたシート11、中間内部電極層8の電極パターンが形成されたシート12、内部電極層7の電極パターンが形成されたシート11、中間内部電極層8の電極パターンが形成されたシート12、最外内部電極層9の電極パターンが形成されたシート13で構成されている。   Actually, the plurality of dielectric layers 6 in the element body 1 of the multilayer capacitor 100 are integrated to such an extent that the boundary between them cannot be visually recognized. As shown in FIG. 4, the element body 1 is formed by stacking and firing 10 ceramic green sheets and integrating them. Specifically, the ten ceramic green sheets are, in order from the top, the sheet 10 on which no electrode pattern is formed, the sheet 13 on which the electrode pattern of the outermost internal electrode layer 9 is formed, and the electrode of the intermediate internal electrode layer 8 Sheet 12 on which a pattern is formed, sheet 11 on which an electrode pattern of internal electrode layer 7 is formed, sheet 12 on which an electrode pattern of intermediate internal electrode layer 8 is formed, sheet 11 on which an electrode pattern of internal electrode layer 7 is formed The sheet 12 on which the electrode pattern of the intermediate internal electrode layer 8 is formed, the sheet 11 on which the electrode pattern of the internal electrode layer 7 is formed, the sheet 12 on which the electrode pattern of the intermediate internal electrode layer 8 is formed, the outermost internal electrode layer It is composed of a sheet 13 on which nine electrode patterns are formed.

各シート10〜13は、BaTiO、CaZrOなどを主成分として構成され、その厚さ、すなわち焼成後の誘電体層6の厚さは、6〜60μmとされている。各シート11〜13の電極パターンはNiやNi合金などの導電材を含んでおり、当該導電性材料を含む導電性ペーストの焼結体として構成される。 Each sheet 10 to 13 is configured such as BaTiO 3, CaZrO 3 as the main component, its thickness, i.e. the thickness of the dielectric layer 6 after firing, there is a 6~60Myuemu. The electrode patterns of the sheets 11 to 13 include a conductive material such as Ni or Ni alloy, and are configured as a sintered body of a conductive paste including the conductive material.

次に、内部電極層7の電極パターンおよび中間内部電極層8の電極パターンについて、図5および図6を参照しつつ説明する。   Next, the electrode pattern of the internal electrode layer 7 and the electrode pattern of the intermediate internal electrode layer 8 will be described with reference to FIGS.

図5に示すように、内部電極層7の電極パターンは、一対の内部電極20、30(第1の内部電極20および第2の内部電極30)によって構成されている。これらの内部電極20、30は、いずれもT字形状を有しており、所定長さだけ離間された状態で、シート11上において第1の端面1aと第2の端面1bとの対面方向に直交する方向(図のY方向)(以下、「幅方向」と称す。)に横断する中心線に関して線対称に配置されている。   As shown in FIG. 5, the electrode pattern of the internal electrode layer 7 includes a pair of internal electrodes 20 and 30 (a first internal electrode 20 and a second internal electrode 30). Each of these internal electrodes 20 and 30 has a T shape, and is separated from the first end surface 1a and the second end surface 1b on the sheet 11 in a state of being separated by a predetermined length. They are arranged symmetrically with respect to a center line that intersects in a direction orthogonal to the figure (Y direction in the figure) (hereinafter referred to as “width direction”).

第1の内部電極20は、素体1の第1の端面1a側に位置し、第1の端子電極2と電気的に接続されるとともに第1の端面1aから第2の端面1b側に延びている。第1の内部電極20は、第1の端面1aから遠い側に位置する活性電極部21と、活性電極部21より第1の端面1aに近い側に位置する引出電極部22とで構成されている。   The first internal electrode 20 is located on the first end face 1a side of the element body 1, is electrically connected to the first terminal electrode 2, and extends from the first end face 1a to the second end face 1b side. ing. The first internal electrode 20 includes an active electrode portion 21 located on the side far from the first end surface 1a, and an extraction electrode portion 22 located on the side closer to the first end surface 1a than the active electrode portion 21. Yes.

活性電極部21は、矩形形状を有し、幅方向における幅が一定幅w1となっている。引出電極部22も、矩形形状を有し、幅方向における幅が一定幅w2となっている。この引出電極部22の幅w2は、活性電極部21の幅w1よりも狭く(すなわち、w2<w1)設計されている。   The active electrode portion 21 has a rectangular shape, and the width in the width direction is a constant width w1. The extraction electrode part 22 also has a rectangular shape, and the width in the width direction is a constant width w2. The width w2 of the extraction electrode portion 22 is designed to be narrower than the width w1 of the active electrode portion 21 (that is, w2 <w1).

第2の内部電極30は、素体1の第2の端面1b側に位置し、第2の端子電極3と電気的に接続されるとともに第2の端面1bから第1の端面1a側に延びている。第2の内部電極30は、第2の端面1bから遠い側に位置する活性電極部31と、活性電極部31より第2の端面1bに近い側に位置する引出電極部32とで構成されている。   The second internal electrode 30 is located on the second end face 1b side of the element body 1, is electrically connected to the second terminal electrode 3, and extends from the second end face 1b to the first end face 1a side. ing. The second internal electrode 30 is composed of an active electrode part 31 located on the side far from the second end face 1b and an extraction electrode part 32 located on the side closer to the second end face 1b than the active electrode part 31. Yes.

活性電極部31は、第1の内部電極20の活性電極部21と同様の矩形形状を有し、かつ、活性電極部21と同幅の一定幅w1となっている。引出電極部32は、第1の内部電極20の引出電極部22と同様の矩形形状を有し、引出電極部22と同幅の一定幅w2となっている。   The active electrode portion 31 has a rectangular shape similar to that of the active electrode portion 21 of the first internal electrode 20, and has a constant width w <b> 1 that is the same width as the active electrode portion 21. The extraction electrode portion 32 has a rectangular shape similar to that of the extraction electrode portion 22 of the first internal electrode 20, and has a constant width w <b> 2 that is the same width as the extraction electrode portion 22.

図6に示すように、中間内部電極層8の電極パターンは、シート12の中央に配置された第3の内部電極40によって構成されている。第3の内部電極40は、第1の端子電極2および第2の端子電極3とは接続されておらず、これらの電極2、3のいずれとも電気的絶縁が図られている。また、第3の内部電極40は、矩形形状を有し、第1の端面1aと第2の端面1bとの対面方向に延びている。第3の内部電極40は、一定幅w3となっており、この幅w3は、第1の内部電極20および第2の内部電極30の活性電極部21、31の幅w1よりも広く(すなわち、w3>w1)設計されている。   As shown in FIG. 6, the electrode pattern of the intermediate internal electrode layer 8 is constituted by a third internal electrode 40 disposed in the center of the sheet 12. The third internal electrode 40 is not connected to the first terminal electrode 2 and the second terminal electrode 3, and both the electrodes 2 and 3 are electrically insulated. The third internal electrode 40 has a rectangular shape and extends in the facing direction between the first end surface 1a and the second end surface 1b. The third internal electrode 40 has a constant width w3, and this width w3 is wider than the width w1 of the active electrode portions 21 and 31 of the first internal electrode 20 and the second internal electrode 30 (that is, w3> w1) Designed.

この第3の内部電極40の延在方向における長さは、第1の内部電極20の活性電極部21および第2の内部電極30の活性電極部31を覆い、さらに、第1の内部電極20の引出電極部22の一部22aおよび第2の内部電極30の引出電極部32の一部32aに掛かる長さに設計されている。そのため、第3の内部電極40は、第1の内部電極20の活性電極部21および第2の内部電極30の活性電極部31に重畳し、かつ、第1の内部電極20の引出電極部22の一部22aおよび第2の内部電極30の引出電極部32の一部32aと重畳する。   The length in the extending direction of the third internal electrode 40 covers the active electrode portion 21 of the first internal electrode 20 and the active electrode portion 31 of the second internal electrode 30, and further, the first internal electrode 20 The length is designed to be applied to a part 22 a of the lead electrode part 22 and a part 32 a of the lead electrode part 32 of the second internal electrode 30. Therefore, the third internal electrode 40 overlaps with the active electrode portion 21 of the first internal electrode 20 and the active electrode portion 31 of the second internal electrode 30, and the extraction electrode portion 22 of the first internal electrode 20. And a part 32 a of the extraction electrode part 32 of the second internal electrode 30.

それにより、第3の内部電極40は、第1の内部電極20および第2の内部電極30との間で直列に接続された2つ容量成分を形成する。具体的には、第3の内部電極40は、第1の内部電極20と対向する対向領域において静電容量C1の容量成分を形成し、第2の内部電極30と対向する対向領域において静電容量C2の容量成分を形成し、これらの容量成分が直列に接続されて合成容量C(=C1×C2/(C1+C2))を形成する。   Thereby, the third internal electrode 40 forms two capacitance components connected in series between the first internal electrode 20 and the second internal electrode 30. Specifically, the third internal electrode 40 forms a capacitance component of the electrostatic capacitance C1 in the opposing region facing the first internal electrode 20, and electrostatically forms in the opposing region facing the second internal electrode 30. A capacitance component of the capacitance C2 is formed, and these capacitance components are connected in series to form a combined capacitance C (= C1 × C2 / (C1 + C2)).

また、第3の内部電極40の位置および寸法は、第1の内部電極20および第2の内部電極30の位置および寸法に対して、第1の内部電極20および第2の内部電極30の活性電極部21、31の幅方向における端部位置と第3の内部電極40の幅方向における端部位置との差d1が、第1の内部電極20(または第2の内部電極30)の活性電極部21(または活性電極部31)の延在方向の端部位置と第3の内部電極40の延在方向の端部位置との差d2よりも大きく(すなわち、d1>d2)設計されている。   The position and size of the third internal electrode 40 are different from the positions and sizes of the first internal electrode 20 and the second internal electrode 30 in terms of the activity of the first internal electrode 20 and the second internal electrode 30. The difference d1 between the end position in the width direction of the electrode portions 21 and 31 and the end position in the width direction of the third internal electrode 40 is the active electrode of the first internal electrode 20 (or the second internal electrode 30). Designed to be larger than the difference d2 between the end position in the extending direction of the portion 21 (or the active electrode section 31) and the end position in the extending direction of the third internal electrode 40 (that is, d1> d2). .

以上で説明した構成を有する積層コンデンサ100においては、内部電極層7と中間内部電極層8との間に幅方向(Y方向)に関する積層ズレが生じた場合、第1の内部電極20および第2の内部電極30の活性電極部21、31の幅w1よりも第3の内部電極40が幅広の形状(幅w3)を有するため、幅方向における端部位置の差d1の分だけ積層ズレを許容することができ、第3の内部電極40の幅方向に関する積層ズレに起因する静電容量の変化を抑えることができる。   In the multilayer capacitor 100 having the above-described configuration, when a misalignment in the width direction (Y direction) occurs between the internal electrode layer 7 and the intermediate internal electrode layer 8, the first internal electrode 20 and the second internal electrode 20 Since the third internal electrode 40 has a wider shape (width w3) than the width w1 of the active electrode portions 21 and 31 of the internal electrode 30, stacking deviation is allowed by the difference d1 in the end position in the width direction. It is possible to suppress the change in capacitance due to the stacking deviation in the width direction of the third internal electrode 40.

一方、図7に示す従来技術のように、第1の内部電極20’および第2の内部電極30’と、第3の内部電極40’とにおいて、幅方向における端部位置が一致する場合には、上記積層ズレも許容することができず、その結果、積層ズレに伴う対向面積の減少が生じて静電容量が大きく低減してしまう。   On the other hand, when the end positions in the width direction of the first internal electrode 20 ′, the second internal electrode 30 ′, and the third internal electrode 40 ′ are the same as in the prior art shown in FIG. However, the above-described stacking misalignment cannot be allowed, and as a result, the facing area is reduced due to the stacking misalignment, and the capacitance is greatly reduced.

また、内部電極層7と中間内部電極層8との間に延在方向(X方向)に関する積層ズレが生じた場合でも、第1の内部電極20と第2の内部電極30とが同幅w1の活性電極部21、31および同幅w2の引出電極部22、32を含むため、第3の内部電極40の延在方向に関する積層ズレに起因する静電容量の変化も抑えることができる。すなわち、延在方向に関する積層ズレにより、第1の内部電極20および第2の内部電極30のいずれか一方に、第3の内部電極40との対向面積の減少が生じた場合でも、他方の内部電極ではその減少した面積の分だけ対向面積が増加(補償)するため、静電容量の変化が効果的に抑制されている。   Even when a stacking shift in the extending direction (X direction) occurs between the internal electrode layer 7 and the intermediate internal electrode layer 8, the first internal electrode 20 and the second internal electrode 30 have the same width w1. Since the active electrode portions 21 and 31 and the extraction electrode portions 22 and 32 having the same width w2 are included, it is possible to suppress a change in capacitance due to the stacking deviation in the extending direction of the third internal electrode 40. In other words, even when a reduction in the area facing the third internal electrode 40 occurs in one of the first internal electrode 20 and the second internal electrode 30 due to the stacking deviation in the extending direction, the other internal In the electrode, the facing area increases (compensates) by the reduced area, so that the change in capacitance is effectively suppressed.

特に、引出電極部22、32の幅w2が活性電極部21、31の幅w1よりも狭いため、第3の内部電極40の延在方向に関する積層ズレの際に、第1の内部電極20と第3の内部電極40との対向面積および第2の内部電極30と第3の内部電極40との対向面積の変化が低減される。すなわち、引出電極部22、32の幅w2を活性電極部21、31の幅w1に対して幅狭化(w2<w1)することで、積層ズレ(たとえばΔlのズレ量)による対向面積の変化量(Δl×w2)が、幅狭化されていないときの対向面積の変化量(Δl×w1)に比べて効果的に低減されている。そのため、第1の内部電極20と第3の内部電極40とで形成される静電容量C1の変化量が低減されるとともに、第2の内部電極30と第3の内部電極40とで形成される静電容量C2の変化量が低減され、結果として、これらの合成容量Cの変化量も低減される。   In particular, since the width w2 of the extraction electrode portions 22 and 32 is narrower than the width w1 of the active electrode portions 21 and 31, the first internal electrode 20 and the third internal electrode 20 Changes in the facing area between the third internal electrode 40 and the facing area between the second internal electrode 30 and the third internal electrode 40 are reduced. That is, by changing the width w2 of the extraction electrode portions 22 and 32 to the width w1 of the active electrode portions 21 and 31 (w2 <w1), the change in the facing area due to stacking misalignment (for example, Δl misalignment). The amount (Δl × w2) is effectively reduced compared to the amount of change in the facing area (Δl × w1) when the width is not narrowed. Therefore, the amount of change in the capacitance C1 formed by the first internal electrode 20 and the third internal electrode 40 is reduced, and the second internal electrode 30 and the third internal electrode 40 are formed. As a result, the amount of change in the combined capacitance C is also reduced.

なお、図7に示す従来技術のように、第1の内部電極20’および第2の内部電極30’が延在方向に亘って均一幅であり、幅狭の引出電極部が形成されていない場合には、第3の内部電極40’の延在方向に関する積層ズレの際、引出電極部が狭小化されている上記態様に比べて対向面積の変化量が大きくなり、それにより合成容量Cが大きく変化してしまう。   As in the prior art shown in FIG. 7, the first internal electrode 20 ′ and the second internal electrode 30 ′ have a uniform width in the extending direction, and a narrow extraction electrode portion is not formed. In this case, the amount of change in the facing area becomes larger when the stacking misalignment in the extending direction of the third internal electrode 40 ′ is compared with the above-described aspect in which the extraction electrode portion is narrowed, and the combined capacitance C is thereby increased. It will change greatly.

以上で詳細に説明したように、積層コンデンサ100においては、積層ズレが生じた場合であっても、静電容量の変化を抑えることができるため、製品間における静電容量のばらつき低減が実現されている。   As described in detail above, in the multilayer capacitor 100, even if a multilayer deviation occurs, a change in capacitance can be suppressed, so that a variation in capacitance among products can be reduced. ing.

また、第1の内部電極20および第2の内部電極30においては、各引出電極部22、32の幅w2を各活性電極部21、31の幅w1よりも狭くすることで、素体1表面からの離隔化が図られている。そのため、素体1の第1の端面1aおよび第2の端面1bに第1の端子電極2および第2の端子電極3をめっき形成する際に、めっき液が素体1内に浸入しにくくなっており、めっき液の浸入による積層コンデンサ100の信頼性低下が抑制されている。   Moreover, in the 1st internal electrode 20 and the 2nd internal electrode 30, by making the width w2 of each extraction electrode part 22 and 32 narrower than the width w1 of each active electrode part 21 and 31, element body 1 surface The separation from is planned. Therefore, when the first terminal electrode 2 and the second terminal electrode 3 are formed on the first end surface 1 a and the second end surface 1 b of the element body 1 by plating, the plating solution is less likely to enter the element body 1. In addition, the reliability of the multilayer capacitor 100 due to the penetration of the plating solution is suppressed.

その上、図6に示すように、第1の内部電極20(または第2の内部電極30)と第3の内部電極40との位置関係に関し、幅方向に関する端部位置の差d1が、延在方向に関する端部位置との差d2よりも大きいため、第3の内部電極40の延在方向における積層ズレに比べて、幅方向における積層ズレに起因する静電容量の変化を効果的に抑えることができる。上述したとおり、延在方向に関する積層ズレは、第1の内部電極20および第2の内部電極30との間で対向面積が相互補償されるが、幅方向に関する積層ズレは、そのような対向面積の相互補償がないため、幅方向に関する積層ズレに対する許容長さ(d1)を長くすることが好ましい。   In addition, as shown in FIG. 6, regarding the positional relationship between the first internal electrode 20 (or the second internal electrode 30) and the third internal electrode 40, the difference d1 in the end position in the width direction is increased. Since it is larger than the difference d2 from the end position with respect to the current direction, it is possible to effectively suppress the change in capacitance caused by the stacking misalignment in the width direction compared to the stacking misalignment in the extending direction of the third internal electrode 40. be able to. As described above, in the stacking misalignment in the extending direction, the opposing area is mutually compensated between the first internal electrode 20 and the second internal electrode 30, but the stacking misalignment in the width direction is such an opposing area. Therefore, it is preferable to increase the allowable length (d1) with respect to the stacking deviation in the width direction.

図8に示すように、最外内部電極層9の電極パターンは、一対の最外内部電極50、60(第4の内部電極50および第5の内部電極60)によって構成されている。これらの内部電極50、60は、所定長さだけ離間された状態で、シート13上において幅方向に横断する中心線に関して線対称に配置されており、いずれも矩形形状を有している。第4の内部電極50および第5の内部電極60はいずれも、幅方向における幅が一定幅w4となっており、この幅w4は、第3の内部電極40の幅w3より広く(すなわち、w4>w3)設計されている。   As shown in FIG. 8, the electrode pattern of the outermost internal electrode layer 9 is constituted by a pair of outermost internal electrodes 50 and 60 (fourth internal electrode 50 and fifth internal electrode 60). These internal electrodes 50 and 60 are arranged in line symmetry with respect to a center line traversing in the width direction on the sheet 13 while being separated by a predetermined length, and both have a rectangular shape. Both the fourth internal electrode 50 and the fifth internal electrode 60 have a constant width w4 in the width direction, and this width w4 is wider than the width w3 of the third internal electrode 40 (that is, w4). > W3) Designed.

第4の内部電極50は、第1の内部電極20同様、素体1の第1の端面1a側に位置し、第1の端子電極2と電気的に接続されるとともに第1の端面1aから第2の端面1b側に延びている。第5の内部電極60は、第2の内部電極30同様、素体1の第2の端面1b側に位置し、第2の端子電極3と電気的に接続されるとともに第2の端面1bから第1の端面1a側に延びている。   Like the first internal electrode 20, the fourth internal electrode 50 is located on the first end face 1a side of the element body 1, and is electrically connected to the first terminal electrode 2 and from the first end face 1a. It extends to the second end face 1b side. Like the second internal electrode 30, the fifth internal electrode 60 is located on the second end face 1b side of the element body 1 and is electrically connected to the second terminal electrode 3 and from the second end face 1b. It extends to the first end face 1a side.

ここで、積層コンデンサ100の素体1の端面1a、1bに形成される端子電極2、3は、素体1内に形成された内部電極との間に、浮遊容量を形成する。特に、素体1の側面に回り込んだ部分の端子電極2、3と、第3の内部電極40との間で、浮遊容量が生じやすい。そのため、中間内部電極層8が、内部電極層7よりも素体1の積層方向における外側に位置する場合には、第1の端子電極2および第2の端子電極3と中間内部電極層8の第3の内部電極40との間で浮遊容量が生じてしまう。   Here, the terminal electrodes 2 and 3 formed on the end faces 1 a and 1 b of the element body 1 of the multilayer capacitor 100 form a stray capacitance between the terminal electrodes 2 and 3 and the internal electrodes formed in the element body 1. In particular, stray capacitance tends to occur between the portion of the terminal electrodes 2 and 3 that wrap around the side surface of the element body 1 and the third internal electrode 40. Therefore, when the intermediate internal electrode layer 8 is located outside the internal electrode layer 7 in the stacking direction of the element body 1, the first terminal electrode 2, the second terminal electrode 3, and the intermediate internal electrode layer 8 A stray capacitance is generated between the third internal electrode 40 and the third internal electrode 40.

そこで、積層コンデンサ100においては、最外内部電極層9を、素体1の最上層および最下層に配置することで、上記浮遊容量の抑制が図られている。すなわち、最外内部電極層9の内部電極50、60は、同じ極性の端子電極2、3と電気的に接続されているため、端子電極2、3との間に浮遊容量を生じさせず、より一層の製品間における静電容量ばらつきの低減が図られている。特に、第4の内部電極50および第5の内部電極60の幅w4が、第3の内部電極40の幅w3よりも広く設計されているため、端子電極2、3と第3の内部電極40との間に浮遊容量が生じる事態が効果的に抑制されている。   Therefore, in the multilayer capacitor 100, the stray capacitance is suppressed by disposing the outermost internal electrode layer 9 in the uppermost layer and the lowermost layer of the element body 1. That is, since the internal electrodes 50 and 60 of the outermost internal electrode layer 9 are electrically connected to the terminal electrodes 2 and 3 having the same polarity, no stray capacitance is generated between the terminal electrodes 2 and 3. Further, the variation in capacitance among products is reduced. In particular, since the width w4 of the fourth internal electrode 50 and the fifth internal electrode 60 is designed to be wider than the width w3 of the third internal electrode 40, the terminal electrodes 2, 3 and the third internal electrode 40 are designed. The situation in which stray capacitance occurs between the two is effectively suppressed.

100…積層コンデンサ、1…素体、1a…第1の端面、1b…第2の端面、2…第1の端子電極、3…第2の端子電極、6…誘電体層、7…内部電極層、8…中間内部電極層、9…最外内部電極層、20…第1の内部電極、21、31…活性電極部、22、32…引出電極部、30…第2の内部電極、40…第3の内部電極、50…第4の内部電極、60…第5の内部電極。   DESCRIPTION OF SYMBOLS 100 ... Multilayer capacitor, 1 ... Element body, 1a ... 1st end surface, 1b ... 2nd end surface, 2 ... 1st terminal electrode, 3 ... 2nd terminal electrode, 6 ... Dielectric layer, 7 ... Internal electrode Layer 8 ... intermediate internal electrode layer 9 ... outermost internal electrode layer 20 ... first internal electrode 21,31 ... active electrode part 22,32 ... extraction electrode part 30 ... second internal electrode 40 ... 3rd internal electrode, 50 ... 4th internal electrode, 60 ... 5th internal electrode.

Claims (2)

内部電極層と中間内部電極層とが誘電体層を介して交互に積層された素体を備える積層コンデンサであって、
前記素体の互いに対面する第1の端面および第2の端面には、第1の端子電極および第2の端子電極がそれぞれ設けられ、
前記内部電極層は、前記第1の端子電極と電気的に接続されるとともに前記第1の端面の側から前記第2の端面方向に延びる第1の内部電極と、前記第2の端子電極と電気的に接続されるとともに前記第2の端面の側から前記第1の端面方向に延びる第2の内部電極とを含み、
前記第1の内部電極および前記第2の内部電極がそれぞれ、端面から遠い側に位置する同幅の活性電極部と、前記活性電極部より幅狭であり、前記活性電極部より端面に近い側に位置する同幅の引出電極部とを含み、
前記中間内部電極層は、前記第1の端子電極および前記第2の端子電極のいずれとも接続されず、前記第1の内部電極および前記第2の内部電極との間で直列に接続された複数の容量成分を形成する第3の内部電極を含み、
前記第3の内部電極は、前記第1の内部電極の引出電極部の一部および前記第2の内部電極の引出電極部の一部と重畳するように、前記第1の端面と前記第2の端面との対面方向に延在し、かつ、前記第1の内部電極および前記第2の内部電極の前記活性電極部の幅よりも幅広の形状を有し、
前記第1の内部電極および前記第2の内部電極の前記活性電極部の幅方向における端部位置と、前記第3の内部電極の幅方向における端部位置との差が、
前記第1の内部電極または前記第2の内部電極の前記活性電極部の延在方向の端部位置と、前記第3の内部電極の延在方向の端部位置との差よりも大きい、積層コンデンサ。
A multilayer capacitor including an element body in which internal electrode layers and intermediate internal electrode layers are alternately stacked via dielectric layers,
A first terminal electrode and a second terminal electrode are respectively provided on the first end surface and the second end surface facing each other of the element body,
The internal electrode layer is electrically connected to the first terminal electrode and extends from the first end face side toward the second end face, and the second terminal electrode A second internal electrode that is electrically connected and extends in the first end face direction from the second end face side;
Each of the first internal electrode and the second internal electrode has an active electrode portion having the same width located on the side far from the end surface, and a side narrower than the active electrode portion and closer to the end surface than the active electrode portion And an extraction electrode portion of the same width located at
The intermediate internal electrode layer is not connected to any of the first terminal electrode and the second terminal electrode, and is connected in series between the first internal electrode and the second internal electrode. A third internal electrode forming a capacitive component of
The third internal electrode includes the first end face and the second end so as to overlap a part of the extraction electrode part of the first internal electrode and a part of the extraction electrode part of the second internal electrode. of extending in opposite direction of the end face, and have a wider shape than the width of the active electrode portion of the first internal electrode and the second internal electrode,
The difference between the end position in the width direction of the active electrode portion of the first internal electrode and the second internal electrode and the end position in the width direction of the third internal electrode is:
A stack that is larger than a difference between an end position in the extending direction of the active electrode portion of the first internal electrode or the second internal electrode and an end position in the extending direction of the third internal electrode. Capacitor.
複数の前記内部電極層のうち、前記素体の積層方向における最も外側に位置する前記内部電極層が、前記中間内部電極層よりも前記素体の積層方向における外側に位置する、請求項1に記載の積層コンデンサ。 Among the plurality of the internal electrode layers, the internal electrode layer positioned on the outermost side in the stacking direction of the element body, located outside in the stacking direction of the intermediate said body than the internal electrode layers, to claim 1 The multilayer capacitor described.
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