JP4623305B2 - Manufacturing method of laminated electronic component - Google Patents

Description

  The present invention relates to a method for manufacturing a laminated electronic component.

  In general, a multilayer electronic component such as a multilayer ceramic capacitor is manufactured by the following process. First, an internal electrode pattern made of a conductive paste is formed on a ceramic green sheet. Next, a plurality of ceramic green sheets having internal electrode patterns are laminated to form a sheet laminate. And after pressing a sheet | seat laminated body, it cut | disconnects to a several chip area | region, and a laminated chip is obtained. Furthermore, well-known processes such as binder removal, firing, and terminal electrode formation are performed on the multilayer chip to obtain a multilayer electronic component.

  In such a multilayer electronic component manufacturing process, the problem that the multilayer chip is deformed due to a step due to the thickness of the internal electrode pattern cannot be ignored. The deformed multilayer chip causes a mounting failure when the multilayer electronic component is mounted on the circuit board.

  Therefore, a technique is known in which a step absorption layer is formed by applying a ceramic paste around the internal electrode pattern on a ceramic green sheet to prevent the above-described deformation of the multilayer chip.

As an aspect of the step absorption layer, as disclosed in FIG. 15 of Patent Document 1, there is an aspect in which the step absorption layer is formed on the entire surface around the internal electrode pattern. However, in this aspect, the step absorption layer is formed in a larger area. When the step absorption layer is formed in a large area, the following problems occur.
(1) The area where the ceramic paste for the step absorption layer is applied also increases, which may increase the cost for forming the step absorption layer.
(2) When the sheet laminate is cut later, the distance for cutting the step absorption layer with the cutting blade is increased. For this reason, the load of a cutting blade increases and there exists a possibility that the lifetime of a cutting blade may become short.
(3) Since the area of the step absorption layer is large, it is difficult to apply high pressure to the step absorption layer in terms of unit area when the sheet laminate is pressed later. From the viewpoint of preventing delamination, it is preferable to apply a high pressure to the step absorption layer.
(4) When removing the laminated chip later, it is difficult to secure a route for exhausting the degassing gas.
JP-A-6-96991

  An object of the present invention is to provide a method for manufacturing a multilayer electronic component capable of preventing the deformation of the multilayer chip while minimizing the formation region of the step absorption layer.

  In order to solve the above-described problem, the present invention provides an internal electrode pattern and a step absorption layer formed in one chip region on a ceramic green sheet, and at least the ceramic green sheet on which the internal electrode pattern and the step absorption layer are formed. A method of manufacturing a laminated electronic component for producing a sheet laminate including one layer, wherein the step absorption is at least in a corner opposite to the lead-out portion of the internal electrode pattern in the one chip region on the ceramic green sheet. Provided is a method for manufacturing a laminated electronic component for forming a layer.

  In the method for manufacturing a laminated electronic component described above, an internal electrode pattern and a step absorption layer are formed in one chip region on a ceramic green sheet. Then, a sheet laminate including at least one ceramic green sheet on which the internal electrode pattern and the step absorption layer are formed is produced. After pressing this sheet laminate, it is cut into a plurality of one-chip regions to obtain a laminated chip.

  An important feature of the present invention is that a step-absorbing layer is formed at least in the corner opposite to the lead-out portion of the internal electrode pattern in one chip region on the ceramic green sheet. The inventors have examined that the step absorption layer formed in the corner on the side opposite to the lead portion of the internal electrode pattern in one chip region effectively works as a region for preventing the deformation of the multilayer chip. I understood. Therefore, deformation of the multilayer chip can be prevented while minimizing the formation region of the step absorption layer on the ceramic green sheet.

  In one embodiment, the step absorption layer is formed on the ceramic green sheet at the intersection of the planned cutting lines determined based on one chip region.

  In another embodiment, step absorption layers are formed at four corners of one chip region on the ceramic green sheet.

  In yet another embodiment, the step absorbing layer is formed on the ceramic green sheet in a region excluding the cutting margin width of the planned cutting line determined based on one chip region.

  As described above, according to the present invention, it is possible to provide a method for manufacturing a multilayer electronic component capable of preventing the deformation of the multilayer chip while minimizing the formation region of the step absorption layer.

  Hereinafter, an embodiment of a method for manufacturing a multilayer electronic component according to the present invention will be described. First, the multilayer electronic component will be described.

  FIG. 1 is a schematic cross-sectional view showing an example of a laminated electronic component to which the laminated electronic component manufacturing method according to the present invention can be applied. The illustrated multilayer electronic component includes a ceramic substrate 1 and n layers of internal electrodes 21 to 2n. In the illustrated embodiment, the manufacturing method according to the present invention is applied to a multilayer ceramic capacitor, but may be applied to other multilayer electronic components such as inductors.

  The ceramic substrate 1 is made of, for example, a dielectric material mainly composed of barium titanate. The ceramic substrate 1 has a substantially rectangular parallelepiped shape having a length direction X, a width direction Y, and a thickness direction Z. Terminal electrodes 41 and 42 are provided on both end surfaces 160 and 170 of the ceramic substrate 1 as viewed in the length direction X.

  The internal electrodes 21 to 2 n are made of a conductive material such as Cu or Ni, and are laminated inside the ceramic base 1 with a gap in the thickness direction Z. Specifically, the internal electrodes 21 to 2n are arranged by alternately shifting the positions viewed in the length direction X, and are alternately drawn to both end surfaces 160 and 170 of the ceramic substrate 1.

  More specifically, the internal electrode 21 has a rectangular shape having a length direction X and a width direction Y when viewed in plan, and one side viewed in the length direction X is drawn out to the end face 160 of the ceramic substrate 1. Are connected to the terminal electrode 41. The other side viewed in the length direction X is spaced from the other end face 170 of the ceramic substrate 1 in the length direction X.

  The next internal electrode 22 also has a rectangular shape having a length direction X and a width direction Y when viewed in plan, and one side viewed in the length direction X is spaced from the end surface 160 of the ceramic substrate 1 in the length direction X. The other side viewed in the length direction L is drawn out to the end face 170 of the ceramic substrate 1 and connected to the terminal electrode 42. The same applies to the remaining internal electrodes 23-2n.

Next, a method for manufacturing such a multilayer electronic component will be described.
FIG. 2 is a diagram illustrating an embodiment of a method for manufacturing a multilayer electronic component according to the present invention. Referring to FIG. 2, a ceramic green sheet (unfired ceramic sheet) 11 is shown. The ceramic green sheet 11 is made of a ceramic paste in which ceramic powder, a solvent, a binder, and the like are mixed, and has a certain thickness. The ceramic green sheet 11 is attached to a support (not shown) such as a flexible plastic film.

  Next, as shown in FIG. 2, the internal electrode pattern 20 is formed in a plurality of one-chip regions Q <b> 1 set on the ceramic green sheet 11. In the illustrated embodiment, each of the internal electrode patterns 20 has a rectangular shape having a length direction X and a width direction Y, and one internal electrode pattern 20 is provided for each of two one chip regions Q1 adjacent to each other in the length direction X. The internal electrode pattern 20 is formed. Furthermore, in the illustrated embodiment, a plurality of internal electrode pattern rows in which the internal electrode patterns 20 are aligned in the length direction X are provided, and the internal electrode pattern rows adjacent in the width direction Y are viewed in the length direction X. Are arranged in an aligned manner. That is, the internal electrode patterns 20 are arranged in a matrix along the length direction X and the width direction Y.

  The one-chip region Q1 is a region for forming the laminated component shown in FIG. 1, and each of the planned cutting lines C1 and C2 along the length direction X and the planned cutting line C3 along the width direction Y. , C4. The planned cutting line C1 passes between adjacent internal electrode pattern rows in the width direction Y. Similarly, the planned cutting line C2 also passes between adjacent internal electrode pattern rows in the width direction Y. The planned cutting line C <b> 3 extends across the internal electrode pattern 20. The planned cutting line C4 extends between the internal electrode patterns 20 adjacent in the length direction X.

  FIG. 3 is an enlarged view showing one chip region Q1 shown in FIG. Referring to FIG. 3, one chip region Q1 includes two sides 61 and 62 in the length direction X given by the planned cutting lines C1 and C2, and two sides 63 in the width direction Y given by the planned cutting lines C3 and C4. 64. Further, the one chip region Q1 is located at a position where the corners 51, 61 and 63 meet, the corner 51 where the edges 62, 63 meet, and the corner 52, where the edges 61, 64 meet. And a corner 54 located at a position where the sides 62 and 64 meet.

  In the internal electrode pattern 20, the sides 201 and 202 on both sides viewed in the width direction Y are spaced from the sides 61 and 62 of the one chip region Q1, and the one side 204 viewed in the length direction X is one chip region Q1. It arrange | positions in the aspect spaced apart from the edge | side 64 of this. The lead portion 205 of the internal electrode pattern 20 is in contact with the side 63 of the one chip region Q1.

  The internal electrode pattern 20 can be formed by printing a conductor paste mixed with conductor powder, a solvent, a binder, and the like in a predetermined pattern. Examples of the printing method include screen printing, gravure printing, and offset printing. The layer thickness of the internal electrode pattern 20 is set to 1 μm, for example.

  Next, as shown in FIG. 2, the step absorption layer 31 is formed on the ceramic green sheet in such a manner as to straddle the intersection of the planned cutting lines C <b> 1 and C <b> 2 and the planned cutting line C <b> 4.

  Referring to FIG. 3, when viewed in one chip region Q <b> 1, the step absorption layer 31 is formed at corners 53 and 54 on the opposite side of the lead part 205 of the internal electrode pattern 20. For example, the corner portion 53 will be described representatively. The step absorption layer 31 has a length that is closer to the cutting line C1 than the line L1 extending the side 201 of the internal electrode pattern 20 in the width direction Y. When viewed in the direction X, it is formed closer to the planned cutting line C4 than the line L4 obtained by extending the side 204 of the internal electrode pattern 20. The step absorption layer 31 has a quadrilateral shape in which two sides in the length direction X straddle the planned cutting line C4 and two sides in the width direction Y straddle the planned cutting line C1.

  The step absorption layer 31 can be formed by printing a ceramic paste in a predetermined pattern. Examples of the printing method include screen printing, gravure printing, and offset printing. The step absorption layer 31 is basically composed of a ceramic paste having the same configuration as the ceramic green sheet 11. In addition, the layer thickness of the step absorption layer 31 is preferably set to substantially the same value as the layer thickness of the internal electrode pattern 20, but may be set to a different value.

  In the present embodiment, the step absorption layer 31 is formed after the internal electrode pattern 20 is formed, but the temporal order relationship between the formation of the internal electrode pattern 20 and the formation of the step absorption layer 31 is arbitrary. For example, the internal electrode pattern may be formed after the step absorption layer is formed, or the internal electrode pattern and the step absorption layer may be formed simultaneously.

  Next, a sheet laminate including at least one ceramic green sheet 11 on which the internal electrode pattern 20 and the step absorption layer 31 are formed is manufactured. Specifically, a sheet laminate in which a plurality of ceramic green sheets 11 on which the internal electrode pattern 20 and the step absorption layer 31 are formed is laminated. More specifically, a plurality of ceramic green sheets 11 are laminated in such a manner that the positions of the internal electrode patterns 20 viewed in the length direction X are alternately shifted and the positions of the internal electrode patterns 20 viewed in the width direction Y are aligned. .

  As a method for producing the sheet laminate, a method of preparing a plurality of ceramic green sheets 11 including the internal electrode pattern 20 and the step absorption layer 31 and sequentially laminating these ceramic green sheets 11 is adopted. it can. In addition, it is also possible to adopt a technique for producing a sheet laminate by repeating the ceramic green sheet forming process, the internal electrode pattern and the step absorption layer printing process, etc. on the flexible support as many times as necessary. it can.

  Moreover, in this embodiment, the aspect which laminated | stacked the ceramic green sheet 11 in which the internal electrode pattern 20 and the level | step difference absorption layer 31 were formed is employ | adopted as an aspect of a sheet | seat laminated body, It is not limited to an aspect. For example, as an aspect of the sheet laminated body, in addition to the ceramic green sheet 11 in which the internal electrode pattern 20 and the step absorption layer 31 are formed, the ceramic green sheet having no step absorption layer even if the internal electrode pattern is provided is laminated. An aspect can also be employ | adopted.

  Next, a pressure treatment is performed on the sheet laminate obtained in this manner. Specifically, the sheet laminate is pressurized at least in the laminating direction. Examples of such pressurizing treatment include a die press and pressurization by isotropic hydrostatic pressure.

  Next, the sheet laminate is cut into a plurality of one-chip regions Q1. Specifically, the cutting along the length direction X may be performed according to the planned cutting lines C1 and C2, and the cutting along the width direction Y may be performed according to the planned cutting lines C3 and C4.

  When the sheet laminate is cut in this manner, a laminated chip is obtained. The laminated chip is subjected to a binder removal process for removing the binder and fired under predetermined conditions. When terminal electrodes are formed on the fired laminated chip, the laminated electronic component shown in FIG. 1 is obtained.

  As described above, in the manufacturing process of the laminated electronic component, the problem of deformation such as a rounded shape of the laminated chip due to a step due to the thickness of the internal electrode pattern cannot be ignored.

  In the present invention, as described with reference to FIG. 3, the step absorbing layer 31 is formed in the corners 53 and 54 on the opposite side of the lead portion 205 of the internal electrode pattern 20 in the one chip region Q1 on the ceramic green sheet 11. Form. The step absorption layer 31 formed at the corners 53 and 54 effectively functions as a region for preventing the above-described deformation of the laminated chip. Therefore, it is possible to prevent the deformation of the multilayer chip while reducing the formation region of the step absorption layer on the ceramic green sheet 11 as much as possible.

Furthermore, the following effects can be obtained by reducing the formation region of the step absorption layer.
(1) Since the area for applying the ceramic paste for the step absorption layer is reduced, the cost for forming the step absorption layer can be reduced.
(2) When cutting a sheet laminated body, the distance which cut | disconnects a level | step difference absorption layer with a cutting blade becomes small. Thereby, the load of a cutting blade can be reduced and the lifetime of a cutting blade can be extended.
(3) Since the area of the step absorption layer is small, it becomes easy to apply a high pressure to the step absorption layer in terms of the unit area when the sheet laminate is pressed later. From the viewpoint of preventing delamination, it is preferable to apply a high pressure to the step absorption layer.
(4) When the binder removal process is performed on the multilayer chip, it is easy to secure a path for exhausting the degassing gas.

  Further, in FIG. 3, the step absorption layer 31 is formed at the intersection of the planned cutting lines C1 and C2 and the planned cutting line C4. According to such an aspect of forming the step absorption layer 31, the effect of preventing the deformation of the laminated chip can be enhanced.

  FIG. 4 is a diagram for explaining another embodiment of the method for manufacturing a multilayer electronic component according to the present invention, and FIG. 5 is an enlarged view of one chip region Q1 shown in FIG. In this embodiment, the description of the same points as those of the embodiment shown in FIGS. 2 and 3 is omitted.

  Referring to FIG. 4, in this embodiment, in addition to forming the step absorption layer 31 at the intersection of the planned cutting lines C1, C2 and the planned cutting line C4, the cutting planned lines C1, C2 and the planned cutting line C3 A step absorption layer 32 is also formed at the intersection. Specifically, the step absorption layer 32 is formed in such a manner as to straddle the intersection of the planned cutting lines C1 and C2 and the planned cutting line C3.

  Referring to FIG. 5, when viewed in one chip region Q <b> 1, the step absorption layer 32 is formed at the corners 51 and 52 on the same side as the lead portion 205 of the internal electrode pattern 20. The shape, formation method, material, layer thickness, and the like of the step absorption layer 32 are basically the same as those of the step absorption layer 31 described above.

  In this embodiment, as shown in FIG. 5, in addition to forming the step absorption layer 31 in the corners 53 and 54 on the opposite side of the lead part 205 of the internal electrode pattern 20 in one chip region Q1, the lead part 205 The step absorption layer 32 is formed in the corners 51 and 52 on the same side. That is, since the step absorption layers 31 and 32 are formed at the four corners 51 to 54 of the one chip region Q1, the effect of preventing the deformation of the multilayer chip can be enhanced.

  FIG. 6 is a diagram for explaining still another embodiment of the method for manufacturing a laminated electronic component according to the present invention. In this embodiment, a description of the same points as those of the embodiment shown in FIGS. 4 and 5 is omitted.

  In the embodiment shown in FIG. 6, the step absorption layers 31 and 32 are formed in such a manner that the corner portions 51 to 54 of the one-chip region Q1 occupy a fan-shaped region. When viewed at the intersection of the planned cutting line, the step absorption layers 31 and 32 are formed in a circular shape having a center on the intersection of the planned cutting line. For example, the intersection of the planned cutting lines C1 and C4 will be described as a representative example. The step absorption layer 31 is formed in a circular shape having a center on the intersection of the planned cutting lines C1 and C4.

  FIG. 7 is a diagram for explaining still another embodiment of the method for manufacturing a laminated electronic component according to the present invention. In this embodiment, a description of the same points as those of the embodiment shown in FIGS. 4 and 5 is omitted.

  In the embodiment shown in FIG. 7, in addition to forming the step absorption layers 31 and 32 at the four corners 51 to 54 of the one chip region Q1, the step absorption layer 33 is also formed at the center of the side of the one chip region Q1. Form. Specifically, in the center of the side 61 connecting the corners 51, 53, the center of the side 62 connecting the corners 52, 54, and the center of the side 64 connecting the corners 53, 54 of one chip region Q 1. A step absorption layer 33 is formed. According to this aspect, the effect of preventing the deformation of the laminated chip can be further enhanced.

  FIG. 8 is a view for explaining still another embodiment of the method for manufacturing a laminated electronic component according to the present invention. In this embodiment, a description of the same points as those of the embodiment shown in FIG. 7 is omitted.

  In the embodiment shown in FIG. 8, the step absorption layers 31 and 32 are formed in such a manner that the corner portions 51 to 54 of the one-chip region Q1 occupy a triangular region. When viewed at the intersection of the planned cutting line, the step absorption layers 31 and 32 have two vertices facing the length direction X on one cutting planned line and the two vertices facing the width direction Y on the other cutting planned line. It is formed in a quadrangular shape. For example, the intersection of the planned cutting lines C1 and C4 will be described representatively. In the step absorption layer 31, the two vertices whose two vertices facing the length direction X are on the planned cutting line C1 and facing the width direction Y are shown. Is formed in a square shape on the planned cutting line C4. The remaining step absorption layer 33 is also formed in a square shape.

  FIG. 9 is a diagram for explaining still another embodiment of the method for manufacturing a laminated electronic component according to the present invention. In this embodiment, a description of the same points as those of the embodiment shown in FIGS. 4 and 5 is omitted.

  In the case of the embodiment shown in FIG. 9, the step absorbing layers 31 and 32 are formed in a region on the ceramic green sheet 11 excluding the cutting margin widths of the planned cutting lines C1 to C4. For example, the step absorption layer 31 is formed in a form excluding the cutting margin width W1 of the planned cutting line C1 and the cutting margin width W4 of the planned cutting line C4 when viewed at the intersection of the planned cutting lines C1 and C4. The same applies to the other intersections of the planned cutting line.

  As shown in FIG. 9, according to the aspect in which the step absorption layers 31 and 32 are formed in the region excluding the cutting margin width of the planned cutting lines C <b> 1 to C <b> 4 on the ceramic green sheet 11, The location where the step absorption layers 31 and 32 are cut in the cutting process can be reduced. Therefore, the load on the cutting blade can be reduced and the life of the cutting blade can be extended.

  FIG. 10 is a diagram for explaining still another embodiment of the method for manufacturing a laminated electronic component according to the present invention. In this embodiment, a description of the same points as those of the embodiment shown in FIGS. 4 and 5 is omitted.

  As shown in FIG. 10, the step absorption layers 31 and 32 may be formed in a form spaced from the side in the length direction X at the corners 51 to 54 of the one chip region Q1. The step absorption layers 31 and 32 are not necessarily in contact with the sides in the length direction X. For example, the step-absorbing layer 31 formed at the corner 53 will be described as a representative example. The step-absorbing layer 31 is formed in such a manner that the gap 61 in the width direction Y is separated from the side 61 in the length direction X. In addition, unlike the illustrated embodiment, the step absorption layer can be formed in a manner in which the interval in the length direction X is separated from the side in the width direction Y at the corner.

  FIG. 11 is a diagram illustrating still another embodiment of the method for manufacturing a laminated electronic component according to the present invention. In this embodiment, a description of the same points as those of the embodiment shown in FIGS. 4 and 5 is omitted.

  As shown in FIG. 11, the step absorption layers 31 and 32 may be formed in a manner spaced from the side in the length direction X and the side in the width direction Y at the corners 51 to 54 of one chip region Q1. . For example, the step absorption layer 31 formed at the corner 53 will be described as a representative. The step absorption layer 31 is separated from the side 61 by a distance d1 in the width direction Y and from the side 64 by a distance d4 in the length direction X. Are formed in a separated manner.

  FIG. 12 is a diagram illustrating still another embodiment of the method for manufacturing a laminated electronic component according to the present invention. In this embodiment, a description of the same points as those of the embodiment shown in FIGS. 4 and 5 is omitted.

  As shown in FIG. 12, the internal electrode pattern 20 is formed in a plurality of one-chip regions Q1 set on the ceramic green sheet 11. In the present embodiment, a plurality of rows of internal electrode patterns in which the internal electrode patterns 20 are aligned in the length direction X are provided, and the positions of the plurality of internal electrode pattern rows in the length direction X are shifted from each other. Deploy.

  One chip region Q1 is defined by planned cutting lines C1 and C2 along the length direction X and planned cutting lines C3 and C4 along the width direction Y. In the present embodiment, the planned cutting line C3 passes between the internal electrode patterns 20 for one internal electrode pattern row, and straddles the internal electrode 20 for another internal electrode pattern row adjacent to the internal electrode pattern row. The planned cutting line C4 is also the same as the planned cutting line C3.

  An enlarged view of one chip region Q1 in the present embodiment is the same as FIG.

  Thereafter, the steps of forming the step absorption layers 31 and 32 are the same as those in the embodiment shown in FIGS. Other points, for example, the production, pressurization, and cutting of the sheet laminate are the same as those in the embodiment shown in FIGS.

  In addition, the arrangement | positioning of the level | step difference absorption layer shown by other embodiment can also be combined with arrangement | positioning of the internal electrode pattern shown by embodiment of FIG. For example, there is an embodiment in which the arrangement of the internal electrode pattern shown in the embodiment of FIG. 12 is combined with the aspect of the step absorption layer shown in the embodiment of FIG.

  Needless to say, any combination exists between the embodiments described above.

It is typical sectional drawing which shows an example of the multilayer electronic component which can apply the manufacturing method of the multilayer electronic component which concerns on this invention. It is a figure explaining one Embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. FIG. 3 is an enlarged view showing one chip area Q1 shown in FIG. 2. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. FIG. 5 is an enlarged view of one chip region Q1 shown in FIG. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention. It is a figure explaining another embodiment of the manufacturing method of the multilayer electronic component which concerns on this invention.

Explanation of symbols

11 Ceramic green sheet Q1 One chip area 20 Internal electrode pattern 31-33 Step absorption layer

Claims (7)

A method for producing a laminated electronic component comprising a step of laminating and cutting a plurality of ceramic green sheets ,
The ceramic green sheet includes an internal electrode pattern and a plurality of first step absorption layers on one surface,
The internal electrode pattern has a rectangular shape having a length direction and a width direction, a plurality are arranged in a matrix along the length direction and the width direction, and the rows along the length direction are: The rows adjacent in the width direction are aligned with the positions seen in the length direction,
Each of the first step absorption layers includes two internal electrode patterns included in the row along the length direction, and two internal electrode patterns adjacent to the two internal electrode patterns in the width direction. And is formed for each region surrounded by the four closest corners,
The plurality of first step absorption layers are independent from each other.
Production method. The method of manufacturing a laminated electronic component according to claim 1, wherein the ceramic green sheet further includes a cutting line.
The planned cutting line defines a plurality of sections in the region,
The first step absorption layer is present in each of the plurality of sections.
Production method. A process for the preparation of a multilayer electronic component according to claim 1 or 2, further wherein the ceramic green sheet comprises a second step absorption layer,
The second step absorption layer is formed independently of the first step absorption layer in a region where the long sides of the adjacent internal electrode patterns face each other.
Production method. A method for manufacturing a laminated electronic component according to claim 3,
The ceramic green sheet has a first planned cutting line, a second planned cutting line, and a third planned cutting line,
The first planned cutting line extends between the long sides of the adjacent internal electrode patterns,
The second planned cutting line extends between the short sides of the adjacent internal electrode patterns, and intersects the first planned cutting line in the region surrounded by the four corners. ,
The third planned cutting line is parallel to the second planned cutting line and extends across an intermediate portion of the long side of the internal electrode pattern,
The first step absorption layer is formed on an intersection of the first planned cutting line and the second planned cutting line,
The second step absorption layer is formed on an intersection of the first planned cutting line and the third planned cutting line.
Production method. A method for manufacturing a laminated electronic component according to claim 3,
The ceramic green sheet has a first planned cutting line, a second planned cutting line, and a third planned cutting line,
The first planned cutting line extends between the long sides of the adjacent internal electrode patterns,
The second planned cutting line extends between the short sides of the adjacent internal electrode patterns, and intersects the first planned cutting line in the region surrounded by the four corners. ,
The third planned cutting line is parallel to the second planned cutting line and extends across an intermediate portion of the long side of the internal electrode pattern,
The first step absorption layer is formed in a region that does not overlap a cutting allowance width of the first planned cutting line and that does not overlap a cutting allowance width of the second planned cutting line. ,
The second step absorption layer is formed in a region that does not overlap with a cutting margin width of the first planned cutting line and that does not overlap with a cutting margin width of the third planned cutting line. ,
Production method. A method for manufacturing a laminated electronic component according to any one of claims 1 to 5,
The first step absorption layer is made of a ceramic paste.
Production method. A method for manufacturing a laminated electronic component according to claim 1,
The first step absorption layer is outside a line extending a pair of long sides constituting the internal electrode pattern and outside a line extending a pair of short sides constituting the internal electrode pattern. Formed,
Production method.

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