JP2005208449A - Display device and driving method for display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such problems that, if power source lines and grounding lines are commonly wired to a plurality of systems, the noise of the pulses to drive another system is liable to enter one system and a sharpness defect occurs due to the noise and the wobble of the respective potentials of the power source lines and the grounding lines accompanying the noise. <P>SOLUTION: The active matrix type liquid crystal display device of a point sequential driving system is so constituted that the power source lines 41, 43, 45 and the grounding lines 42, 44 and 46 to apply a power source potential VDD and a grounding potential GND to vertical driving circuits 12A and 12B, a horizontal driving circuit 13 and a precharge circuit 14 are independently wired to each of the vertical driving circuits 12A and 12B, the horizontal driving circuit 13 and the precharge circuit 14. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device and a display device driving method, and more particularly to a display device in which pixels including electro-optic elements are two-dimensionally arranged in a matrix and a driving method of the display device.

  In a display device in which pixels including electro-optical elements are two-dimensionally arranged in a matrix, for example, a liquid crystal display device using a liquid crystal cell as an electro-optical element, a signal wired for each column of a matrix array of pixels When writing a video signal to a line, it is known that when the charge / discharge current due to the writing of the video signal is large, vertical streak noise due to the charge / discharge current appears on the display screen.

  In order to suppress the charge / discharge current due to the writing of the video signal as much as possible, in an active matrix type liquid crystal display device of a dot sequential driving method in which the video signal is written in units of pixels, a predetermined signal is written in advance before writing the video signal to the signal line. A configuration including a precharge circuit for writing a level precharge signal to a signal line is employed (see, for example, Patent Document 1).

  Thus, by writing the precharge signal in advance before writing the video signal to the signal line, the signal level when writing the video signal can be reduced, and the charge / discharge current when writing the video signal can be reduced. Since it can be suppressed, the occurrence of vertical streak noise can be suppressed. The writing of the precharge signal is performed, for example, for each pixel row (for each line) in which the video signal is written in the horizontal blanking period (hereinafter, this method is referred to as “line sequential precharge method”).

  The precharge circuit has a vertical drive circuit for selecting each pixel of a pixel array unit in which pixels are arranged in a matrix in units of rows, and a signal line for pixels in a row selected by the vertical drive circuit. And a peripheral drive circuit such as a horizontal drive circuit for writing a video signal through the pixel array section on the same substrate (liquid crystal panel) as the pixel array section. At that time, the horizontal drive circuit and the precharge circuit are arranged separately on the upper and lower sides with the pixel array portion interposed therebetween. For the vertical drive circuit, for example, two systems are arranged on both the left and right sides of the pixel array portion.

  The vertical drive circuit and the horizontal drive circuit have a circuit configuration based on, for example, a shift register. The shift register is configured by a combination of inverter circuits, for example. On the other hand, the horizontal drive circuit performs an operation based on the horizontal cycle, whereas the vertical drive circuit and the precharge circuit perform an operation based on the vertical cycle. Therefore, the power supply line and the ground (GND) line are generally configured so that they are separately wired for those related to the horizontal drive system and those other than that (related to the vertical drive system and the precharge system). It is.

JP 2002-333869 A

  In the liquid crystal display device having the above configuration, the power supply line and the ground line particularly related to the vertical drive system and the precharge system constitute an inverter circuit of a shift register, which is a basic circuit of the vertical drive circuit, or constitute a precharge circuit. It will be wired to many transistors. Then, when a pulse for driving the vertical drive circuit is given to these many transistors, it is pulled by a sudden level change at the rise or fall of the pulse, as shown in the waveform diagram of FIG. In addition, potential fluctuations occur in the power supply line and the ground line. Further, under the influence of the charge / discharge noise of the transistor, the fluctuation of the potential occurs in the power supply line and the ground line due to the noise.

  These potential fluctuations adversely affect the operation of the vertical drive circuit. For example, when considering a case where the potential of the ground line is constantly swinging to a potential higher than 0 [V] and the power supply line is constantly lower than a desired potential, the waveform of the pulse for driving the vertical drive circuit is lifted from the GND level. Because of the waveform, the shift register constituting the vertical drive circuit may cause a malfunction in the worst case, specifically, pulse shaping may not be performed during the shift operation.

  In recent years, liquid crystal display devices with higher definition and higher image quality have been desired, and there is a demand for a liquid crystal display device of 3 million pixel class such as QXGA (H: 2048 × V: 1536) as a graphics display standard. It has come out. In this way, as the number of pixels increases, the vertical blanking period of the video format is shortened accordingly. As an example, XGA (H: 1024 × V: 768) has a vertical blanking period of about 4.0 μsec, whereas QXGA has a very short vertical blanking period of about 1.5 μsec.

  On the other hand, in the line-sequential precharge method in which the precharge signal is written for each pixel row in which the video signal is written in the vertical blanking period, the signal lines for the number of horizontal pixels are written and driven at a time, and the load is very heavy. Therefore, it is necessary to secure a precharge time of about 1.5 μsec before completing the precharge. However, in the liquid crystal display device of the 3 million pixel class, as described above, the vertical blanking period becomes very short, and therefore, a line sequential precharge method in which a precharge signal is written for each pixel row in the vertical blanking period is adopted. I can't do that.

  Therefore, in an active matrix type liquid crystal display device with a multi-pixel dot sequential drive method such as QXGA, a dot sequential precharge method for writing a precharge signal prior to the writing of the video signal is written for each pixel to which the video signal is written. I have to adopt it. In the sequential precharge method, a precharge signal is written for each signal line, and the load becomes very light. Therefore, the precharge time is as short as about 100 nsec.

  In order to employ the dot sequential precharge method, the precharge circuit is also configured using a shift register as in the horizontal drive circuit. As a result, as described above, if the power supply line and the ground line are wired in common to the vertical drive system and the precharge system, the noise of the pulse driving the other system enters the vertical drive system or the precharge system. It becomes easy to cause an image quality defect due to the noise and fluctuations of the power supply potential (power supply line and ground line potentials) associated therewith.

  The present invention has been made in view of the above-mentioned problems, and the object of the present invention is to make the vertical drive system, the horizontal drive system, and the precharge system contain only noise of pulses for driving them. Accordingly, it is an object of the present invention to provide a display device and a driving method thereof capable of suppressing image quality defects caused by the noise and accompanying power supply potential fluctuation.

  In order to achieve the above object, according to the present invention, a pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix, and a first driving unit that selects pixels in the pixel array unit in units of rows, A second driving means for writing a video signal in pixel units to pixels in a row selected by the first driving means; and a predetermined signal at a timing different from the writing timing of the video signal by the second driving means. In a display device comprising third driving means for writing in units, first and second power supply lines are wired independently to each of the first driving means, the second driving means, and the third driving means. The first and second power supply lines supply power.

  In the display device having the above-described configuration, the first and second power supply lines for applying the first and second power supply potentials to the first drive means, the second drive means, and the third drive means are the first drive means, Since each of the two driving means and the third driving means is wired independently, each of the first driving means, the second driving means, and the third driving means receives only noise of a pulse for driving the respective driving means. In addition, fluctuations in the potentials of the first and second power supply lines due to the noise can be minimized.

  According to the present invention, each of the first drive means, the second drive means, and the third drive means contains only the noise of the pulse that drives each of them, and the fluctuation of the power supply potential accompanying the noise is minimized. Therefore, it is possible to suppress image quality defects due to noise and fluctuations in the power supply potential.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing an outline of the configuration of the display device according to the first embodiment of the present invention. Here, a dot sequential drive type active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel will be described as an example. As is apparent from FIG. 1, the active matrix liquid crystal display device according to the present embodiment includes a pixel array unit 11, two vertical drive circuits 12A and 12B as first drive means, and horizontal drive as second drive means. A circuit 13 and a precharge circuit 14 as third driving means are provided.

  In the pixel array unit 11, pixels 20 including liquid crystal cells as electro-optical elements are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (not shown), and m rows of the pixels 20 are arranged. The scanning lines 15-1 to 15-m are wired for every row in the arrangement of n columns, and the signal lines 16-1 to 16-n are wired for every column. The first glass substrate is disposed opposite to the second glass substrate with a predetermined gap, and a liquid crystal material is sealed between the second glass substrate to constitute a liquid crystal panel.

  The pixel 20 includes a pixel transistor, for example, a TFT (Thin Film Transistor) 21, a liquid crystal cell 22 having a pixel electrode connected to the drain electrode of the TFT 21, and a storage capacitor having one electrode connected to the drain electrode of the TFT 21. 23. Here, the liquid crystal cell 22 means a liquid crystal capacitance generated between a pixel electrode and a counter electrode formed opposite to the pixel electrode.

  The TFT 21 has a gate electrode connected to the scanning line 15 (15-1 to 15-m) and a source electrode connected to the signal line 16 (16-1 to 16-n). Further, for example, the counter electrode of the liquid crystal cell 22 and the other electrode of the storage capacitor 23 are connected to the common line 17 in common for each pixel. A common voltage (counter electrode voltage) Vcom is applied to the common electrode of the liquid crystal cell 22 via the common line 17.

  The vertical drive circuits 12A and 12B, the horizontal drive circuit 13, and the precharge circuit 14 are arranged on the same substrate (liquid crystal panel) as the pixel array unit 11, for example, and are positive power supply potentials higher than the voltage necessary for driving the liquid crystal The operation is performed using VDD as the first power supply potential, for example, the ground potential (0 [V]) GND as the second power supply potential.

  The two vertical drive circuits 12A and 12B are arranged on both the left and right sides with the pixel array unit 11 in between. Here, the vertical drive circuits 12A and 12B are arranged on both the left and right sides of the pixel array unit 11. However, a configuration in which one vertical drive circuit 12 is arranged only on one of the left and right sides of the pixel array unit 11 may be adopted. Is possible. The vertical drive circuit 12A includes a shift register 121, buffer circuits 122-1 to 122-m, and the like. Similarly to the vertical drive circuit 12A, the vertical drive circuit 12B includes a shift register 123, buffer circuits 124-1 to 124-m, and the like.

  In the shift registers 121 and 123, a vertical start pulse VST and a vertical clock pulse VCK (generally, clock pulses VCK and VCKX having opposite phases to each other) are supplied to level shift (L / S) circuits 31 and 32 and a buffer circuit 33. , 34. The level shift circuits 31 and 32 level shift (level convert) the vertical start pulse VST and the vertical clock pulse VCK having a logic level (about 5 [V] or less) to an amplitude voltage necessary for driving the liquid crystal. The level-shifted vertical start pulse VST and vertical clock pulse VCK are applied to the shift registers 121 and 123 via the buffer circuits 33 and 34, respectively.

  The shift registers 121 and 123 are configured by, for example, a combination of inverter circuits, start a shift operation in response to the vertical start pulse VST, and sequentially shift the vertical start pulse VST in synchronization with the vertical clock pulse VCK. The transfer pulses transferred at each transfer stage (shift stage) are sequentially output as scan pulses V1 to Vm. The scanning pulses V1 to Vm are applied to the scanning lines 15-1 to 15-m of the pixel array unit 11 through the buffer circuits 122-1 to 122-m and 124-1 to 124-m, thereby causing the pixels 20 to pass through. Select by units.

  The horizontal drive circuit 13 includes a shift register 131, sampling switches 132-1 to 132-n, and the like. The shift register 131 is supplied with a horizontal start pulse HST and a horizontal clock pulse HCK (generally, clock pulses HCK and HCKX having phases opposite to each other) via the level shift circuit 35 and the buffer circuit 36. The level shift circuit 35 level-shifts the horizontal start pulse HST and the horizontal clock pulse HCK at the logic level to an amplitude voltage necessary for driving the liquid crystal. The level-shifted horizontal start pulse HST and horizontal clock pulse HCK are supplied to the shift register 131 via the buffer circuit 36.

  The shift register 131 is configured by, for example, a combination of inverter circuits, starts a shift operation in response to the horizontal start pulse HST, and sequentially shifts the horizontal start pulse HST in synchronization with the horizontal clock pulse HCK, thereby transferring each transfer. The transfer pulses transferred at the stages are sequentially output as sampling pulses H1 to Hn. Sampling pulses H1 to Hn are sequentially supplied to sampling switches 132-1 to 132-n.

  One end of each of the sampling switches 132-1 to 132-n is connected in common to the video line 18 to which the video signal Vsig is input, and the other end is each one end of the signal lines 16-1 to 16-n of the pixel array unit 11. Are connected to each. These sampling switches 132-1 to 132-n are turned on (closed) in response to the sampling pulses H1 to Hn, and sequentially sample the video signal Vsig inputted through the video line 18, thereby the video signal Vsig. Are written to the signal lines 16-1 to 16-n. That is, it is possible to realize dot-sequential driving in which the video signal Vsig is written in units of pixels for each pixel 20 in the pixel row selected by the vertical driving circuits 12A and 12B.

  The precharge circuit 14 includes a shift register 141, precharge switches 142-1 to 142-n, and the like. A precharge start pulse PST and a precharge clock pulse PCK (generally, clock pulses PCK and PCKX having phases opposite to each other) are supplied to the shift register 141 via a level shift circuit 37 and a buffer circuit 38. The level shift circuit 141 level-shifts the precharge start pulse PST and the precharge clock pulse PCK at the logic level to the amplitude voltage necessary for driving the liquid crystal.

  The level-shifted precharge start pulse PST and precharge clock pulse PCK are supplied to the shift register 141 via the buffer circuit 38. Here, the precharge start pulse PST and the precharge clock pulse PCK are pulses slightly advanced in phase with respect to the horizontal start pulse HST and the horizontal clock pulse HCK.

  The shift register 141 is configured by, for example, a combination of inverter circuits, starts a shift operation in response to the precharge start pulse PST, and sequentially shifts the precharge start pulse PST in synchronization with the precharge clock pulse PCK. The transfer pulses transferred at each transfer stage are sequentially output as precharge pulses P1 to Pn. Precharge pulses P1 to Pn are sequentially applied to precharge switches 142-1 to 142-n.

  One end of each of the precharge switches 142-1 to 142-n is connected in common to a precharge line 19 to which a precharge signal Psig of a predetermined level is input, and each other end is connected to a signal line 16-1 to 16-1 of the pixel array unit 11. It is connected to each other end of 16-n. These precharge switches 142-1 to 142-n are turned on in response to the precharge pulses P1 to Pn, and sequentially sample the precharge signal Psig input through the precharge line 19, whereby the precharge switches 142-1 to 142-n are turned on. The signal Psig is written to the signal lines 16-1 to 16-n. That is, for each pixel 20 in the pixel row selected by the vertical drive circuits 12A and 12B, dot-sequential precharge is performed in which the precharge signal Psig is written in units of pixels before the video signal Vsig is written in units of pixels. it can.

  In the point-sequential drive type active matrix liquid crystal display device having the above configuration, in this embodiment, the vertical drive circuits 12A and 12B, the horizontal drive circuit 13 and the precharge circuit 14 are supplied with the power supply potential VDD and the ground potential GND (first and first potentials). The first power supply line and the second power supply line for supplying the second power supply potential are independently wired to the vertical drive circuits 12A and 12B, the horizontal drive circuit 13, and the precharge circuit 14, respectively.

  That is, the vertical drive system, that is, the vertical drive circuits 12A and 12B, the level shift circuit 31 and the buffer circuit 32 are supplied with the power supply potential VDD by the power supply line 41 and the ground potential GND by the ground line 42. The horizontal drive system, that is, the horizontal drive circuit 13, the level shift circuit 33, and the buffer circuit 34 is supplied with the power supply potential VDD by the power supply line 43 and supplied with the ground potential GND by the ground line 44. The precharge system, that is, the precharge circuit 14, the level shift circuit 35, and the buffer circuit 36 are supplied with the power supply potential VDD through the power supply line 45 and supplied with the ground potential GND through the ground line 46. The ground lines 42, 44, 46 are also a kind of power supply line.

  As described above, the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 for supplying the power supply potential VDD and the ground potential GND to the vertical drive circuits 12A, 12B, the horizontal drive circuit 13, and the precharge circuit 14 are vertically driven. By adopting a configuration in which the circuits 12A and 12B, the horizontal drive circuit 13, and the precharge circuit 14 are independently wired, the following operational effects can be obtained.

  First, when pulses for driving them, for example, start pulses VST, HST, PST, are given to the vertical drive circuits 12A, 12B, horizontal drive circuit 13, and precharge circuit 14, when the start pulses VST, HST, PST rise. Alternatively, it is pulled by a sudden level change at the time of falling, and as shown in the waveform diagram of FIG. 2, potential fluctuations occur in the power supply lines 41, 43, 45 and the ground lines 42, 44, 46. Further, under the influence of the charge / discharge noise of the transistors constituting the shift registers 121, 123, 131, 141, potential fluctuations occur in the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 due to the noises. .

  Thus, the noise of the pulses that drive the vertical drive circuits 12A and 12B, the horizontal drive circuit 13 and the precharge circuit 14, or the potentials of the power supply lines 41, 43 and 45 and the ground lines 42, 44 and 46 associated with the noises. Even if shaking occurs, the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 are wired independently for each drive system, so that the vertical drive circuits 12A, 12B, the horizontal drive circuit 13, and the precharge circuit 14 are provided. Each of these includes only noise of a pulse for driving each of them, and fluctuations in the potentials of the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 due to the noise can be minimized. Therefore, the noise of the pulses for driving the vertical drive circuits 12A and 12B, the horizontal drive circuit 13 and the precharge circuit 14, or the fluctuations in the potentials of the power supply lines 41, 43 and 45 and the ground lines 42, 44 and 46 due to the noise. The resulting image quality defect can be suppressed.

  Even if image quality failure occurs, the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 are independent of each of the vertical drive circuits 12A, 12B, the horizontal drive circuit 13, and the precharge circuit 14. Therefore, noise of pulses for driving the vertical drive circuits 12A and 12B, the horizontal drive circuit 13 and the precharge circuit 14, or fluctuations in potentials of the power supply lines 41, 43 and 45 and the ground lines 42, 44 and 46 due to the noise. It is possible to easily analyze in which power supply line and ground line the cause of the image quality failure caused by.

[Second Embodiment]
FIG. 3 is a block diagram showing an outline of the configuration of a display device according to the second embodiment of the present invention. In FIG. 3, the same parts as those in FIG. In this embodiment, a dot sequential drive type active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel will be described as an example. FIG. 3 mainly shows power supply lines 41, 43, 45 and ground lines 42, 44, 46 of the vertical drive circuits 12A, 12B, the horizontal drive circuit 13, and the precharge circuit 14.

  In FIG. 3, the pixel array unit 11, the vertical drive circuits 12A and 12B, the horizontal drive circuit 13, and the precharge circuit 14 have basically the same configuration as that of the liquid crystal display device according to the first embodiment. In addition, they are integrally disposed on the same substrate (liquid crystal panel) 40. Further, the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 are independently wired to the vertical drive circuits 12A, 12B, the horizontal drive circuit 13, and the precharge circuit 14, respectively. This is the same as the case of the liquid crystal display device according to the first embodiment.

  As described above, in the active matrix type liquid crystal display device having the same basic configuration as that of the liquid crystal display device according to the first embodiment, in the present embodiment, the vertical drive is provided at the end of the substrate (liquid crystal panel) 50. Power terminal 51 and ground terminal 52 (first terminal pair), power terminal 53 and ground terminal 54 (second terminal pair), horizontal drive power terminal 55 and ground terminal 56 (first terminal pair), A power terminal 57 and a ground terminal 58 (second terminal pair), a precharge power terminal 59 and a ground terminal 60 (first terminal pair), a power terminal 61 and a ground terminal 62 (second terminal pair) are connected. Both ends of the power line 41 and the ground line 42 are connected to the power terminals 51 and 53 and the ground terminals 52 and 54, and both ends of the power line 43 and the ground line 44 are connected to the power terminals 55 and 56 and The terminal 57 and 58, is characterized in that it has connected to the ends of the power supply line 45 and ground line 46 to power supply terminals 59, 60 and ground terminals 61 and 62.

  Here, considering the case where only one end of each of the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 is connected to the power supply terminal and the ground terminal and the other ends are opened, the power supply lines 41, 43 are considered. , 45 and the wiring resistance R of the ground lines 42, 44, 46 increase in accordance with the distance from the power supply terminal and the ground terminal. On the other hand, fluctuations in the potentials of the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 are determined by the parasitic capacitance C and the wiring resistance R attached to the power supply lines 41, 43, 45 and the ground lines 42, 44, 46. Accordingly, the potential fluctuation is larger on the other end side than the one end side (power supply terminal and ground terminal side) on the power supply lines 41, 43, 45 and the ground lines 42, 44, 46. , 45 and the ground lines 42, 44, 46 cannot be held at a stable potential.

  On the other hand, by connecting the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 to the power supply terminal and the ground terminal at both ends, respectively, the maximum value of the wiring resistance R of these lines can be increased only at one end. Compared to the case of connecting to the terminal and the ground terminal, it can be almost halved. As a result, the maximum value of the potential fluctuation on the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 can be reduced to about half, so that the power supply lines 41, 43, 45 and the ground lines 42, 44, The potential of 46 can be maintained at a stable potential. As a result, noise of pulses for driving the vertical drive circuits 12A and 12B, the horizontal drive circuit 13 and the precharge circuit 14, or fluctuations in potentials of the power supply lines 41, 43 and 45 and the ground lines 42, 44 and 46 due to the noise. Therefore, it is possible to more reliably suppress image quality defects caused by the image quality.

  In the active matrix type liquid crystal display device according to the present embodiment having the above configuration, the power supply lines 41, 43, 45 and the ground lines 42, 44, 46 are connected to the power supply terminal and the ground terminal at both ends. However, the connection is not limited to both ends, and particularly for a line having a long wiring length, such as the power supply line 41 and the ground line 42 of the vertical drive system, the power supply terminal and the ground are further connected in the middle of the wiring. By connecting to the terminal, the potential of the power supply line and the ground line can be held at a more stable potential.

  As described above, the power line 41 and the ground line 42 of the vertical drive system have an advantage that the number of terminals (number of pins of the IC) can be reduced by wiring in common to the vertical drive circuits 12A and 12B. However, it is not always necessary to wire them in common. Power lines and ground lines are wired independently to the vertical drive circuits 12A and 12B, and are connected to power terminals and ground terminals at least at both ends of each power line and ground line. It is also possible to adopt a configuration to do so. Thereby, although the number of terminals is increased, the potentials of the power supply line and the ground line of the vertical drive system can be held at a more stable potential.

  In each of the above embodiments, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as an electro-optical element of the pixel has been described as an example. However, the present invention is not limited to this application example, and the pixel The present invention can be applied to all display devices in which pixels including electro-optical elements are two-dimensionally arranged in a matrix, such as an organic EL display device using organic EL (electro luminescence) elements as electro-optical elements.

  Further, in each of the above embodiments, as the third driving unit, the precharge circuit 14 that writes the precharge signal Psig at a predetermined level in advance in units of pixels prior to the writing of the video signal Vsig by the horizontal drive circuit 13 is used. As described above by way of example, the present invention is not limited to the precharge circuit 14, and any structure may be used as long as a predetermined signal is written in units of pixels at a timing different from the video signal Vsig writing timing by the horizontal drive circuit 13.

  The dot matrix driving type active matrix liquid crystal display device according to the present embodiment can be used as a general video display device, and for example, as a liquid crystal light valve in a projection type liquid crystal display device (liquid crystal projector device). be able to.

1 is a block diagram showing an outline of a configuration of a dot sequential drive type active matrix liquid crystal display device according to a first embodiment of the present invention. It is a wave form diagram which shows the mode of the fluctuation | variation of the electric potential of the power supply line and ground line resulting from a pulse. It is a block diagram which shows the outline of a structure of the dot-sequential drive system active matrix type liquid crystal display device concerning 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel array part, 12A, 12B ... Vertical drive circuit, 13 ... Horizontal drive circuit, 14 ... Precharge circuit, 15, 15-1 to 15-m ... Scan line, 16, 16-1 to 16-n ... Signal Line 18, video line 19, precharge line, 20 pixel, 21 TFT (thin film transistor), 22 liquid crystal cell, 23 holding capacitor 31, 32, 35, 37 level shift circuit 33, 34, 36, 38 ... buffer circuit, 41, 43, 45 ... power supply line, 42, 42, 44 ... ground line

Claims (7)

A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
First driving means for selecting pixels of the pixel array section in units of rows;
Second driving means for writing a video signal in pixel units to pixels in a row selected by the first driving means;
Third driving means for writing a predetermined signal in a pixel unit at a timing different from the writing timing of the video signal by the second driving means;
A display device, comprising: first and second power supply lines that are independently wired to each of the first drive means, the second drive means, and the third drive means. 2. The display device according to claim 1, wherein the third driving unit writes a precharge signal of a predetermined level in units of pixels in advance before the video signal is written by the second driving unit. The first driving means, the second driving means and the third driving means are disposed on the same substrate,
A first terminal pair to which one end of each of the first power supply line and the second power supply line is connected to an end portion of the substrate for each of the first drive means, the second drive means, and the third drive means. And a second terminal pair to which the other ends of the first and second power lines are connected. The display device according to claim 1, wherein: Two first driving means are disposed on both sides of the pixel array portion,
The display device according to claim 1, wherein the first and second power supply lines are wired in common to the two first drive units. The display device according to claim 4, wherein the first and second power supply lines are connected to the third terminal pair in the middle of the wiring. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
First driving means for selecting pixels of the pixel array section in units of rows;
Second driving means for writing a video signal in pixel units to pixels in a row selected by the first driving means;
A driving method for a display device, comprising: third driving means for writing a predetermined signal in units of pixels at a timing different from the writing timing of the video signal by the second driving means,
A method of driving a display device, comprising: supplying power through first and second power lines independently wired to each of the first driving means, the second driving means, and the third driving means. . The display device driving method according to claim 6, wherein the third driving unit writes a precharge signal of a predetermined level in advance in units of pixels prior to the writing of the video signal by the second driving unit.

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