JP2005197685A - ダブル・ゲートFinFET設計のための自動層生成法および装置 - Google Patents
ダブル・ゲートFinFET設計のための自動層生成法および装置 Download PDFInfo
- Publication number
- JP2005197685A JP2005197685A JP2004370239A JP2004370239A JP2005197685A JP 2005197685 A JP2005197685 A JP 2005197685A JP 2004370239 A JP2004370239 A JP 2004370239A JP 2004370239 A JP2004370239 A JP 2004370239A JP 2005197685 A JP2005197685 A JP 2005197685A
- Authority
- JP
- Japan
- Prior art keywords
- design
- fin
- hierarchy level
- structures
- next higher
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013461 design Methods 0.000 title claims abstract description 174
- 238000000034 method Methods 0.000 title claims abstract description 90
- 230000008859 change Effects 0.000 claims description 3
- 238000004590 computer program Methods 0.000 claims 2
- 230000001131 transforming effect Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000005669 field effect Effects 0.000 abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 4
- 150000004706 metal oxides Chemical class 0.000 abstract description 4
- 230000000295 complement effect Effects 0.000 abstract description 2
- 230000007704 transition Effects 0.000 abstract 1
- 230000008569 process Effects 0.000 description 31
- 238000010586 diagram Methods 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 125000006850 spacer group Chemical group 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000012545 processing Methods 0.000 description 6
- 238000009966 trimming Methods 0.000 description 6
- 230000002457 bidirectional effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 125000001475 halogen functional group Chemical group 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009291 secondary effect Effects 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 210000004690 animal fin Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002071 nanotube Substances 0.000 description 1
- SNICXCGAKADSCV-UHFFFAOYSA-N nicotine Chemical compound CN1CCCC1C1=CC=CN=C1 SNICXCGAKADSCV-UHFFFAOYSA-N 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000010076 replication Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Ceramic Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
【解決手段】セル構造「A」とセル構造「B」の配置を含むが、以前に生成されたフィンをセル構造「A」およびセル構造「B」が含まない、対応するセル構造「C」512。この設計階層で起こるセル構造「A」とセル構造「B」の他のセル構造への任意の配置の結合を考える。フィン生成ツールは、この階層のセル構造「A」およびセル構造「B」にフィンを配置しないと判断する。フィン生成は上の階層に委任され、したがって円によって指示されるように段のない結合フィン形状560。
【選択図】図24
Description
502’ セル構造「A」
504’ セル構造「B」
505 ゲート
508 結合構造「C」
510’ 結合前のゲート領域
512 セル構造「C」
515 ゲート
540 結合フィン形状
550 セル構造「A」/「B」結合領域
560 結合フィン形状
Claims (17)
- フィン形構造を含み、少なくとも2つの設計階層レベルを含むハードウェア設計を、前記設計を生成するときに満たされるべき少なくとも1つのデザイン・ルールに基づいて生成する方法であって、現在の設計階層レベルにおいて所与の設計が前記少なくとも1つのデザイン・ルールに違反している場合に、前記デザイン・ルールの前記違反が回避されるように前記所与の設計を変更するために、前記現在の設計階層レベルから次に高い設計階層レベルに移る方法。
- 前記次に高い設計階層レベルが、フィン形構造のより大きな連続領域を含む、請求項1に記載の方法。
- 前記所与の設計を変更する前記ステップが、少なくとも1つのフィン配置の変更を含む、請求項1または2に記載の方法。
- 前記少なくとも1つのデザイン・ルールが、2つのフィン形構造間のオーバラップ領域のフィン・トポロジ、または近接したフィン形構造間の他の任意の干渉を含む、請求項1ないし3のいずれかに記載の方法。
- フィン形構造の生成前には機能上互いに独立している第1のセル構造と第2のセル構造とを、所与の設計階層レベルにおいて組み立てるために、前記フィン形構造を生成する前に、次に高い設計階層レベルに移り、前記次に高い設計階層レベルで前記フィン形構造を生成し、前記第1のセル構造と第2のセル構造の結合されたフィン形状構造を得る、請求項1ないし4のいずれかに記載の方法。
- 既存の非フィン形ハードウェア設計を、少なくとも2つの設計階層レベルを含む対応するフィン形ハードウェア設計に、前記設計を生成するときに満たされるべき少なくとも1つのデザイン・ルールに基づいて変換する方法であって、現在の設計階層レベルにおいて所与の設計が前記少なくとも1つのデザイン・ルールに違反している場合に、前記デザイン・ルールの前記違反が回避されるように前記所与の設計を変更するために、前記現在の設計階層レベルから次に高い設計階層レベルに移る方法。
- 前記次に高い設計階層レベルが、フィン形構造のより大きな連続領域を含む、請求項6に記載の方法。
- 前記所与の設計を変更する前記ステップが、少なくとも1つのフィン配置の変更を含む、請求項6または7に記載の方法。
- フィン形構造の生成前には機能上互いに独立している第1のセル構造と第2のセル構造とを、所与の設計階層レベルにおいて組み立てるために、前記フィン形構造を生成する前に、次に高い設計階層レベルに移り、前記次に高い設計階層レベルで前記フィン形構造を生成し、前記第1のセル構造と第2のセル構造の結合されたフィン形状構造を得る、請求項6ないし8のいずれかに記載の方法。
- ディジタル・コンピュータの内部メモリに格納されたコンピュータ・プログラム製品であって、前記製品が前記コンピュータ上で実行されたときに請求項1ないし9のいずれかに記載の方法を実行するプログラム・コード部分を含むコンピュータ・プログラム製品。
- フィン形構造を含み、少なくとも2つの設計階層レベルを含むハードウェア設計を生成するフィン形ハードウェア設計を、前記設計を生成するときに満たされるべき少なくとも1つのデザイン・ルールに基づいて設計し生成する装置であって、現在の設計階層レベルにおいて所与の設計が前記少なくとも1つのデザイン・ルールに違反している場合に、前記デザイン・ルールの前記違反が回避されるように前記所与の設計を変更するために、前記現在の設計階層レベルから次に高い設計階層レベルに移る装置。
- 前記次に高い設計階層レベルが、フィン形構造のより大きな連続した領域を含む、請求項11に記載の装置。
- 前記所与の設計を変更する前記ステップが、少なくとも1つのフィン配置の変更を含む、請求項11または12に記載の装置。
- 前記少なくとも1つのデザイン・ルールが、2つのフィン形構造間のオーバラップ領域のフィン・トポロジ、または近接したフィン形構造間の他の任意の干渉(interference)を含む、請求項11ないし13のいずれかに記載の装置。
- 既存の非フィン形ハードウェア設計を、少なくとも2つの設計階層レベルを含む対応するフィン形ハードウェア設計に、前記設計を生成するときに満たされるべき少なくとも1つのデザイン・ルールに基づいて変換する装置であって、現在の設計階層レベルにおいて所与の設計が前記少なくとも1つのデザイン・ルールに違反している場合に、前記デザイン・ルールの前記違反が回避されるように前記所与の設計を変更するために、前記現在の設計階層レベルから次に高い設計階層レベルに移る装置。
- 前記次に高い設計階層レベルが、フィン形構造のより大きな連続領域を含む、請求項15に記載の装置。
- 前記所与の設計を変更する前記ステップが、少なくとも1つのフィン配置の変更を含む、請求項15または16に記載の装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03104921 | 2003-12-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005197685A true JP2005197685A (ja) | 2005-07-21 |
JP4215712B2 JP4215712B2 (ja) | 2009-01-28 |
Family
ID=34673627
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004370239A Expired - Fee Related JP4215712B2 (ja) | 2003-12-22 | 2004-12-21 | フィン形状の生成方法及び装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7315994B2 (ja) |
JP (1) | JP4215712B2 (ja) |
KR (1) | KR100702552B1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008060219A (ja) * | 2006-08-30 | 2008-03-13 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2009509344A (ja) * | 2005-09-19 | 2009-03-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 高密度のシェブロンfinFET及びそれを製造する方法 |
CN103187296B (zh) * | 2011-12-31 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
JP2018064125A (ja) * | 2013-08-23 | 2018-04-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
JP2018064126A (ja) * | 2013-09-04 | 2018-04-19 | 株式会社ソシオネクスト | 半導体装置 |
Families Citing this family (91)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1047298C (zh) * | 1994-07-08 | 1999-12-15 | Acta株式会社 | 筷子 |
US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
US7905021B2 (en) | 2005-08-10 | 2011-03-15 | Kamran Shirazi | International dining kit |
US7491594B2 (en) * | 2005-10-26 | 2009-02-17 | Freescale Semiconductor, Inc. | Methods of generating planar double gate transistor shapes |
US7530037B2 (en) * | 2005-10-26 | 2009-05-05 | Freescale Semiconductor, Inc. | Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods |
KR100763330B1 (ko) * | 2005-12-14 | 2007-10-04 | 삼성전자주식회사 | 활성 핀들을 정의하는 소자분리 방법, 이를 이용하는반도체소자의 제조방법 및 이에 의해 제조된 반도체소자 |
US9009641B2 (en) * | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US7908578B2 (en) * | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US7956421B2 (en) * | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US7838948B2 (en) * | 2007-01-30 | 2010-11-23 | Infineon Technologies Ag | Fin interconnects for multigate FET circuit blocks |
US7812373B2 (en) * | 2007-02-12 | 2010-10-12 | Infineon Technologies Ag | MuGFET array layout |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US7898037B2 (en) * | 2007-04-18 | 2011-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact scheme for MOSFETs |
US8237201B2 (en) * | 2007-05-30 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout methods of integrated circuits having unit MOS devices |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
WO2009116015A1 (en) * | 2008-03-20 | 2009-09-24 | Nxp B.V. | Finfet transistor with high-voltage capability and cmos-compatible method for fabricating the same |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US20090283829A1 (en) * | 2008-05-13 | 2009-11-19 | International Business Machines Corporation | Finfet with a v-shaped channel |
JP5599395B2 (ja) | 2008-07-16 | 2014-10-01 | テラ イノヴェイションズ インコーポレイテッド | 動的アレイアーキテクチャにおけるセル位相整合及び配置の方法及びその実施 |
US9122832B2 (en) * | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8305829B2 (en) * | 2009-02-23 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same |
US8305790B2 (en) * | 2009-03-16 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical anti-fuse and related applications |
US8957482B2 (en) | 2009-03-31 | 2015-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
US8912602B2 (en) | 2009-04-14 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US8461015B2 (en) | 2009-07-08 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI structure and method of forming bottom void in same |
US8298925B2 (en) | 2010-11-08 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
US8623728B2 (en) | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
US8440517B2 (en) | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
US8497528B2 (en) | 2010-05-06 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
US8629478B2 (en) | 2009-07-31 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure for high mobility multiple-gate transistor |
US8114721B2 (en) * | 2009-12-15 | 2012-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of controlling gate thickness in forming FinFET devices |
US8759943B2 (en) | 2010-10-08 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor having notched fin structure and method of making the same |
US8472227B2 (en) | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
US9484462B2 (en) | 2009-09-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of fin field effect transistor |
US8482073B2 (en) | 2010-03-25 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including FINFETs and methods for forming the same |
US8980719B2 (en) | 2010-04-28 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
US8264032B2 (en) | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
US8187928B2 (en) | 2010-09-21 | 2012-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuits |
US8264021B2 (en) * | 2009-10-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfets and methods for forming the same |
US8202780B2 (en) * | 2009-07-31 | 2012-06-19 | International Business Machines Corporation | Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions |
US8383503B2 (en) * | 2009-08-05 | 2013-02-26 | GlobalFoundries, Inc. | Methods for forming semiconductor structures using selectively-formed sidewall spacers |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US20110097867A1 (en) * | 2009-10-22 | 2011-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of controlling gate thicknesses in forming fusi gates |
US8813014B2 (en) | 2009-12-30 | 2014-08-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for making the same using semiconductor fin density design rules |
US8621398B2 (en) * | 2010-05-14 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Automatic layout conversion for FinFET device |
US8881084B2 (en) * | 2010-05-14 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET boundary optimization |
US8659072B2 (en) | 2010-09-24 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Series FinFET implementation schemes |
US8603924B2 (en) | 2010-10-19 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming gate dielectric material |
US9048181B2 (en) | 2010-11-08 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8816444B2 (en) | 2011-04-29 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US8621406B2 (en) | 2011-04-29 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US8799833B2 (en) * | 2011-04-29 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US8726220B2 (en) | 2011-04-29 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US8586482B2 (en) | 2011-06-29 | 2013-11-19 | International Business Machines Corporation | Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation |
US8580692B2 (en) | 2011-06-29 | 2013-11-12 | International Business Machines Corporation | Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation |
WO2013106799A1 (en) * | 2012-01-13 | 2013-07-18 | Tela Innovations, Inc. | Circuits with linear finfet structures |
KR101904417B1 (ko) | 2012-03-30 | 2018-10-08 | 삼성전자주식회사 | 반도체 집적 회로 및 그 설계 방법 |
US8741701B2 (en) | 2012-08-14 | 2014-06-03 | International Business Machines Corporation | Fin structure formation including partial spacer removal |
KR101953240B1 (ko) | 2012-09-14 | 2019-03-04 | 삼성전자 주식회사 | 핀 트랜지스터 및 이를 포함하는 반도체 집적 회로 |
US8766363B2 (en) * | 2012-11-07 | 2014-07-01 | International Business Machines Corporation | Method and structure for forming a localized SOI finFET |
US8716094B1 (en) | 2012-11-21 | 2014-05-06 | Global Foundries Inc. | FinFET formation using double patterning memorization |
US9158879B2 (en) * | 2013-09-04 | 2015-10-13 | Globalfoundries Inc. | Color-insensitive rules for routing structures |
US9054192B1 (en) * | 2013-12-20 | 2015-06-09 | International Business Machines Corporation | Integration of Ge-containing fins and compound semiconductor fins |
US9633906B2 (en) | 2014-01-24 | 2017-04-25 | International Business Machines Corporation | Gate structure cut after formation of epitaxial active regions |
US9196612B2 (en) | 2014-03-26 | 2015-11-24 | International Business Machines Corporation | Semiconductor device including merged-unmerged work function metal and variable fin pitch |
TWI633451B (zh) * | 2014-06-04 | 2018-08-21 | 聯華電子股份有限公司 | 平面設計至非平面設計之轉換方法 |
US9263586B2 (en) | 2014-06-06 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure |
US9431383B2 (en) | 2014-07-22 | 2016-08-30 | Samsung Electronics Co., Ltd. | Integrated circuit, semiconductor device based on integrated circuit, and standard cell library |
KR101958421B1 (ko) * | 2014-07-22 | 2019-03-14 | 삼성전자 주식회사 | 집적 회로, 상기 집적 회로에 따른 반도체 소자 및 표준 셀 라이브러리 |
KR20160013698A (ko) | 2014-07-28 | 2016-02-05 | 삼성전자주식회사 | 레이아웃 디자인 시스템, 레이아웃 디자인 방법 및 레이아웃 디자인 방법을 수행하기 위한 프로그램을 포함하는 컴퓨터로 판독 가능한 기록매체 |
US9852252B2 (en) | 2014-08-22 | 2017-12-26 | Samsung Electronics Co., Ltd. | Standard cell library and methods of using the same |
US9418896B2 (en) | 2014-11-12 | 2016-08-16 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
US9496399B2 (en) * | 2015-04-02 | 2016-11-15 | International Business Machines Corporation | FinFET devices with multiple channel lengths |
KR102392695B1 (ko) | 2015-05-26 | 2022-05-02 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
KR102399023B1 (ko) * | 2015-06-22 | 2022-05-16 | 삼성전자주식회사 | 반도체 장치 |
US9698225B2 (en) * | 2015-07-07 | 2017-07-04 | International Business Machines Corporation | Localized and self-aligned punch through stopper doping for finFET |
US9940424B2 (en) * | 2016-05-25 | 2018-04-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Systems and methods for minimum-implant-area aware detailed placement |
US9741823B1 (en) * | 2016-10-28 | 2017-08-22 | Internation Business Machines Corporation | Fin cut during replacement gate formation |
US10312132B2 (en) * | 2017-01-25 | 2019-06-04 | International Business Machines Corporation | Forming sacrificial endpoint layer for deep STI recess |
US10096524B1 (en) | 2017-10-18 | 2018-10-09 | International Business Machines Corporation | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0828476B2 (ja) * | 1991-06-07 | 1996-03-21 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6662350B2 (en) * | 2002-01-28 | 2003-12-09 | International Business Machines Corporation | FinFET layout generation |
KR100420070B1 (ko) * | 2002-02-01 | 2004-02-25 | 한국과학기술원 | 이중-게이트 플래쉬 메모리소자 및 그 제조방법 |
US6770516B2 (en) * | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
US7013447B2 (en) * | 2003-07-22 | 2006-03-14 | Freescale Semiconductor, Inc. | Method for converting a planar transistor design to a vertical double gate transistor design |
-
2004
- 2004-11-22 KR KR1020040095823A patent/KR100702552B1/ko not_active IP Right Cessation
- 2004-12-01 US US11/001,297 patent/US7315994B2/en not_active Expired - Fee Related
- 2004-12-21 JP JP2004370239A patent/JP4215712B2/ja not_active Expired - Fee Related
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009509344A (ja) * | 2005-09-19 | 2009-03-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 高密度のシェブロンfinFET及びそれを製造する方法 |
JP2008060219A (ja) * | 2006-08-30 | 2008-03-13 | Elpida Memory Inc | 半導体装置及びその製造方法 |
CN103187296B (zh) * | 2011-12-31 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
JP2018064125A (ja) * | 2013-08-23 | 2018-04-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US10181469B2 (en) | 2013-08-23 | 2019-01-15 | Socionext Inc. | Semiconductor integrated circuit device having a standard cell which includes a fin |
US10833075B2 (en) | 2013-08-23 | 2020-11-10 | Socionext Inc. | Semiconductor integrated circuit device having a standard cell which includes a fin |
US11362088B2 (en) | 2013-08-23 | 2022-06-14 | Socionext Inc. | Semiconductor integrated circuit device having a standard cell which includes a fin and a dummy transistor |
US11764217B2 (en) | 2013-08-23 | 2023-09-19 | Socionext Inc. | Semiconductor integrated circuit device having a standard cell which includes a fin and a dummy transistor |
JP2018064126A (ja) * | 2013-09-04 | 2018-04-19 | 株式会社ソシオネクスト | 半導体装置 |
US10242985B2 (en) | 2013-09-04 | 2019-03-26 | Socionext Inc. | Semiconductor device comprising a standard cell and a non-active transistor |
US10651175B2 (en) | 2013-09-04 | 2020-05-12 | Socionext Inc. | Semiconductor device comprising a standard cell including a non-active fin area |
US11114437B2 (en) | 2013-09-04 | 2021-09-07 | Socionext Inc. | Semiconductor device comprising first and second standard cells arranged adjacent to each other |
Also Published As
Publication number | Publication date |
---|---|
KR20050063674A (ko) | 2005-06-28 |
US7315994B2 (en) | 2008-01-01 |
JP4215712B2 (ja) | 2009-01-28 |
US20050136582A1 (en) | 2005-06-23 |
KR100702552B1 (ko) | 2007-04-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4215712B2 (ja) | フィン形状の生成方法及び装置 | |
US10878162B2 (en) | Metal with buried power for increased IC device density | |
JP6467476B2 (ja) | リニアFinFET構造をもつ回路 | |
JP5334367B2 (ja) | 高密度集積回路の製造方法 | |
CN110692137B (zh) | 用于5纳米及以上的标准单元布局架构和绘图样式 | |
CN102760179B (zh) | 用于将平面设计转换为FinFET设计的系统和方法 | |
TWI791904B (zh) | 半導體裝置和積體電路佈局設計修改方法 | |
US11302636B2 (en) | Semiconductor device and manufacturing method of the same | |
US20140331193A1 (en) | Method and device for increasing fin device density for unaligned fins | |
US12019969B2 (en) | Power rail with non-linear edge | |
TWI804797B (zh) | 半導體裝置以及製造半導體裝置的方法 | |
JP4481731B2 (ja) | 自動設計方法及び半導体集積回路 | |
US8703608B2 (en) | Control of local environment for polysilicon conductors in integrated circuits | |
TW202324496A (zh) | 半導體裝置的製造方法 | |
TW202141334A (zh) | 半導體元件 | |
EP1548619A2 (en) | Method and device for automated layer generation for double-gate finFET designs | |
TWI807579B (zh) | 半導體元件及其製造方法 | |
TWI774226B (zh) | 積體晶片及其設計與製造方法 | |
US20240105555A1 (en) | Semiconductor device and method for fabricating the same | |
US12033998B2 (en) | Integrated circuit and method of forming the same | |
US20230124119A1 (en) | Integrated circuit and method of forming the same | |
KR20240002217A (ko) | 집적 회로 디바이스 및 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070130 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080507 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080627 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20081021 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20081104 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111114 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |