JP2005184029A - 不揮発性記憶素子及び半導体集積回路装置 - Google Patents

不揮発性記憶素子及び半導体集積回路装置 Download PDF

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JP2005184029A
JP2005184029A JP2005041612A JP2005041612A JP2005184029A JP 2005184029 A JP2005184029 A JP 2005184029A JP 2005041612 A JP2005041612 A JP 2005041612A JP 2005041612 A JP2005041612 A JP 2005041612A JP 2005184029 A JP2005184029 A JP 2005184029A
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film
insulating film
region
semiconductor
silicon nitride
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JP2005041612A
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JP2005184029A5 (enExample
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Shoji Yadori
章二 宿利
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Renesas Technology Corp
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Renesas Technology Corp
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Publication of JP2005184029A5 publication Critical patent/JP2005184029A5/ja
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JP2005041612A 2005-02-18 2005-02-18 不揮発性記憶素子及び半導体集積回路装置 Pending JP2005184029A (ja)

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JP2005041612A JP2005184029A (ja) 2005-02-18 2005-02-18 不揮発性記憶素子及び半導体集積回路装置

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JP2005041612A JP2005184029A (ja) 2005-02-18 2005-02-18 不揮発性記憶素子及び半導体集積回路装置

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JP2001257698A Division JP2003068893A (ja) 2001-08-28 2001-08-28 不揮発性記憶素子及び半導体集積回路

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JP2008008964A Division JP2008172251A (ja) 2008-01-18 2008-01-18 不揮発性記憶素子及び半導体集積回路装置

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JP2005184029A true JP2005184029A (ja) 2005-07-07
JP2005184029A5 JP2005184029A5 (enExample) 2008-03-06

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067412A (ja) * 2005-08-31 2007-03-15 Samsung Electronics Co Ltd 電荷トラップ絶縁体の製造方法及びsonos型の不揮発性半導体装置の製造方法
JP2008084977A (ja) * 2006-09-26 2008-04-10 Denso Corp 不揮発性半導体記憶装置のデータ書き換え方法
KR100933905B1 (ko) * 2006-11-20 2009-12-28 매크로닉스 인터내셔널 컴퍼니 리미티드 터널링 배리어 상부에 전계 분산층을 구비하는 전하 트래핑소자
US8068370B2 (en) 2008-04-18 2011-11-29 Macronix International Co., Ltd. Floating gate memory device with interpoly charge trapping structure
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8987098B2 (en) 2012-06-19 2015-03-24 Macronix International Co., Ltd. Damascene word line
US9099538B2 (en) 2013-09-17 2015-08-04 Macronix International Co., Ltd. Conductor with a plurality of vertical extensions for a 3D device
US9379126B2 (en) 2013-03-14 2016-06-28 Macronix International Co., Ltd. Damascene conductor for a 3D device
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067412A (ja) * 2005-08-31 2007-03-15 Samsung Electronics Co Ltd 電荷トラップ絶縁体の製造方法及びsonos型の不揮発性半導体装置の製造方法
JP2008084977A (ja) * 2006-09-26 2008-04-10 Denso Corp 不揮発性半導体記憶装置のデータ書き換え方法
KR100933905B1 (ko) * 2006-11-20 2009-12-28 매크로닉스 인터내셔널 컴퍼니 리미티드 터널링 배리어 상부에 전계 분산층을 구비하는 전하 트래핑소자
KR100942928B1 (ko) * 2006-11-20 2010-02-22 매크로닉스 인터내셔널 컴퍼니 리미티드 터널링 배리어 상부에 전계 분산층을 구비하는 전하 트래핑소자
US8889509B2 (en) 2006-11-20 2014-11-18 Macronix International Co., Ltd. Charge trapping devices with field distribution layer over tunneling barrier
US8101989B2 (en) 2006-11-20 2012-01-24 Macronix International Co., Ltd. Charge trapping devices with field distribution layer over tunneling barrier
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8068370B2 (en) 2008-04-18 2011-11-29 Macronix International Co., Ltd. Floating gate memory device with interpoly charge trapping structure
US8987098B2 (en) 2012-06-19 2015-03-24 Macronix International Co., Ltd. Damascene word line
US9379126B2 (en) 2013-03-14 2016-06-28 Macronix International Co., Ltd. Damascene conductor for a 3D device
US9099538B2 (en) 2013-09-17 2015-08-04 Macronix International Co., Ltd. Conductor with a plurality of vertical extensions for a 3D device
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND

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