JP2005159089A - 配線基板およびこれを用いた半導体装置 - Google Patents
配線基板およびこれを用いた半導体装置 Download PDFInfo
- Publication number
- JP2005159089A JP2005159089A JP2003396929A JP2003396929A JP2005159089A JP 2005159089 A JP2005159089 A JP 2005159089A JP 2003396929 A JP2003396929 A JP 2003396929A JP 2003396929 A JP2003396929 A JP 2003396929A JP 2005159089 A JP2005159089 A JP 2005159089A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- wiring board
- conductor
- insulating layer
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】 複数の絶縁層1bが積層されて成り、上面の中央部に半導体素子3がフリップチップ接続により搭載される搭載部を有する絶縁基板1と、絶縁層1bの層間に隣接して配設された第1の導体パターン2aおよび第2の導体パターン2bを有する配線基板であって、第1および第2の導体パターン2a、2bは、両者の隣接する縁が交互に相手側に入り込む波形である。
【選択図】 図2
Description
1b:絶縁層
2a:第1の導体パターン
2b:第2の導体パターン
3:半導体素子
Claims (2)
- 複数の絶縁層が積層されて成り、上面の中央部に半導体素子がフリップチップ接続により搭載される搭載部を有する絶縁基板と、前記絶縁層の層間に隣接して配設された第1の導体パターンおよび第2の導体パターンを有する配線基板であって、前記第1および第2の導体パターンは、両者の隣接する縁が交互に相手側に入り込む波形とされていることを特徴とする配線基板。
- 請求項1記載の配線基板の前記搭載部に前記半導体素子がフリップチップ接続により搭載されていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003396929A JP4227502B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003396929A JP4227502B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005159089A true JP2005159089A (ja) | 2005-06-16 |
JP4227502B2 JP4227502B2 (ja) | 2009-02-18 |
Family
ID=34722228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003396929A Expired - Fee Related JP4227502B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4227502B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012199426A (ja) * | 2011-03-22 | 2012-10-18 | Fujitsu Semiconductor Ltd | 配線基板 |
-
2003
- 2003-11-27 JP JP2003396929A patent/JP4227502B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012199426A (ja) * | 2011-03-22 | 2012-10-18 | Fujitsu Semiconductor Ltd | 配線基板 |
Also Published As
Publication number | Publication date |
---|---|
JP4227502B2 (ja) | 2009-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7704548B2 (en) | Method for manufacturing wiring board | |
KR101085733B1 (ko) | 전자소자 내장 인쇄회로기판 및 그 제조방법 | |
JPWO2007126090A1 (ja) | 回路基板、電子デバイス装置及び回路基板の製造方法 | |
KR20080076241A (ko) | 전자소자 내장 인쇄회로기판 및 그 제조방법 | |
JP2007096273A (ja) | 配線基板 | |
JP2008016844A (ja) | プリント基板及びその製造方法 | |
TWI618199B (zh) | 佈線基板 | |
JPWO2011030542A1 (ja) | 電子部品モジュールおよびその製造方法 | |
TW201536130A (zh) | 內建零件的配線基板及其製造方法 | |
KR101905879B1 (ko) | 인쇄회로기판 및 그의 제조 방법 | |
JP2004179576A (ja) | 配線基板及びその製造方法 | |
JP2005150443A (ja) | 積層型半導体装置およびその製造方法 | |
JP2010109243A (ja) | 配線基板 | |
JP4235092B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP2007059588A (ja) | 配線基板の製造方法および配線基板 | |
JP4227502B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP5370883B2 (ja) | 配線基板 | |
JP2016127134A (ja) | 配線基板 | |
JP2009290044A (ja) | 配線基板 | |
JP2014123592A (ja) | プリント配線板の製造方法及びプリント配線板 | |
JP5808055B2 (ja) | 配線基板 | |
JP4439248B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP4508620B2 (ja) | 配線基板 | |
JP2004327633A (ja) | 配線基板 | |
JP2007258544A (ja) | 配線基板及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061109 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080512 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080520 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080718 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080811 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081009 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20081104 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20081128 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111205 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111205 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121205 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131205 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |