JP2005158968A - 配線基板およびこれを用いた半導体装置 - Google Patents
配線基板およびこれを用いた半導体装置 Download PDFInfo
- Publication number
- JP2005158968A JP2005158968A JP2003394571A JP2003394571A JP2005158968A JP 2005158968 A JP2005158968 A JP 2005158968A JP 2003394571 A JP2003394571 A JP 2003394571A JP 2003394571 A JP2003394571 A JP 2003394571A JP 2005158968 A JP2005158968 A JP 2005158968A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- wiring board
- semiconductor device
- connection
- mounting portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
【解決手段】 最外周に配列された接続パッド2aに、搭載部の外側に向けて延出する延出部11が形成されている。
【選択図】 図2
Description
2:配線導体
2a:接続パッド
3:半導体素子
8:半田
11:延出部
Claims (2)
- 上面の中央部に半導体素子がフリップチップ接続により搭載される搭載部を有する絶縁基板と、前記搭載部に縦横に並んで配列された、前記半導体素子の電極が半田を介して接続される複数の接続パッドとを具備する配線基板において、前記複数の接続パッドのうち最外周に配列された前記接続パッドは、前記搭載部の外側に向けて延出する延出部が形成されていることを特徴とする配線基板。
- 請求項1記載の配線基板の前記搭載部に前記半導体素子をフリップチップ接続により搭載したことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003394571A JP4439248B2 (ja) | 2003-11-25 | 2003-11-25 | 配線基板およびこれを用いた半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003394571A JP4439248B2 (ja) | 2003-11-25 | 2003-11-25 | 配線基板およびこれを用いた半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005158968A true JP2005158968A (ja) | 2005-06-16 |
JP4439248B2 JP4439248B2 (ja) | 2010-03-24 |
Family
ID=34720602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003394571A Expired - Fee Related JP4439248B2 (ja) | 2003-11-25 | 2003-11-25 | 配線基板およびこれを用いた半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4439248B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017152678A (ja) * | 2016-02-22 | 2017-08-31 | 京セラ株式会社 | 配線基板、電子装置および配線基板の製造方法 |
-
2003
- 2003-11-25 JP JP2003394571A patent/JP4439248B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017152678A (ja) * | 2016-02-22 | 2017-08-31 | 京セラ株式会社 | 配線基板、電子装置および配線基板の製造方法 |
Also Published As
Publication number | Publication date |
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JP4439248B2 (ja) | 2010-03-24 |
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