JP2005117066A - 半導体装置、実装用基板、電子機器 - Google Patents
半導体装置、実装用基板、電子機器 Download PDFInfo
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- JP2005117066A JP2005117066A JP2005002226A JP2005002226A JP2005117066A JP 2005117066 A JP2005117066 A JP 2005117066A JP 2005002226 A JP2005002226 A JP 2005002226A JP 2005002226 A JP2005002226 A JP 2005002226A JP 2005117066 A JP2005117066 A JP 2005117066A
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- Prior art keywords
- semiconductor
- semiconductor chip
- semiconductor device
- chips
- connection pad
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】基板上に複数の半導体チップを搭載した半導体装置であって、前記半導体チップの側面に形成された接続用パッドを互いに対向するように複数の半導体チップが配置されてなり、前記接続用パッド同士が接続されてなることから、多数の半導体チップとの突き合せ接続を行うことが可能になる。
【選択図】図1
Description
に示すように従来の半導体装置1では、その表面に配線が形成された基板2の実装面3に複数の半導体チップ4A、4Bが搭載されている。そしてこれら半導体チップ4A、4Bでは、上面5に設けられた接続用パッド(図示せず)と、基板2の表面に形成されたランド(図示せず)との間をワイヤ6で接続するとともに、前記ワイヤ6を用いて隣り合う半導体チップ4A、4Bの接続用パッド間を接続するようにしている(ワイヤボンディングと呼ばれ、ワイヤ材質は金やアルミが主流)。
2 基板
3 実装面
4A、4B 半導体チップ
5 上面
6 ワイヤ
7 外部端子
10 半導体装置
12 半導体チップ
14 絶縁膜
16 金属配線
18 側面
20 接続用パッド
22 金属素地
24 メッキ地
26 溝部
28 外部端子
30 基板
31 ワイヤ
32 レジストパターン
33A 境界線
33B レーザ光
33C レーザ照射器
34 貫通穴
35 半導体ウェハ
35A 割断用溝部
35B 粘着シート
35C ラップ定盤
35D 矢印
36 傾斜面
38 垂直面
40 能動面
42 ホール
44 銅またはタングステン
46 ダイシングライン
Claims (7)
- 基板上に複数の半導体チップを搭載した半導体装置であって、前記半導体チップの側面に形成された接続用パッドを互いに対向するように複数の半導体チップが配置されてなり、前記接続用パッド同士が接続されてなることを特徴とする半導体装置。
- 前記半導体チップは、隙間無く敷き詰められる同一形状の多角形であることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップは、正六角形であることを特徴とする請求項2に記載の半導体装置。
- 前記半導体チップの側面に形成された前記接続用パッドと前記半導体チップの表面から前記接続用パッドの裏面に形成されてなる傾斜面と、前記傾斜面に前記接続用パッドと導通する配線とを有することを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップの側面に形成された前記接続用パッドと前記半導体チップの表面から前記半導体チップを貫通する貫通穴と、前記貫通穴に前記接続用パッドと導通する配線とを有することを特徴とする請求項1に記載の半導体装置。
- 請求項1に記載の半導体装置を用いたことを特徴とする実装用基板。
- 請求項6に記載の実装用基板を用いたことを特徴とする電子機器。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005002226A JP4086038B2 (ja) | 2005-01-07 | 2005-01-07 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005002226A JP4086038B2 (ja) | 2005-01-07 | 2005-01-07 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24760799A Division JP3651325B2 (ja) | 1999-09-01 | 1999-09-01 | ペレタイズ方法および半導体チップの製造方法ならびに半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005117066A true JP2005117066A (ja) | 2005-04-28 |
JP4086038B2 JP4086038B2 (ja) | 2008-05-14 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2005002226A Expired - Fee Related JP4086038B2 (ja) | 2005-01-07 | 2005-01-07 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4086038B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008112752A (ja) * | 2006-10-27 | 2008-05-15 | Mitsubishi Heavy Ind Ltd | 半導体装置、検査装置、半導体装置の製造方法及びチップの製造方法 |
KR100871708B1 (ko) | 2007-04-03 | 2008-12-08 | 삼성전자주식회사 | 딤플을 구비하는 칩, 그 제조방법 및 그 칩을 이용한패키지 |
-
2005
- 2005-01-07 JP JP2005002226A patent/JP4086038B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008112752A (ja) * | 2006-10-27 | 2008-05-15 | Mitsubishi Heavy Ind Ltd | 半導体装置、検査装置、半導体装置の製造方法及びチップの製造方法 |
KR100871708B1 (ko) | 2007-04-03 | 2008-12-08 | 삼성전자주식회사 | 딤플을 구비하는 칩, 그 제조방법 및 그 칩을 이용한패키지 |
Also Published As
Publication number | Publication date |
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JP4086038B2 (ja) | 2008-05-14 |
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