JP2005101268A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2005101268A
JP2005101268A JP2003333070A JP2003333070A JP2005101268A JP 2005101268 A JP2005101268 A JP 2005101268A JP 2003333070 A JP2003333070 A JP 2003333070A JP 2003333070 A JP2003333070 A JP 2003333070A JP 2005101268 A JP2005101268 A JP 2005101268A
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JP
Japan
Prior art keywords
main surface
semiconductor substrate
pad electrode
via hole
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003333070A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005101268A5 (https=
Inventor
Akira Suzuki
彰 鈴木
Shinzo Ishibe
眞三 石部
Takashi Noma
崇 野間
Hiroyuki Shinoki
裕之 篠木
Koichi Takakura
康一 高倉
Yukihiro Takao
幸弘 高尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2003333070A priority Critical patent/JP2005101268A/ja
Publication of JP2005101268A publication Critical patent/JP2005101268A/ja
Publication of JP2005101268A5 publication Critical patent/JP2005101268A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/216—Through-semiconductor vias, e.g. TSVs characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2003333070A 2003-09-25 2003-09-25 半導体装置の製造方法 Pending JP2005101268A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003333070A JP2005101268A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003333070A JP2005101268A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2005101268A true JP2005101268A (ja) 2005-04-14
JP2005101268A5 JP2005101268A5 (https=) 2006-11-02

Family

ID=34461188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003333070A Pending JP2005101268A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2005101268A (https=)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053149A (ja) * 2005-08-16 2007-03-01 Renesas Technology Corp 半導体ウエハ及びその製造方法
JP2008034508A (ja) * 2006-07-27 2008-02-14 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2009545117A (ja) * 2006-07-25 2009-12-17 エルジー・ケム・リミテッド 有機発光素子の製造方法およびこれによって製造された有機発光素子
JP2010520641A (ja) * 2007-03-05 2010-06-10 テッセラ，インコーポレイテッド 貫通ビアによって前面接点に接続された後面接点を有するチップ
JP2012038872A (ja) * 2010-08-06 2012-02-23 On Semiconductor Trading Ltd 半導体装置及びその製造方法
JP2012084871A (ja) * 2010-09-15 2012-04-26 Elpida Memory Inc 半導体装置、およびその製造方法、ならびにデータ処理装置
CN102592982A (zh) * 2011-01-17 2012-07-18 精材科技股份有限公司 晶片封装体的形成方法
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8890322B2 (en) 2009-03-03 2014-11-18 Olympus Corporation Semiconductor apparatus and method of manufacturing semiconductor apparatus
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
CN107431017A (zh) * 2015-03-31 2017-12-01 浜松光子学株式会社 半导体装置
WO2021103110A1 (zh) * 2019-11-28 2021-06-03 苏州晶方半导体科技股份有限公司 芯片封装结构以及封装方法
WO2021199680A1 (ja) * 2020-03-31 2021-10-07 ソニーセミコンダクタソリューションズ株式会社 受光素子および電子機器

Cited By (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053149A (ja) * 2005-08-16 2007-03-01 Renesas Technology Corp 半導体ウエハ及びその製造方法
JP2009545117A (ja) * 2006-07-25 2009-12-17 エルジー・ケム・リミテッド 有機発光素子の製造方法およびこれによって製造された有機発光素子
JP2015008145A (ja) * 2006-07-25 2015-01-15 エルジー・ケム・リミテッド 有機発光素子の製造方法およびこれによって製造された有機発光素子
JP2008034508A (ja) * 2006-07-27 2008-02-14 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8653644B2 (en) 2006-11-22 2014-02-18 Tessera, Inc. Packaged semiconductor chips with array
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
EP2575166A3 (en) * 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
JP2010520641A (ja) * 2007-03-05 2010-06-10 テッセラ，インコーポレイテッド 貫通ビアによって前面接点に接続された後面接点を有するチップ
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8890322B2 (en) 2009-03-03 2014-11-18 Olympus Corporation Semiconductor apparatus and method of manufacturing semiconductor apparatus
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
JP2012038872A (ja) * 2010-08-06 2012-02-23 On Semiconductor Trading Ltd 半導体装置及びその製造方法
US9443790B2 (en) 2010-09-15 2016-09-13 Ps4 Luxco S.A.R.L. Semiconductor device
JP2012084871A (ja) * 2010-09-15 2012-04-26 Elpida Memory Inc 半導体装置、およびその製造方法、ならびにデータ処理装置
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US9847277B2 (en) 2010-09-17 2017-12-19 Tessera, Inc. Staged via formation from both sides of chip
US9362203B2 (en) 2010-09-17 2016-06-07 Tessera, Inc. Staged via formation from both sides of chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US9224649B2 (en) 2010-12-08 2015-12-29 Tessera, Inc. Compliant interconnects in wafers
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
CN102592982A (zh) * 2011-01-17 2012-07-18 精材科技股份有限公司 晶片封装体的形成方法
US10622402B2 (en) 2015-03-31 2020-04-14 Hamamatsu Photonics K.K. Semiconductor device
US10141368B2 (en) 2015-03-31 2018-11-27 Hamamatsu Photonics K.K. Semiconductor device
CN107431017A (zh) * 2015-03-31 2017-12-01 浜松光子学株式会社 半导体装置
US10403676B2 (en) 2015-03-31 2019-09-03 Hamamatsu Photonics K.K. Semiconductor device manufacturing method
US10615220B2 (en) 2015-03-31 2020-04-07 Hamamatsu Photonics K.K. Semiconductor device and manufacturing method thereof
US10622403B2 (en) 2015-03-31 2020-04-14 Hamamatsu Photonics K.K. Semiconductor device manufacturing method
EP3279926A4 (en) * 2015-03-31 2018-11-07 Hamamatsu Photonics K.K. Semiconductor device
CN107431017B (zh) * 2015-03-31 2020-12-04 浜松光子学株式会社 半导体装置
CN114050124A (zh) * 2015-03-31 2022-02-15 浜松光子学株式会社 半导体装置的制造方法
EP3961687A1 (en) * 2015-03-31 2022-03-02 Hamamatsu Photonics K.K. Semiconductor device manufacturing method
CN114050124B (zh) * 2015-03-31 2025-09-30 浜松光子学株式会社 半导体装置的制造方法
WO2021103110A1 (zh) * 2019-11-28 2021-06-03 苏州晶方半导体科技股份有限公司 芯片封装结构以及封装方法
WO2021199680A1 (ja) * 2020-03-31 2021-10-07 ソニーセミコンダクタソリューションズ株式会社 受光素子および電子機器

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