JP2004503089A - 銅のメタライゼーションに関するビアファーストのデュアルダマシン法 - Google Patents

銅のメタライゼーションに関するビアファーストのデュアルダマシン法 Download PDF

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Publication number
JP2004503089A
JP2004503089A JP2002507438A JP2002507438A JP2004503089A JP 2004503089 A JP2004503089 A JP 2004503089A JP 2002507438 A JP2002507438 A JP 2002507438A JP 2002507438 A JP2002507438 A JP 2002507438A JP 2004503089 A JP2004503089 A JP 2004503089A
Authority
JP
Japan
Prior art keywords
insulating layer
layer
forming
vias
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002507438A
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English (en)
Japanese (ja)
Other versions
JP2004503089A5 (https=
JP2004503089A6 (ja
Inventor
ブラズ，ガブリエラ
シュレーダー，ウヴェ，パウル
ハロウェイ，ケレン，リン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of JP2004503089A publication Critical patent/JP2004503089A/ja
Publication of JP2004503089A6 publication Critical patent/JP2004503089A6/ja
Publication of JP2004503089A5 publication Critical patent/JP2004503089A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2002507438A 2000-06-30 2001-07-02 銅のメタライゼーションに関するビアファーストのデュアルダマシン法 Pending JP2004503089A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60854000A 2000-06-30 2000-06-30
US09/608,541 2000-06-30
PCT/US2001/021161 WO2002003457A2 (en) 2000-06-30 2001-07-02 Via first dual damascene process for copper metallization

Publications (3)

Publication Number Publication Date
JP2004503089A true JP2004503089A (ja) 2004-01-29
JP2004503089A6 JP2004503089A6 (ja) 2004-08-05
JP2004503089A5 JP2004503089A5 (https=) 2005-02-03

Family

ID=24436949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002507438A Pending JP2004503089A (ja) 2000-06-30 2001-07-02 銅のメタライゼーションに関するビアファーストのデュアルダマシン法

Country Status (4)

Country Link
JP (1) JP2004503089A (https=)
KR (1) KR100474605B1 (https=)
TW (1) TW519725B (https=)
WO (1) WO2002003457A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102454363B1 (ko) 2020-08-24 2022-10-14 주식회사 세움피엔에프 운동기구의 수평 이동 장치
KR102491980B1 (ko) 2021-01-05 2023-01-27 최순복 필라테스용 레더바렐
CN113394184B (zh) * 2021-06-09 2022-06-17 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
US11876047B2 (en) 2021-09-14 2024-01-16 International Business Machines Corporation Decoupled interconnect structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6127258A (en) * 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2000150644A (ja) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp 半導体デバイスの製造方法
EP1192656A1 (en) * 1999-06-30 2002-04-03 Intel Corporation Method of protecting an underlying wiring layer during dual damascene processing

Also Published As

Publication number Publication date
TW519725B (en) 2003-02-01
KR20030020324A (ko) 2003-03-08
WO2002003457A2 (en) 2002-01-10
WO2002003457A3 (en) 2002-06-06
KR100474605B1 (ko) 2005-03-10

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