WO2002003457A3 - Via first dual damascene process for copper metallization - Google Patents

Via first dual damascene process for copper metallization Download PDF

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Publication number
WO2002003457A3
WO2002003457A3 PCT/US2001/021161 US0121161W WO0203457A3 WO 2002003457 A3 WO2002003457 A3 WO 2002003457A3 US 0121161 W US0121161 W US 0121161W WO 0203457 A3 WO0203457 A3 WO 0203457A3
Authority
WO
WIPO (PCT)
Prior art keywords
dual damascene
damascene process
copper metallization
vias
filling
Prior art date
Application number
PCT/US2001/021161
Other languages
French (fr)
Other versions
WO2002003457A2 (en
Inventor
Gabriela Brase
Uwe Paul Schroeder
Karen Lynne Holloway
Original Assignee
Infineon Technologies Corp
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp, Ibm filed Critical Infineon Technologies Corp
Priority to EP01953408A priority Critical patent/EP1295333A2/en
Priority to KR10-2002-7018006A priority patent/KR100474605B1/en
Priority to JP2002507438A priority patent/JP2004503089A/en
Publication of WO2002003457A2 publication Critical patent/WO2002003457A2/en
Publication of WO2002003457A3 publication Critical patent/WO2002003457A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The process of filling the vias and trenches involves use of a silicon nitride film (24) as an etch stop and the filling of the vias with an anti-reflection coating (30).
PCT/US2001/021161 2000-06-30 2001-07-02 Via first dual damascene process for copper metallization WO2002003457A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP01953408A EP1295333A2 (en) 2000-06-30 2001-07-02 Via first dual damascene process ofr copper metallization
KR10-2002-7018006A KR100474605B1 (en) 2000-06-30 2001-07-02 Via first dual damascene process for copper metallization
JP2002507438A JP2004503089A (en) 2000-06-30 2001-07-02 Via-first dual damascene method for copper metallization

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60854000A 2000-06-30 2000-06-30
US09/608,540 2000-06-30

Publications (2)

Publication Number Publication Date
WO2002003457A2 WO2002003457A2 (en) 2002-01-10
WO2002003457A3 true WO2002003457A3 (en) 2002-06-06

Family

ID=24436949

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/021161 WO2002003457A2 (en) 2000-06-30 2001-07-02 Via first dual damascene process for copper metallization

Country Status (4)

Country Link
JP (1) JP2004503089A (en)
KR (1) KR100474605B1 (en)
TW (1) TW519725B (en)
WO (1) WO2002003457A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102454363B1 (en) 2020-08-24 2022-10-14 주식회사 세움피엔에프 Horizontal moving device of combined exercise equipment
KR102491980B1 (en) 2021-01-05 2023-01-27 최순복 Pilates ladder barrel
CN113394184B (en) * 2021-06-09 2022-06-17 武汉新芯集成电路制造有限公司 Semiconductor device and method for manufacturing the same
US11876047B2 (en) 2021-09-14 2024-01-16 International Business Machines Corporation Decoupled interconnect structures

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0892428A2 (en) * 1997-07-17 1999-01-20 Sharp Kabushiki Kaisha Method of producing low resistance contacts between integrated circuit metal levels and structure produced thereby.
WO2000005763A1 (en) * 1998-07-23 2000-02-03 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2000049137A (en) * 1998-06-25 2000-02-18 Motorola Inc Forming method of semiconductor element
WO2000014793A2 (en) * 1998-09-08 2000-03-16 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
JP2000150644A (en) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp Manufacture of semiconductor device
WO2001001480A1 (en) * 1999-06-30 2001-01-04 Intel Corporation Method of protecting an underlying wiring layer during dual damascene processing

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0892428A2 (en) * 1997-07-17 1999-01-20 Sharp Kabushiki Kaisha Method of producing low resistance contacts between integrated circuit metal levels and structure produced thereby.
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
JP2000049137A (en) * 1998-06-25 2000-02-18 Motorola Inc Forming method of semiconductor element
US6127258A (en) * 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
WO2000005763A1 (en) * 1998-07-23 2000-02-03 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
WO2000014793A2 (en) * 1998-09-08 2000-03-16 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
JP2000150644A (en) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp Manufacture of semiconductor device
US6251774B1 (en) * 1998-11-10 2001-06-26 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
WO2001001480A1 (en) * 1999-06-30 2001-01-04 Intel Corporation Method of protecting an underlying wiring layer during dual damascene processing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 05 14 September 2000 (2000-09-14) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 08 6 October 2000 (2000-10-06) *

Also Published As

Publication number Publication date
TW519725B (en) 2003-02-01
WO2002003457A2 (en) 2002-01-10
JP2004503089A (en) 2004-01-29
KR100474605B1 (en) 2005-03-10
KR20030020324A (en) 2003-03-08

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