KR100474605B1 - 구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스 - Google Patents

구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스 Download PDF

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Publication number
KR100474605B1
KR100474605B1 KR10-2002-7018006A KR20027018006A KR100474605B1 KR 100474605 B1 KR100474605 B1 KR 100474605B1 KR 20027018006 A KR20027018006 A KR 20027018006A KR 100474605 B1 KR100474605 B1 KR 100474605B1
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KR
South Korea
Prior art keywords
insulating layer
vias
layer
copper
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR10-2002-7018006A
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English (en)
Korean (ko)
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KR20030020324A (ko
Inventor
브라스가브리엘라
슈뢰더우베폴
할로웨이카렌린
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
인피네온 테크놀로지스 아게
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션, 인피네온 테크놀로지스 아게 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR20030020324A publication Critical patent/KR20030020324A/ko
Application granted granted Critical
Publication of KR100474605B1 publication Critical patent/KR100474605B1/ko
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Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR10-2002-7018006A 2000-06-30 2001-07-02 구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스 Expired - Lifetime KR100474605B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US60854000A 2000-06-30 2000-06-30
US09/608,541 2000-06-30
US09/608,540 2000-06-30
PCT/US2001/021161 WO2002003457A2 (en) 2000-06-30 2001-07-02 Via first dual damascene process for copper metallization

Publications (2)

Publication Number Publication Date
KR20030020324A KR20030020324A (ko) 2003-03-08
KR100474605B1 true KR100474605B1 (ko) 2005-03-10

Family

ID=24436949

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-7018006A Expired - Lifetime KR100474605B1 (ko) 2000-06-30 2001-07-02 구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스

Country Status (4)

Country Link
JP (1) JP2004503089A (https=)
KR (1) KR100474605B1 (https=)
TW (1) TW519725B (https=)
WO (1) WO2002003457A2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220025480A (ko) 2020-08-24 2022-03-03 주식회사 세움피엔에프 운동기구의 수평 이동 장치
KR20220098929A (ko) 2021-01-05 2022-07-12 최순복 필라테스용 레더바렐

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113394184B (zh) * 2021-06-09 2022-06-17 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
US11876047B2 (en) 2021-09-14 2024-01-16 International Business Machines Corporation Decoupled interconnect structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6127258A (en) * 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2000150644A (ja) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp 半導体デバイスの製造方法
EP1192656A1 (en) * 1999-06-30 2002-04-03 Intel Corporation Method of protecting an underlying wiring layer during dual damascene processing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220025480A (ko) 2020-08-24 2022-03-03 주식회사 세움피엔에프 운동기구의 수평 이동 장치
KR20220098929A (ko) 2021-01-05 2022-07-12 최순복 필라테스용 레더바렐

Also Published As

Publication number Publication date
TW519725B (en) 2003-02-01
JP2004503089A (ja) 2004-01-29
KR20030020324A (ko) 2003-03-08
WO2002003457A2 (en) 2002-01-10
WO2002003457A3 (en) 2002-06-06

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