JP2004158672A - Method for manufacturing multilayer board - Google Patents

Method for manufacturing multilayer board Download PDF

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Publication number
JP2004158672A
JP2004158672A JP2002323683A JP2002323683A JP2004158672A JP 2004158672 A JP2004158672 A JP 2004158672A JP 2002323683 A JP2002323683 A JP 2002323683A JP 2002323683 A JP2002323683 A JP 2002323683A JP 2004158672 A JP2004158672 A JP 2004158672A
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JP
Japan
Prior art keywords
copper
etching
substrate
layer
resin substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002323683A
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Japanese (ja)
Inventor
Riichi Sekimoto
利一 関本
Tatsumi Takahashi
達美 高橋
Junichi Ito
純一 伊藤
Hiroyuki Owada
裕之 大和田
Hiroki Taniguchi
博喜 谷口
Kenichi Ryuba
健一 柳葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EITO KOGYO KK
Original Assignee
EITO KOGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EITO KOGYO KK filed Critical EITO KOGYO KK
Priority to JP2002323683A priority Critical patent/JP2004158672A/en
Publication of JP2004158672A publication Critical patent/JP2004158672A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer board in which the accuracy of a through hole can be enhanced, a manufacturing time can be shortened by simplifying production, and adhesion can be enhanced between layers. <P>SOLUTION: The multilayer board is manufactured through seven steps as follows. 1. Metal foil having a three-layer structure of copper 2/nickel 3/copper 4 is formed on the surface of a resin substrate 1, and an etching resist 5 is formed in a region other than bumps. 2. Etching is performed. 3. Bumps are subjected to solder plating after removing the resist. 4. Copper foil 4 laid under a solder plating layer is etched. 5. An adhesive resin film 7 is formed on the rear surface of the resin substrate. 6. Holes fitted with lower layer bumps are formed in the adhesive resin and the resin substrate by laser beam machining. 7. The layers are integrated by full hot press. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明はガラスエポキシ樹脂等のコア材の両面に、導電パターンを絶縁層を介在させて複数層形成し、前記コア材を挟んだ各面の所望の導電パターンを絶縁層に形成したスルーホールで接続し多層基板の製造方法に関する。
【0002】
【従来の技術】
従来におけるビルドアップ法によって製作される積層基板としては、コア材の片面あにいは両面にエキシマレーザ等によって溶解する絶縁層を形成し、その後、該絶縁層にマキシマレーザを照射することによってスルーホールを形成し、次いで、メッキを行って前記絶縁層の上に導電パターンを形成すると共に、前記スルーホールの内周面にもメッキを施して所望の上部導電パターンと下部導電パターンとを接続するものであった。
【0003】
【特許文献】特開2001−358464
【0004】
【発明が解決しようとする課題】
ところで、前記した従来におけるビルドアップ法によって形成された多層基板にあっては、マキシマレーザの照射径によりスルーホールの孔径が決定されるために、小さなスルーホールを形成することは困難であり、また、スルーホールを希望する部分に正確に製作するためには、位置決めのために時間が掛かるといった問題があった。
【0005】
本発明は前記した問題点を解決せんとするもので、その目的とするところは、スルーホールの精度を高めることができると共に、製作が簡単で製作時間の短縮が図れ、また、各層間の接着力を高めることができる多層基板の製造方法を提供せんとするにある。
【0006】
【課題を解決するための手段】
本発明の積層基板の製造方法は前記した目的を達成せんとするもので、その手段は、ガラスエポキシ等の樹脂基板の表面に銅箔、ニッケル箔および銅、ニッケル(半田と錫との合金でも可)銅の3層メタライズ構造の銅箔を積層すると共にバンプおよび下層のバンプとの接続部分を残してエッチングレジストを形成する第1の工程と、前記エッチングレジストを施した部分を除いてエッチングを行う第2の工程と、前記エッチングレジストを除去した後にバンプとなる部分に半田メッキを行う第3の工程と、該半田メッキの下層部分に位置する前記3層メタライズ構造の銅箔をエッチングする第4の工程と、前記樹脂基板の裏面にプリプレブ等の接着性樹脂膜を形成する第5の工程と、該接着性樹脂および前記樹脂基板に下層のバンプが嵌合される孔をレーザ加工によって形成する第6の工程と、前記第1の工程から第6の工程によって製作した各層を一括加熱プレス加工によって一体化する第7の工程からなるものである。
【0007】
【発明の実施の形態】
以下、本発明に係る多層基板の製造方法を図面と共に説明する。
図1(a)〜(e)は第1基板層Aを製作する工程を示し、(a)は第1工程であるガラスエポキシ等による樹脂基板1、該樹脂基板1の表面に形成した銅箔2、該銅箔2の表面に形成したニッケル箔3、銅(50μ)、ニッケルまたは半田と錫の合金(3μ)、銅(18μ)の3層メタライズ構造の銅箔4、前記樹脂基板1のみを溶融することのないエッチングレジスト5を積層したものであり、該エッチングレジスト5は図1(g)に示す下層の第2層のバンプbの位置までされている。
【0008】
(b)は第2の工程である塩銅エッチング液によってエッチングを行う工程を示し、このエッチング工程によって前記エッチングレジスト5の下部を残して露出している銅箔4、ニッケル箔3および銅箔2が除去される。
【0009】
(c)は第3の工程を示し、前記エッチング工程が終了した後のエッチングレジスト5を除去し、次いで、バンプaを形成する部分のみに半田メッキ6を施した工程を示している。
【0010】
(d)は第4の工程である塩化アンモニューム銅液によってエッチングを行う工程を示し、このエッチング工程によって前記半田メッキ6の下部を残して露出している銅箔4が除去される。
【0011】
(e)は第5の工程を示し、樹脂基板1の裏面にプリプレグ等の接着性樹脂膜7を形成する工程である。(f)は第6の工程を示し、前記接着性樹脂膜7側からレーザ光を照射して前記バンプbが嵌合される孔a1 を形成する工程である。
【0012】
(f)は前記した第1の工程から第5の工程を経て製作したと同様な工程によって第2基板層Bおよび第3基板層Cを製作する。この時、第2基板層Bの孔b1 に第3基板層Cのバンプcが嵌合するように製作する。また、前記第1基板層Aのバンプaが嵌合される孔d1 を有するガラスエポキシ樹脂等の樹脂基板8の裏面側にプリプレグ等の接着性樹脂膜9を形成し、かつ、上面に銅箔10を形成した第4基板層Dを形成し、さらに、第3基板層Cの孔c1 と嵌合されるバンプeを有する銅板11からなる第5基板層Eを形成する。なお、前記バンプeの上面には半田メッキ12が形成されている。
【0013】
このように啓作した第1基板層A〜第5基板層Eを図2(g)のように配列積層すると共に加熱プレスすることにより、各基板層間は接着性樹脂膜によって一体化されると共に各バンプは半田メッキが溶解して上面の銅箔に電気的に接続される(図2(f)参照)。
【0014】
そして、第4基板層Dと第5基板層Eの銅箔10,11をエッチング処理によってバンプaとバンプeとが表面に露出するパターンd,e1 となり、残された銅箔10と11とはバンプa〜eを介して電気的に接続されることとなる。
【0015】
【発明の効果】
本発明は前記したように、下層のバンプと接続される導電パターンと上層の導電パターンに接続されるバンプを形成した各基板層を重ねた状態で加熱プレスことにより積層基板を製造することができるので、スルーホールの精度を高めることができると共に、製作が簡単で製作時間の短縮が図れ、また、各層間の接着力を高めることができる等の効果を有するものである。
【図面の簡単な説明】
【図1】(a)〜(f)は本発明の積層基板の製造方法に係る実施の形態を示す製造工程の説明図である。
【図2】(g)〜(i)は同上の製造工程に続く工程である。
【符号の説明】
1 樹脂基板
2 銅箔
3 ニッケル箔
4 銅箔
5 エッチングレジスト
6 半田メッキ
7 接着性樹脂膜
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is a through-hole in which a plurality of conductive patterns are formed on both surfaces of a core material such as a glass epoxy resin with an insulating layer interposed, and a desired conductive pattern on each surface sandwiching the core material is formed on the insulating layer. The present invention relates to a method for manufacturing a connected multilayer substrate.
[0002]
[Prior art]
As a laminated substrate manufactured by a conventional build-up method, an insulating layer that is melted by an excimer laser or the like is formed on one side or both sides of a core material, and thereafter, the through-hole is formed by irradiating the insulating layer with a maxima laser. Forming, then, plating to form a conductive pattern on the insulating layer, and plating the inner peripheral surface of the through hole to connect the desired upper conductive pattern and lower conductive pattern. there were.
[0003]
[Patent Document] JP-A-2001-358644
[0004]
[Problems to be solved by the invention]
By the way, in the multilayer substrate formed by the above-described conventional build-up method, since the diameter of the through-hole is determined by the irradiation diameter of the maxima laser, it is difficult to form a small through-hole, In order to accurately manufacture a through hole at a desired portion, it takes a long time for positioning.
[0005]
An object of the present invention is to solve the above-mentioned problems. The object of the present invention is to improve the accuracy of a through hole, to simplify the production, to shorten the production time, and to bond the layers. It is an object of the present invention to provide a method for manufacturing a multilayer substrate capable of increasing the power.
[0006]
[Means for Solving the Problems]
The method of manufacturing a laminated substrate according to the present invention achieves the above-mentioned object, and the means includes a method in which a copper foil, a nickel foil, copper, and nickel (an alloy of solder and tin are used) on a surface of a resin substrate such as glass epoxy. (Possible) A first step of laminating a copper foil having a three-layer metallized structure of copper and forming an etching resist while leaving a connection portion between the bump and the lower bump, and performing etching except for the portion where the etching resist is applied. A second step of performing, a third step of performing solder plating on a portion to be a bump after removing the etching resist, and a third step of etching the copper foil of the three-layer metallized structure located in a lower layer portion of the solder plating. Step 4, a fifth step of forming an adhesive resin film such as a prepreg on the back surface of the resin substrate, and lower bumps are fitted to the adhesive resin and the resin substrate. A sixth step of forming by laser machining a hole that is made of a seventh step of integrating the collective heating pressing each layer fabricated by the sixth step from the first step.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a multilayer substrate according to the present invention will be described with reference to the drawings.
FIGS. 1A to 1E show a process of manufacturing a first substrate layer A. FIG. 1A shows a first process, a resin substrate 1 made of glass epoxy or the like, and a copper foil formed on a surface of the resin substrate 1. 2, a nickel foil 3 formed on the surface of the copper foil 2, copper (50μ), an alloy of nickel or solder and tin (3μ), copper foil 18 of a three-layer metallized structure of copper (18μ), only the resin substrate 1 Is laminated so that the etching resist 5 is not melted. The etching resist 5 extends to the position of the lower second layer bump b shown in FIG. 1 (g).
[0008]
(B) shows a second step of etching with a salt copper etching solution, which is a copper foil 4, a nickel foil 3, and a copper foil 2 which are exposed by the etching step except for the lower portion of the etching resist 5. Is removed.
[0009]
(C) shows a third step, in which the etching resist 5 after the completion of the etching step is removed, and then the solder plating 6 is applied only to the portion where the bump a is to be formed.
[0010]
(D) shows a fourth step of etching with an ammonium chloride copper solution, and the exposed copper foil 4 excluding the lower portion of the solder plating 6 is removed by this etching step.
[0011]
(E) shows a fifth step in which an adhesive resin film 7 such as a prepreg is formed on the back surface of the resin substrate 1. (F) shows a sixth step, in which a laser beam is irradiated from the adhesive resin film 7 side to form a hole a1 into which the bump b is fitted.
[0012]
In (f), the second substrate layer B and the third substrate layer C are manufactured by the same steps as those manufactured through the above-described first to fifth steps. At this time, it is manufactured so that the bump c of the third substrate layer C is fitted into the hole b1 of the second substrate layer B. An adhesive resin film 9 such as a prepreg is formed on the back surface of a resin substrate 8 such as a glass epoxy resin having a hole d1 into which the bump a of the first substrate layer A is fitted, and a copper foil is formed on the upper surface. The fourth substrate layer D on which the substrate 10 is formed is formed, and further, the fifth substrate layer E made of the copper plate 11 having the bump e fitted with the hole c1 of the third substrate layer C is formed. Note that a solder plating 12 is formed on the upper surface of the bump e.
[0013]
The first substrate layer A to the fifth substrate layer E thus elaborated are arranged and laminated as shown in FIG. 2 (g), and are heated and pressed. The bumps are melted by the solder plating and are electrically connected to the copper foil on the upper surface (see FIG. 2 (f)).
[0014]
Then, the copper foils 10 and 11 of the fourth substrate layer D and the fifth substrate layer E are etched to form patterns d and e1 in which the bumps a and e are exposed on the surface. Electrical connection is made via the bumps a to e.
[0015]
【The invention's effect】
As described above, according to the present invention, a laminated substrate can be manufactured by heating and pressing each of the substrate layers on which the conductive patterns connected to the lower bumps and the bumps connected to the upper conductive patterns are stacked. Therefore, the precision of the through-hole can be improved, the production is simple, the production time can be shortened, and the adhesive strength between the layers can be increased.
[Brief description of the drawings]
FIGS. 1A to 1F are explanatory views of a manufacturing process showing an embodiment according to a method of manufacturing a laminated substrate of the present invention.
FIG. 2 (g) to (i) are steps subsequent to the above manufacturing steps.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Resin board 2 Copper foil 3 Nickel foil 4 Copper foil 5 Etching resist 6 Solder plating 7 Adhesive resin film

Claims (1)

ガラスエポキシ等の樹脂基板の表面に銅箔、ニッケル箔および銅、ニッケル(半田と錫との合金でも可)銅の3層メタライズ構造の銅箔を積層すると共にバンプおよび下層のバンプとの接続部分を残してエッチングレジストを形成する第1の工程と、前記エッチングレジストを施した部分を除いてエッチングを行う第2の工程と、前記エッチングレジストを除去した後にバンプとなる部分に半田メッキを行う第3の工程と、該半田メッキの下層部分に位置する前記3層メタライズ構造の銅箔をエッチングする第4の工程と、前記樹脂基板の裏面にプリプレブ等の接着性樹脂膜を形成する第5の工程と、該接着性樹脂および前記樹脂基板に下層のバンプが嵌合される孔をレーザ加工によって形成する第6の工程と、前記第1の工程から第6の工程によって製作した各層を一括加熱プレス加工によって一体化する第7の工程からなる多層基板の製造方法。A copper foil, a nickel foil and a copper foil of a three-layer metallized structure of a copper, nickel (or an alloy of solder and tin) copper are laminated on a surface of a resin substrate such as a glass epoxy, and a connection portion between the bump and a lower bump is formed. A first step of forming an etching resist while leaving a second step, a second step of performing etching except for the part where the etching resist has been applied, and a second step of performing solder plating on a part to be a bump after removing the etching resist. A third step of etching the copper foil of the three-layer metallized structure located below the solder plating, and a fifth step of forming an adhesive resin film such as a prepreg on the back surface of the resin substrate. A sixth step of forming, by laser processing, a hole into which the lower bump is fitted in the adhesive resin and the resin substrate, and a sixth step from the first step. Seventh method of manufacturing a multilayer substrate made of a step of integrating the collective heating pressing each layer fabricated by.
JP2002323683A 2002-11-07 2002-11-07 Method for manufacturing multilayer board Pending JP2004158672A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100717909B1 (en) * 2006-02-24 2007-05-14 삼성전기주식회사 Substrate comprising nickel layer and its manufacturing method
KR100873666B1 (en) * 2007-06-25 2008-12-11 대덕전자 주식회사 Method of processing double-sided core for printed circuit board
JP2009528707A (en) * 2006-03-03 2009-08-06 ウエイブニクス インク. Multilayer package structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100717909B1 (en) * 2006-02-24 2007-05-14 삼성전기주식회사 Substrate comprising nickel layer and its manufacturing method
JP2009528707A (en) * 2006-03-03 2009-08-06 ウエイブニクス インク. Multilayer package structure and manufacturing method thereof
KR100873666B1 (en) * 2007-06-25 2008-12-11 대덕전자 주식회사 Method of processing double-sided core for printed circuit board

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