JP2004031561A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2004031561A
JP2004031561A JP2002184316A JP2002184316A JP2004031561A JP 2004031561 A JP2004031561 A JP 2004031561A JP 2002184316 A JP2002184316 A JP 2002184316A JP 2002184316 A JP2002184316 A JP 2002184316A JP 2004031561 A JP2004031561 A JP 2004031561A
Authority
JP
Japan
Prior art keywords
main surface
substrate
semiconductor chip
connection terminals
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002184316A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004031561A5 (https=
Inventor
Noriyuki Takahashi
高橋　典之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Renesas Technology Corp
Hitachi Yonezawa Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Hitachi Yonezawa Electronics Co Ltd filed Critical Renesas Technology Corp
Priority to JP2002184316A priority Critical patent/JP2004031561A/ja
Publication of JP2004031561A publication Critical patent/JP2004031561A/ja
Publication of JP2004031561A5 publication Critical patent/JP2004031561A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07553—Controlling the environment, e.g. atmosphere composition or temperature changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/537—Multiple bond wires having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2002184316A 2002-06-25 2002-06-25 半導体装置およびその製造方法 Pending JP2004031561A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002184316A JP2004031561A (ja) 2002-06-25 2002-06-25 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002184316A JP2004031561A (ja) 2002-06-25 2002-06-25 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2004031561A true JP2004031561A (ja) 2004-01-29
JP2004031561A5 JP2004031561A5 (https=) 2005-10-13

Family

ID=31180264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002184316A Pending JP2004031561A (ja) 2002-06-25 2002-06-25 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JP2004031561A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073586A (ja) * 2004-08-31 2006-03-16 Renesas Technology Corp 半導体装置の製造方法
KR100752648B1 (ko) * 2006-01-09 2007-08-29 삼성전자주식회사 솔더 조인트 신뢰성이 개선된 반도체 패키지 및 그제조방법
JP2008192898A (ja) * 2007-02-06 2008-08-21 Renesas Technology Corp 半導体装置
CN115321467A (zh) * 2022-09-06 2022-11-11 合肥领航微系统集成有限公司 Mems芯片封装结构、具有其的超声波传感器及封装工艺

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073586A (ja) * 2004-08-31 2006-03-16 Renesas Technology Corp 半導体装置の製造方法
KR100752648B1 (ko) * 2006-01-09 2007-08-29 삼성전자주식회사 솔더 조인트 신뢰성이 개선된 반도체 패키지 및 그제조방법
JP2008192898A (ja) * 2007-02-06 2008-08-21 Renesas Technology Corp 半導体装置
CN115321467A (zh) * 2022-09-06 2022-11-11 合肥领航微系统集成有限公司 Mems芯片封装结构、具有其的超声波传感器及封装工艺

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