JP2003501800A - 窒化物スペーサーを用いて高密度のメモリセルおよび小さな間隔を作る方法 - Google Patents

窒化物スペーサーを用いて高密度のメモリセルおよび小さな間隔を作る方法

Info

Publication number
JP2003501800A
JP2003501800A JP2001500325A JP2001500325A JP2003501800A JP 2003501800 A JP2003501800 A JP 2003501800A JP 2001500325 A JP2001500325 A JP 2001500325A JP 2001500325 A JP2001500325 A JP 2001500325A JP 2003501800 A JP2003501800 A JP 2003501800A
Authority
JP
Japan
Prior art keywords
layer
nitride
arc
dimension
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001500325A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003501800A5 (https=
Inventor
ランガラジャン，バラス
シン，バンワール
テンプルトン，マイケル・ケイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003501800A publication Critical patent/JP2003501800A/ja
Publication of JP2003501800A5 publication Critical patent/JP2003501800A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks

Landscapes

  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2001500325A 1999-05-26 2000-03-13 窒化物スペーサーを用いて高密度のメモリセルおよび小さな間隔を作る方法 Pending JP2003501800A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/320,417 US6329124B1 (en) 1999-05-26 1999-05-26 Method to produce high density memory cells and small spaces by using nitride spacer
US09/320,417 1999-05-26
PCT/US2000/006585 WO2000074121A1 (en) 1999-05-26 2000-03-13 Method to produce high density memory cells and small spaces by using nitride spacer

Publications (2)

Publication Number Publication Date
JP2003501800A true JP2003501800A (ja) 2003-01-14
JP2003501800A5 JP2003501800A5 (https=) 2007-04-05

Family

ID=23246336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001500325A Pending JP2003501800A (ja) 1999-05-26 2000-03-13 窒化物スペーサーを用いて高密度のメモリセルおよび小さな間隔を作る方法

Country Status (5)

Country Link
US (1) US6329124B1 (https=)
EP (1) EP1181714A1 (https=)
JP (1) JP2003501800A (https=)
KR (1) KR100682638B1 (https=)
WO (1) WO2000074121A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014112655A (ja) * 2012-10-30 2014-06-19 Dainippon Printing Co Ltd ナノインプリントモールドおよびその製造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG102681A1 (en) 2001-02-19 2004-03-26 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
US20030064585A1 (en) * 2001-09-28 2003-04-03 Yider Wu Manufacture of semiconductor device with spacing narrower than lithography limit
US6664191B1 (en) * 2001-10-09 2003-12-16 Advanced Micro Devices, Inc. Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
US6977203B2 (en) * 2001-11-20 2005-12-20 General Semiconductor, Inc. Method of forming narrow trenches in semiconductor substrates
US7029958B2 (en) * 2003-11-04 2006-04-18 Advanced Micro Devices, Inc. Self aligned damascene gate
CN100356513C (zh) * 2003-11-19 2007-12-19 旺宏电子股份有限公司 具有缩小间距的半导体元件及其形成方法
JP4016009B2 (ja) * 2004-03-24 2007-12-05 株式会社東芝 パターン形成方法及び半導体装置の製造方法
US20070052133A1 (en) * 2005-09-07 2007-03-08 Michael Gostkowski Methods for fabricating sub-resolution line space patterns
CN100426466C (zh) * 2006-02-24 2008-10-15 晶豪科技股份有限公司 形成具有缩小的字线间距的快闪单元阵列的方法
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
KR100914289B1 (ko) * 2007-10-26 2009-08-27 주식회사 하이닉스반도체 스페이서를 이용한 반도체 메모리소자의 패턴 형성방법
US20180323078A1 (en) * 2015-12-24 2018-11-08 Intel Corporation Pitch division using directed self-assembly
US10566194B2 (en) * 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning
CN116153781A (zh) * 2021-11-23 2023-05-23 上海华力集成电路制造有限公司 半导体鳍状结构截断工艺

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150826A (ja) * 1985-12-25 1987-07-04 Toshiba Corp 半導体装置の製造方法
JPH04207076A (ja) * 1990-11-30 1992-07-29 Toshiba Corp 固体撮像装置の製造方法
JPH04291758A (ja) * 1990-12-10 1992-10-15 Samsung Electron Co Ltd マスクプグラム方式の読出し専用メモリー装置の製造方法
JPH06232095A (ja) * 1993-01-29 1994-08-19 Sony Corp パターンの形成方法
JPH0786244A (ja) * 1993-09-13 1995-03-31 Sony Corp ドライエッチング方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4415383A (en) * 1982-05-10 1983-11-15 Northern Telecom Limited Method of fabricating semiconductor devices using laser annealing
JPH02283039A (ja) 1989-04-25 1990-11-20 Toshiba Corp 電荷転送装置と電荷転送装置の製造方法
US5580384A (en) 1989-09-22 1996-12-03 Balzers Aktiengesellschaft Method and apparatus for chemical coating on opposite surfaces of workpieces
EP0450091A4 (en) 1989-10-20 1993-12-22 Oki Electric Ind Co Ltd Method of producing semiconductor integrated circuit devices
US5420067A (en) 1990-09-28 1995-05-30 The United States Of America As Represented By The Secretary Of The Navy Method of fabricatring sub-half-micron trenches and holes
US5296410A (en) 1992-12-16 1994-03-22 Samsung Electronics Co., Ltd. Method for separating fine patterns of a semiconductor device
KR100366910B1 (ko) * 1994-04-05 2003-03-04 소니 가부시끼 가이샤 반도체장치의제조방법
US5667940A (en) 1994-05-11 1997-09-16 United Microelectronics Corporation Process for creating high density integrated circuits utilizing double coating photoresist mask
DE4445427C2 (de) 1994-12-20 1997-04-30 Schott Glaswerke Plasma-CVD-Verfahren zur Herstellung einer Gradientenschicht
US5541130A (en) 1995-06-07 1996-07-30 International Business Machines Corporation Process for making and programming a flash memory array
KR19980021248A (ko) * 1996-09-14 1998-06-25 김광호 반도체소자 미세패턴 형성방법
US6191034B1 (en) * 1997-05-30 2001-02-20 Advanced Micro Devices Forming minimal size spaces in integrated circuit conductive lines
US6180465B1 (en) * 1998-11-20 2001-01-30 Advanced Micro Devices Method of making high performance MOSFET with channel scaling mask feature
US6274445B1 (en) * 1999-02-03 2001-08-14 Philips Semi-Conductor, Inc. Method of manufacturing shallow source/drain junctions in a salicide process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150826A (ja) * 1985-12-25 1987-07-04 Toshiba Corp 半導体装置の製造方法
JPH04207076A (ja) * 1990-11-30 1992-07-29 Toshiba Corp 固体撮像装置の製造方法
JPH04291758A (ja) * 1990-12-10 1992-10-15 Samsung Electron Co Ltd マスクプグラム方式の読出し専用メモリー装置の製造方法
JPH06232095A (ja) * 1993-01-29 1994-08-19 Sony Corp パターンの形成方法
JPH0786244A (ja) * 1993-09-13 1995-03-31 Sony Corp ドライエッチング方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014112655A (ja) * 2012-10-30 2014-06-19 Dainippon Printing Co Ltd ナノインプリントモールドおよびその製造方法

Also Published As

Publication number Publication date
KR100682638B1 (ko) 2007-02-15
KR20010113838A (ko) 2001-12-28
EP1181714A1 (en) 2002-02-27
WO2000074121A1 (en) 2000-12-07
US6329124B1 (en) 2001-12-11

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