JP2003347302A - 信頼性向上のためのケイ化銅パッシベーション - Google Patents

信頼性向上のためのケイ化銅パッシベーション

Info

Publication number
JP2003347302A
JP2003347302A JP2003120807A JP2003120807A JP2003347302A JP 2003347302 A JP2003347302 A JP 2003347302A JP 2003120807 A JP2003120807 A JP 2003120807A JP 2003120807 A JP2003120807 A JP 2003120807A JP 2003347302 A JP2003347302 A JP 2003347302A
Authority
JP
Japan
Prior art keywords
copper
forming
interconnect structure
dielectric
copper silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003120807A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003347302A5 (https=
Inventor
Robert Wayne Bradshaw
ウエイン ブラッドシャウ ロバート
Daniele Gilkes
ギルキス ダニエル
Sailesh M Merchant
マンシン マーチャント サイレッシュ
Deepak A Ramappa
エー．ラマッパ デーパック
Kurt G Steiner
ジョージ ステイナー カート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of JP2003347302A publication Critical patent/JP2003347302A/ja
Publication of JP2003347302A5 publication Critical patent/JP2003347302A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0526—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by thermal treatment thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2003120807A 2002-04-26 2003-04-25 信頼性向上のためのケイ化銅パッシベーション Pending JP2003347302A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13378202A 2002-04-26 2002-04-26
US10/133782 2002-04-26

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010137862A Division JP2010232676A (ja) 2002-04-26 2010-06-17 信頼性向上のためのケイ化銅パッシベーション

Publications (2)

Publication Number Publication Date
JP2003347302A true JP2003347302A (ja) 2003-12-05
JP2003347302A5 JP2003347302A5 (https=) 2006-06-01

Family

ID=22460275

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2003120807A Pending JP2003347302A (ja) 2002-04-26 2003-04-25 信頼性向上のためのケイ化銅パッシベーション
JP2010137862A Withdrawn JP2010232676A (ja) 2002-04-26 2010-06-17 信頼性向上のためのケイ化銅パッシベーション

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2010137862A Withdrawn JP2010232676A (ja) 2002-04-26 2010-06-17 信頼性向上のためのケイ化銅パッシベーション

Country Status (4)

Country Link
JP (2) JP2003347302A (https=)
KR (1) KR101005434B1 (https=)
GB (1) GB2390742B (https=)
TW (1) TWI278963B (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109736A (ja) * 2005-10-11 2007-04-26 Nec Electronics Corp 半導体装置およびその製造方法
US8344509B2 (en) 2009-01-19 2013-01-01 Kabushiki Kaisha Toshiba Method for fabricating semiconductor device and semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101028811B1 (ko) * 2003-12-29 2011-04-12 매그나칩 반도체 유한회사 반도체 소자의 듀얼 다마신 패턴 형성 방법
US7229911B2 (en) 2004-04-19 2007-06-12 Applied Materials, Inc. Adhesion improvement for low k dielectrics to conductive materials
US20050233555A1 (en) * 2004-04-19 2005-10-20 Nagarajan Rajagopalan Adhesion improvement for low k dielectrics to conductive materials
US8884441B2 (en) 2013-02-18 2014-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Process of ultra thick trench etch with multi-slope profile
CN115295722B (zh) * 2022-06-07 2025-12-12 昕原半导体(杭州)有限公司 Rram下电极结构及其形成方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01103840A (ja) * 1987-10-16 1989-04-20 Sanyo Electric Co Ltd ドライエツチング方法
JPH04192527A (ja) * 1990-11-27 1992-07-10 Toshiba Corp 半導体装置
JPH11191556A (ja) * 1997-12-26 1999-07-13 Sony Corp 半導体装置の製造方法および銅または銅合金パターンの形成方法
JP2000058544A (ja) * 1998-08-04 2000-02-25 Matsushita Electron Corp 半導体装置及びその製造方法
JP2000195820A (ja) * 1998-12-25 2000-07-14 Sony Corp 金属窒化物膜の形成方法およびこれを用いた電子装置
JP2001185549A (ja) * 1999-12-24 2001-07-06 Toshiba Corp 半導体装置の製造方法
JP2001313285A (ja) * 2000-02-21 2001-11-09 Hitachi Ltd プラズマ処理装置及び試料の処理方法
JP2003045960A (ja) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447887A (en) * 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
JP3661366B2 (ja) * 1997-09-04 2005-06-15 ソニー株式会社 半導体装置及びその製造方法
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6406996B1 (en) * 2000-09-30 2002-06-18 Advanced Micro Devices, Inc. Sub-cap and method of manufacture therefor in integrated circuit capping layers
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01103840A (ja) * 1987-10-16 1989-04-20 Sanyo Electric Co Ltd ドライエツチング方法
JPH04192527A (ja) * 1990-11-27 1992-07-10 Toshiba Corp 半導体装置
JPH11191556A (ja) * 1997-12-26 1999-07-13 Sony Corp 半導体装置の製造方法および銅または銅合金パターンの形成方法
JP2000058544A (ja) * 1998-08-04 2000-02-25 Matsushita Electron Corp 半導体装置及びその製造方法
JP2000195820A (ja) * 1998-12-25 2000-07-14 Sony Corp 金属窒化物膜の形成方法およびこれを用いた電子装置
JP2001185549A (ja) * 1999-12-24 2001-07-06 Toshiba Corp 半導体装置の製造方法
JP2001313285A (ja) * 2000-02-21 2001-11-09 Hitachi Ltd プラズマ処理装置及び試料の処理方法
JP2003045960A (ja) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109736A (ja) * 2005-10-11 2007-04-26 Nec Electronics Corp 半導体装置およびその製造方法
US8344509B2 (en) 2009-01-19 2013-01-01 Kabushiki Kaisha Toshiba Method for fabricating semiconductor device and semiconductor device
US8536706B2 (en) 2009-01-19 2013-09-17 Kabushiki Kaisha Toshiba Method for fabricating semiconductor device and semiconductor device

Also Published As

Publication number Publication date
JP2010232676A (ja) 2010-10-14
GB2390742B (en) 2006-07-19
KR20030084761A (ko) 2003-11-01
GB2390742A (en) 2004-01-14
GB0309476D0 (en) 2003-06-04
KR101005434B1 (ko) 2011-01-05
TWI278963B (en) 2007-04-11
TW200408055A (en) 2004-05-16

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