1278963 玖、發明說明： 【發明所屬之技術領域】 本發明一般係關於半導體積體電路及其形成方法。更特 定言之，本發明係關於在半導體積體電路及類似物中抑制 銅擴散。 【先前技術】 在半導體積體電路裝置及相似物中使用銅互連特徵正在 變得越來越流行。通常使用鑲嵌處理方法形成銅互連特徵 ，如通道及互連引線（也稱作導線）。使用銅作為一互連材科 犯加快裝置速度，且與傳統使用如鋁及鋁合金等材科相比 ，銅互連特徵含有較少的電線電阻。然而，銅在金屬及介 電質中具有非常高的擴散速率，即使在低溫下也是如此: 鋼擴散能導致淺漏及失去可靠性。防止銅擴散及失去可, :的-個方法包括在通道、溝渠及其他開口内(傳統上在： 鑲後鋼互連結構）引進阻障材料，如包及氣化备。阻 :=鋼封裝在開口内。然而’在實爾操作以磨平 〜 在介電質内形成鑲嵌銅互連特徵後，卻曝露了上 的：表面。如果不將曝露的銅表面封裝或以 =上來自曝露的鋼表面的銅會擴散進入或 運，構上面形成的導電及/或介電材料。 電防止甸擴散之-傳統技術係在隨後另-介 該鋼表面上面月）/成銅結構上面之前’在整個結構上面（包括 甸）形成一氮化矽或碳化矽層。 碎層隨後必然成為該上覆介„ =切或碳化 且心 4分。該多層介 84992 1278963 4 遠负堆登明顯耑要額外處理操作以形成氮化碎或碳化碎層 。此外，銅擴散或電移可能出現在碳化矽/銅或氮化矽/銅介 面從而導致裝置可靠性降低。 因此，本技術需要一種方法及結構，以防止沿著銅/介電 質介面之銅電移及銅擴散進入並通過上方介電質及導電材 【發明内容】 本發明提供一種方法，其藉由將銅互連結構之曝露的鋼 表面轉化成銅矽化物來直接鈍化該表面。在該銅互連結構 上直接形成的薄銅矽化物層防止銅擴散及電移，並同時在 將該銅互連結構耦合至其他導電特徵而形成的接點内作為 -阻障層。在一項具體實施例中，該銅表面可在一原位順 序處理期間藉由矽烷鈍化，其中在該銅互連結構上面還形 成-上万介電層，如氮切或碳切。根據該項具體實施 例，可實施鈍化或銅矽化使得銅矽化物形成於該銅互連結 構之整個上表面。 在另-項示範性具體實施例中’本發明提供一上銅表面 、在該表面上形成-介電層、形成透過該介電層的一開口 從而曝露上銅表面之-部分’隨後藉由將其轉化成銅硬化 物材料而局部鈍化該上銅表面曝露的部分。 在另-項示範性具體實施例中，本發明提供—半導體產 品，其包括在-基板上形成的一銅互連結構及包括一上表 面，其中至少該上表面的-部分係藉切與銅互連結構上 的鋼結合而形成的銅碎化物。 84992 1278963 【實施方式】 本發明係提供一種鈍化方法，其藉由在一矽環境（如矽烷） 中，將銅表面的曝露部分轉化成一銅矽化物而將一銅互連 結構曝露的銅（Cu)表面鈍化。該鈍化過程也可稱為一碎化過 程。隨著矽滲入原先的銅表面並與其中的鋼結合，銅矽化 物得以形成。該銅矽化物用作防止銅從表面擴散進入任何 上方材料中，如上方導電材料及上方介電材料。銅矽化物 在一些區域内也作為金屬與金屬之間的阻障層，在該等區 域内銅互連結構與在銅矽化物區域内另一導電材料:接; 。由最初曝露的銅表面形《的銅碎化物也防止沿著該銅表 面與上方介電材料’如碳切、氮切、或各種低k介電材 料之間所形成的介面發生電移。碳切或氮切材料通常 形成在使用鑲嵌處理技術而形成的銅互連結構之上。此外 ，銅秒化物抑制堆積_。叫形成及改善對所形成薄膜之附 著以接觸銅互連結構之_匕物表面。藉由將銅表面曝露 於切化學品（如㈣）中而對銅表面實施的純化，可有益於 在原位與在銅互連結構上面形成氮化矽、碳化矽、或其他 介電質所用之處理操作一起實施。 本發明也提供銅表面曝露部分的局部純化。才艮據本項具 體實施例，在銅表面上㈣成—介電f，及為延伸透過該 介電質及曝露銅表面之一部分而形成一開口。隨後實施使 用該碎化學品的純化過程，將銅表面之曝露部分轉化成銅 梦化物。在該開口中可形成另一導電材料，其與作為阻障 層的銅妙化物區域接觸。此外，可選擇使用獨立形成的阻 84992 1278963 障層作為另-導電材料的一部分。在本項具體實施例中， 該銅碎化物區域作為一金屬與金屬之間擴散的阻障，並也 克服了在具有高縱橫比的開口内形成阻障層的相關問題。 儘管銅互連技術通常使用鑲嵌處理技術形成銅互連結構 ’如通道、互連線及類似物，但目前仍在開發使用與微影 蝕刻技術相結合的飯刻方法，將一表面上形成的銅薄膜圖 案化的技術。因而與在該項技術中使用的其他圖案化互連 材料相似，圖案化的銅包括一曝露的上表面，㈣露的側 壁、。本發明提供純化該圖案化的銅結構之所有曝露的表面 乂在已括側壁的所有表面形成銅矽化物，從而鈍化該銅 互連結構以防止沿著一介電層介面發生銅擴散及銅遷移， 这介電層係隨後形成在該圖案化的銅結構上。如在第一項 非局部聽具體實施財，原位純々化有益於在原位與 隨後的沈積一上方介電薄膜同時實施。 圖1係一使用鑲嵌技術形成的銅互連結構之斷面透視圖 。在圖1所說明的具體實施例中，該範例性銅互連結構係銅 互連引線10，其在基上縱向延伸並能提供橫向分隔特徵 之=接觸。銅互連引線10只作為範例，且在其他示範性 具體實施例中，根據本發明將鈍化/矽化的鋼結構可能為一 通道，或其他使用鑲嵌處理技術形成的導電結構。在另一 =示範性具體實施财，如在圖10及圖u中所^，可使用: 影姓刻圖案化及蝕刻的銅引線。 請繼續參照圖1，銅互連引線10形成於基板丨上面，更明 確地說，其形成於在介電材料9之内所形成的開口 7中。基 84992 1278963 ,1。可為由諸如矽、砷化鎵或其他適當材料所形成的半導體 晶圓。如在所述的該項具體實施例中所指定的，基板！也可 代表在β晶圓上形成的—介電層或其他層。介電材料9可為 一基於矽的介電質，如碳氧化矽(SiliC〇"xycarblde ; Si〇C-H)，可為一旋轉塗体芳香族碳（spin_〇n _* ㈣㈣’可為有機碎玻璃㈣跡仙如㈣㈣旧⑺可 為聚亞醯胺或磷矽玻璃（Ph〇sphate 3出_卬咖；ps⑺，或 任何與銅互連特徵一同使用的各種其他適當介電質。 在-項較佳具體實施例中，介電材料9為低k介電材料， 即’ 一介電常數小W.0的材料。在該項示範性說明的且於 實施例中，開口 7係在介電材料9内形成的—雙鑲嵌開口。 孩雙鑲嵌開口可使用傳統技術形&，並僅作為範例。在其 他示範性具體實施財，可使用—單鑲嵌結構並可包括^ 種形狀。儘管圖中所示之介電材料9為—單層，但介電材料 9可由^介電層構成。例如，一獨立介電層可與雙镶嵌開口 7之每-層對應。在另-項具體實施例中，介電材料9可為 -多層介電質堆疊，其中至少包括一硬光罩層，其可協助 形成孩π範性雙鑲彼（雙層）開口 7。圖中顯示開口 7延伸至人 電材料9的底層19及在基板！上面形成的下臥層23之接^ 分2!。這用於說明該項具體實施例’其中銅互連引線_ -通道相似’與一下臥組件電性接觸。這只作為範例，在 其他示範性具體實施例中，開口7可具有其他形狀，並可能 不向下延伸到底層19，反而可由介電材科9完全包圍。根2 該項說明性具體實施例，視鋼互連引線1〇的功能及結構情 84992 -10- 1278963 況’下队層23可為一硬光罩、一阻障層、一導電材料、一 介電材料或任何其他各種材料。根據另一項示範性具體實 施例，下臥層23亦可不存在。 在本說明性具體實施例中，銅互連引線1 〇係由塊狀銅部 分3及兩阻障層13及15形成。可使用傳統方法形成該等阻障 層及在其上面形成塊狀銅材料。該等阻障層從側面及下面 有效封裝銅互連引線10的塊狀銅部分3。在一項示範性具體 實施例中，下阻障層13可由鈕（Ti)形成，而上阻障層15可由 氮化鈕（TiN)形成。該等薄膜只作為範例，在其他示範性具 體實施中，可使用由鈦、氮化鈦、鎢及鈦鎢形成的其他阻 障層。根據其他示範性具體實施例，可使用各種矽化物作 為一阻障層。在各種示範性具體實施例中，只使用一單層 阻障層。根據另一項範例性具體實施例，可不包括阻障層 。圖1顯示使用拋光或其他合適的鑲嵌技術將該結構實質上 平面化並在開口 7内形成銅互連引線10後的結構。銅互連引 線10包括上表面12，其基本為平面並與介電材料9的頂表面 11共平面。上表面12包括上銅表面5及邊緣17，其由阻障層 形成。在可選擇阻障層及之後的塊狀銅材料3於開口 7中形 成後，可採用本技術中的各種拋光及其他技術來形成 所示的結構。 隨後將圖1中所示的結構鈍化以形成圖2中所示的結構。 根據本π範性具體實施例，上銅表面5的全部都得到曝露， 並使用本發明的鈍化/矽化過程，全部上銅表面5都實質上都 轉化成銅矽化物。該鈍化/矽化過程有利於在300至400乂 84992 -11 - 1278963 皿度範圍内使用一矽烷’並包括一流動速率(其範圍為3⑽ 至1，000 sccm)、一壓力（其範圍為t〇rr)、及射頻電漿 功率（其範圍13.56 MHz時為5〇至！，〇〇〇 watt)。根據一項示範 性具體實施例，該錢流動速率可大約為3〇〇3_，且該過 程可包括一 5torr的壓力、一 35〇〇c的溫度、5〇〇至 的射頻電漿功率。在其他示範性具體實施例中，可使用 其他碎來源的化學氣體。此外，上述數值僅為範例性數值1278963 发明, DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a semiconductor integrated circuit and a method of forming the same. More specifically, the present invention relates to suppression of copper diffusion in semiconductor integrated circuits and the like. [Prior Art] The use of copper interconnect features in semiconductor integrated circuit devices and the like is becoming more and more popular. Copper interconnect features, such as vias and interconnect leads (also referred to as wires), are typically formed using damascene processing. The use of copper as an interconnect material has speeded up the installation and has less wire resistance than conventional materials such as aluminum and aluminum alloys. However, copper has a very high diffusion rate in metals and dielectrics, even at low temperatures: steel diffusion can cause shallow leaks and loss of reliability. To prevent copper from spreading and losing, the method includes introducing barrier materials such as packages and gasification in channels, trenches and other openings (traditionally: inlaid steel interconnects). Resistance: = steel is enclosed in the opening. However, after the operation in the spiral to flatten ~ the formation of the inlaid copper interconnect features in the dielectric, but exposed: the surface. If the exposed copper surface is not encapsulated or the copper from the exposed steel surface is diffused into or transported, the conductive and/or dielectric material formed thereon is formed. The electricity prevents the diffusion of the dianthium - the conventional technique is to form a tantalum nitride or tantalum carbide layer on the entire structure (including the dynasty) before the upper surface of the steel surface. The shard layer is then bound to become the overlying layer „=cut or carbonized and the heart is 4 points. The multilayer slab 84992 1278963 4 is far from the stack and it is obvious that additional processing operations are required to form nitrided or carbonized fragments. In addition, copper diffusion or Electromigration may occur in tantalum carbide/copper or tantalum nitride/copper interfaces resulting in reduced device reliability. Therefore, the present technology requires a method and structure to prevent copper electromigration and copper diffusion along the copper/dielectric interface. Entering and Passing the Upper Dielectric and Conductive Material [Invention] The present invention provides a method for directly passivating the surface of the copper interconnect structure by converting the exposed steel surface into a copper telluride. The thin copper telluride layer formed directly thereon prevents copper from diffusing and electromigrating, and at the same time acts as a barrier layer in the junction formed by coupling the copper interconnect structure to other conductive features. In a specific embodiment, The copper surface may be passivated by decane during an in-situ sequential process, wherein a tens of thousands of dielectric layers, such as nitrogen cut or carbon cut, are also formed over the copper interconnect structure. According to this embodiment, passivation may be performed. Or copper bismuth such that a copper bismuth compound is formed over the entire upper surface of the copper interconnect structure. In another exemplary embodiment, the present invention provides an upper copper surface on which a dielectric layer is formed and formed through An opening of the dielectric layer to expose a portion of the copper surface is then partially inactivated by converting it to a copper hardened material. In another exemplary embodiment, The invention provides a semiconductor product comprising a copper interconnect structure formed on a substrate and including an upper surface, wherein at least a portion of the upper surface is formed by cutting a copper bond with a steel on the copper interconnect structure 84992 1278963 [Embodiment] The present invention provides a passivation method for exposing copper to a copper interconnect structure by converting an exposed portion of the copper surface into a copper telluride in an atmosphere such as decane. (Cu) Surface passivation. This passivation process can also be referred to as a fragmentation process. As the tantalum penetrates into the original copper surface and bonds with the steel therein, the copper telluride is formed. Copper diffuses from the surface into any of the upper materials, such as the upper conductive material and the upper dielectric material. The copper telluride also acts as a barrier between metal and metal in some areas, in which the copper interconnect structure Another conductive material in the copper telluride region: the copper surface of the initially exposed copper surface is also prevented from along the copper surface and the upper dielectric material such as carbon cut, nitrogen cut, or various low-k The interface formed between the electrical materials is electrically shifted. The carbon-cut or nitrogen-cut material is usually formed on a copper interconnect structure formed using a damascene process. In addition, the copper-secondary compound inhibits the build-up. Forming the adhesion of the film to contact the surface of the copper interconnect structure. Purification of the copper surface by exposing the copper surface to a dicing chemical (eg, (iv)) may be beneficial in situ and in copper interconnect The processing operations used to form tantalum nitride, tantalum carbide, or other dielectrics on the structure are implemented together. The present invention also provides for local purification of copper surface exposed portions. According to a specific embodiment of the present invention, an opening is formed on the copper surface by (four) forming a dielectric f and extending through the dielectric and a portion of the exposed copper surface. A purification process using the shredded chemical is then carried out to convert the exposed portion of the copper surface to a copper dream compound. Another conductive material may be formed in the opening in contact with the copper region as the barrier layer. In addition, a separately formed barrier 84992 1278963 barrier layer can be optionally used as part of the other conductive material. In this embodiment, the copper clastic region acts as a barrier to diffusion between the metal and the metal, and also overcomes the problems associated with forming a barrier layer in an opening having a high aspect ratio. Although copper interconnect technology typically uses damascene processing techniques to form copper interconnect structures such as vias, interconnects, and the like, it is still being developed to use a meal engraving method combined with lithography to form a surface. Copper film patterning technology. Thus, similar to other patterned interconnect materials used in the art, the patterned copper includes an exposed upper surface and (iv) exposed side walls. The present invention provides for the purification of all exposed surfaces of the patterned copper structure, the formation of copper telluride on all surfaces of the included sidewalls, thereby passivating the copper interconnect structure to prevent copper diffusion and copper migration along a dielectric layer interface The dielectric layer is then formed on the patterned copper structure. In the first non-local listening implementation, in-situ pure deuteration is beneficial for simultaneous deposition in situ with subsequent deposition of an upper dielectric film. Figure 1 is a cross-sectional perspective view of a copper interconnect structure formed using a damascene technique. In the particular embodiment illustrated in Figure 1, the exemplary copper interconnect structure is a copper interconnect lead 10 that extends longitudinally over the substrate and provides lateral contact features = contact. The copper interconnect leads 10 are merely exemplary, and in other exemplary embodiments, the passivated/deuterated steel structure may be a channel, or other conductive structure formed using damascene processing techniques, in accordance with the present invention. In another = exemplary implementation, as shown in Figures 10 and u, a copper lead patterned and etched can be used. With continued reference to Figure 1, a copper interconnect lead 10 is formed over the substrate stack, more specifically, formed in the opening 7 formed within the dielectric material 9. Base 84992 1278963, 1. It may be a semiconductor wafer formed of, for example, germanium, gallium arsenide or other suitable material. As specified in the specific embodiment described, the substrate! It can also represent a dielectric layer or other layer formed on a beta wafer. The dielectric material 9 can be a germanium-based dielectric such as bismuth carbon dioxide (SiliC〇"xycarblde; Si〇CH), which can be a rotating coating of aromatic carbon (spin_〇n _* (four) (four)' can be Organic cullet (4) Traces such as (4) (4) Old (7) may be polyamidamine or phosphonium glass (Ph〇sphate 3 _ 卬 coffee; ps (7), or any other suitable dielectric used with copper interconnect features. In a preferred embodiment, the dielectric material 9 is a low-k dielectric material, ie, a material having a small dielectric constant of W.0. In the exemplary embodiment of the item and in the embodiment, the opening 7 is The dual damascene opening formed in the dielectric material 9. The double inlaid opening can be made using conventional techniques and is merely exemplary. In other exemplary implementations, a single damascene structure can be used and can include a variety of shapes. Although the dielectric material 9 is shown as a single layer, the dielectric material 9 can be formed of a dielectric layer. For example, an independent dielectric layer can correspond to each of the layers of the dual damascene opening 7. In a specific embodiment, the dielectric material 9 can be a multi-layer dielectric stack including at least one hard mask layer It can assist in the formation of a double-inlaid (double-layer) opening 7. The opening 7 extends to the bottom layer 19 of the human electrical material 9 and the lower layer 23 of the lower layer 23 formed on the substrate! This is used to illustrate that the specific embodiment 'where the copper interconnect leads _ - channel is similar' is in electrical contact with the underlying component. This is by way of example only, in other exemplary embodiments, the opening 7 may have other shapes and It may not extend down to the bottom layer 19, but may be completely surrounded by the dielectric material section 9. Root 2 This illustrative embodiment, the function and structure of the steel interconnecting lead 1〇84992 -10- 1278963 Layer 23 can be a hard mask, a barrier layer, a conductive material, a dielectric material, or any other variety of materials. According to another exemplary embodiment, lower layer 23 may also be absent. In a specific embodiment, the copper interconnect leads 1 are formed of a bulk copper portion 3 and two barrier layers 13 and 15. These barrier layers can be formed using conventional methods and formed into a bulk copper material thereon. The barrier layer effectively encapsulates copper interconnects from the side and below The bulk copper portion 3 of 10. In an exemplary embodiment, the lower barrier layer 13 may be formed of a button (Ti), and the upper barrier layer 15 may be formed of a nitride button (TiN). For example, in other exemplary implementations, other barrier layers formed of titanium, titanium nitride, tungsten, and titanium tungsten may be used. According to other exemplary embodiments, various tellurides may be used as a barrier layer. In various exemplary embodiments, only a single layer of barrier layer is used. According to another exemplary embodiment, the barrier layer may not be included. Figure 1 shows the structure being substantially planar using polishing or other suitable damascene techniques. The structure after the copper interconnect lead 10 is formed in the opening 7 is formed. The copper interconnect lead 10 includes an upper surface 12 that is substantially planar and coplanar with the top surface 11 of the dielectric material 9. The upper surface 12 includes an upper copper surface 5 and an edge 17 formed of a barrier layer. After the optional barrier layer and the subsequent bulk copper material 3 are formed in the opening 7, various polishing and other techniques in the art can be employed to form the illustrated structure. The structure shown in Figure 1 is then passivated to form the structure shown in Figure 2. According to the present embodiment of the present invention, all of the upper copper surface 5 is exposed, and using the passivation/deuteration process of the present invention, all of the upper copper surface 5 is substantially converted into copper telluride. The passivation/deuteration process facilitates the use of monooxane in the range of 300 to 400 乂 84092 -11 - 1278963 and includes a flow rate (ranging from 3 (10) to 1,000 sccm) and a pressure (the range is t〇) Rr), and RF plasma power (5 〇 to !, 〇〇〇 watt for the range 13.56 MHz). According to an exemplary embodiment, the money flow rate may be approximately 3 〇〇 3 _, and the process may include a pressure of 5 torr, a temperature of 35 〇〇 c, and a radio frequency plasma power of 5 〇〇. In other exemplary embodiments, other sources of chemical gases may be used. In addition, the above values are only exemplary values.
’且根據其他示範性具體實施例，可使用不同的程序參數 組口，藉由使電漿化學品中的矽滲入曝露的銅表面並與其 中的銅反應’將上銅表面5曝露的部分轉化成銅矽化物。可 形成鋼$彳匕物的各種相態。熟知此技術之人士明白，碎化 心度b Ik著時間之增加而增加。在—項具體實施例中，實 施該過程的時間範圍為5至2〇分，但根據需要的矽化程度也 可採用其他的處理時間。And according to other exemplary embodiments, different program parameter sets may be used to convert the exposed portion of the copper surface 5 by infiltrating the ruthenium in the plasma chemical into the exposed copper surface and reacting with the copper therein. Copper bismuth compound. It can form various phases of steel $彳匕. Those skilled in the art understand that the shredded heart rate increases with an increase in time. In the specific embodiment, the time period for carrying out the process is 5 to 2 minutes, but other processing times may be employed depending on the degree of deuteration required.
圖2顯示圖1的結構在整個曝露的上銅表面5(如圖丨所示） 實質上已經全邵轉化成銅矽化物表面25後的情形。在其他 具體實施例中，至少上銅表面5之曝露區域的一部分轉化成 為銅矽化物表面25。與原Cu表面5相比，銅矽化物表面以為 表面積增加的粗糙表面，並且基本不含有不應有的氧化 銅。增加的表面積改善了對在銅矽化物表面25上面形成並 入/、接觸之薄膜的黏著。銅碎化物表面2 5也具有抑制在銅 互連引線1 0中形成堆積之優點。 圖2 A係已轉化成銅矽化物之原銅表面的一展開斷面圖。 圖2A顯示在圖〗中顯示的原上銅表面$轉化成銅矽化物表面 84992 -12- 1278963 25，其包括侵入塊狀銅材料3的鋼碎化物29。㈣化物⑼戈 表銅互連引線1〇轉化後的一部分，其切渗入原上銅表面 並^其中的銅結合形成銅秒化物。該過程參數之選擇要確 保藉由來自㈣或其他碎氣體化學品㈣形成銅碎化物， 其渗入原上鋼表面5,並與Cu結合，進而將該表面之上部分 轉化成銅矽化物29。鋼矽化物29可包括一厚度31，其範圍 為20至2GG埃，但也可採用其他厚度。熟知本技術之人會明 白，可改變處理溫度及處理過程持續時間來控制銅秒化物 29之厚度31。厚度31可與需要的矽化程度一同選擇，其要 足夠厚以防止來自銅互連結構的銅擴散，但又不能太厚， 以使互連引線10中銅之薄層電阻的增加幅度最小。在所述 具體實施例中顯示的銅矽化物表面25係一粗糙及不規則表 面。該粗糙及不規則的表面提供额外表面積，其會改善對 上面形成的薄膜的黏著 。 可選擇在35〇cC至400。(：的溫度範圍執行一短時間退火過 心，以降低銅互連引線的薄層電阻及降低銅矽化物表面Μ 與任何為與銅矽化物表面25接觸而形成的其他導電材料之 間的接觸電阻。該可選擇的退火包括秒或分等級的一退火 時間。咸信因為短時間退火改變了最初形成的該銅矽化物 的相態及/或因為矽過量會引起形成额外的銅矽化物，故可 以實現降低該薄層/接觸電阻。該退火過程可包括氮氣或其 他惰性氣體。根據其他示範性具體實施例，可不採用該退 火過程。 圖2顯示銅碎化物表面2 5形成後的結構。根據一項示範性 84992 • 13 · 1278963 具體實施例，該結構可以為一中間結構，作為本發明一優 點係本發明的鈍化/矽化可在原位且與隨後在該結構上面形 成另外一薄膜一同進行。該另一薄膜可為用於形成一上覆 介電堆疊的各種介電薄膜之任一薄膜’根據一項示範性具 體實施例，在孩表面直接生成的第一層可為一氮化矽薄膜 ，或使用矽化/鈍化過程在原位形成的一碳化矽薄膜。 圖3係一斷面圖，其顯示在與圖2所示結構大體相同的結 構上形成的上介電層35，其不同點是，為清晰起見，已將 下臥層2 3、阻障層1 3及1 5移除。因此應明白，儘管沒有說 明，但該等特徵可包括在各種具體實施例中，如所述的具 體貫施例。上介電層35形成於上表面丨丨及銅矽化物表面以 之上，如上所述，該銅矽化物表面包括銅矽化物29。上介 電層35可以為一單層介電薄膜或其可代表一介電層的堆疊 ，其中一部分或全部皆為使用該矽化/鈍化過程在原位形成 。可使用低k介電材料及基於Si的材料，該等介電材料可以 為與圖1中介電材料9一道說明的介電材料。在一項示範性 具體實施例中，上介電層35可以為多個單層的複合或堆疊 。上介電層35可藉由虛線分開的35八與35B兩層構成。根據 該項示範性具體實施例，介電層35八可以為氮化矽或碳化矽 ，而介電層35B可以為一低k介電材料。這僅作為範例，而 在其他不範性具體實施例中，可使用不同數量的各種介電 薄膜形成上介電層35。上介電層35可包括一層或數層硬2 罩薄膜。本發明的一個方面係改善了矽化的銅矽化物表面 25與上介電層35之間的黏著，特別是當與矽化的銅矽化物 84992 -14- 1278963 表面25接觸的介電層為氮化矽或碳化矽時。 圖4顯示圖3中的結構，其中已經形成_示範性㈣μ 39，以穿過在上介電層35中形成的開口㈣底部與銅互連 引線ίο的銅矽化物表面25相接觸。開口41延伸到上介電層 h的底部，並將㈣化物表面25的區段51曝露。在該項: 範性具體實施例中，開口41係„雙鑲嵌開口，但在其他具 體實施例中，可以用其他開口，以提供與銅互連引線㈣ 銅矽化物表面25的接觸。開口41僅曝露了銅矽化物表面25 的:部分。銅矽化物表面25的其他部分仍藉由上介電層h 覆蓋（其在圖5中顯示得更清楚）。導電結構”包括可選擇的 阻障層43及45與塊狀導電材料47。可選擇的阻障層43及45 與結合銅互連引線10一道說明的阻障層13及15相似，而塊 狀導電材料47可以為銅或其他適當的導電材料。根據一項 示範性具體實施例，本發明的一項優點為由於銅矽化物表 面25作為在銅互連引線1〇及導電結構39之間的擴散阻障層 ，故不需要可選擇的阻障層43及45。根據所說明的示範性 具體實施例，導電結構39係一鑲嵌結構，其包括一平面化 的頂表面49，該頂表面49實質上與上介電層35的頂表面” 共平面。在其他示範性具體實施例中，可使用其他各種鑲 嵌與非鑲嵌導電結構接觸銅矽化物表面25。 圖5係一平面圖，其顯示在銅互連引線1〇上面形成並與其 接觸的上導電結構3 9 ,如圖4所示。在該項示範性具體實施 例中’導電結構39係在一開口内部（圖4中所示的開口 41)形 成的一通道，其接觸銅互連引線1〇的銅矽化物表面25之區 84992 -15- 1278963 段51。銅碎化物表面25的其他部分藉由上介電層35覆蓋。 圖5中沒有圖示可選擇阻障層43及45。 根據所述示範性具體實施例，銅互連引線丨〇為一互連引 、泉’其在一横穿過該裝置延伸的長溝渠内延伸，導電結構 為通道’但根據其他示範性實施例，也可以使用其他 -置例如，在一項示範性具體實施例中，該上部鑲欲互 連結構延伸到其從中形成的該介電層的底部，根據該項示 範性具體實施例，可以在以大體垂直關係相互穿越的兩互 連結構之間形成接觸。此外，根據其他示範性具體實施例 ’該上互連結構可為一非鑲嵌結構。 本發明之另一項具體實施例為一曝露的銅表面之局部矽 化圖6係在介電材料9之内形成的一示範性銅互連引線j 〇 的一斷面圖。第二介電層61形成在上銅表面5及介電材料9 的頂表面11之上。如前面所述，第二介電層61可為各種材料 或材料層堆疊的任一層。例如，第二介電層61可包括或僅 由基於矽的低k介電層形成且至少包括一硬光罩層。形成開 口 65係為穿過第二介電層61延伸並將上銅表面$之區段67 曝露出來。儘管所示的示範性開口 6 5係一雙鑲嵌開口，但 在其他示範性具體實施例中，仍可形成各種其他開口。隨 後根據上述鈍化/矽化過程，可將銅互連引線丨〇的上鋼表面5 曝露的區段67鈍化。鈍化/矽化過程係在圖6所示的結構上面 實施’以形成圖7所示的結構。 圖7顯示局邵銅矽化物表面2 5，其形成在銅互連引線丨〇之 原銅上表面之曝露的區段67内。上銅表面5之其他未曝露的 84992 -16 - 1278963 邵分不純化。隨奢碎滲入原銅上表面並與銅互連引線1 〇的 銅結合，形成銅矽化物29並侵蝕Cu互連引線10，以將上銅 表面5之曝露的區段67中的銅轉化成銅矽化物29。在該項具 體實施例中，局部銅矽化物29可作為銅互連引線1〇及一隨 後形成的與銅互連引線1 〇接觸的一導電結構之間的阻障層 。這可克服在開口 65内形成一連續阻障層薄膜的缺點以與 銅互連引線10接觸。根據開口 65具有一高縱橫比的示範性 具體實施例，使用傳統方法形成的阻障層薄膜傾向於不連 續並在開口内產生空洞區域。 圖8係圖7中所不的結構之平面圖。圖8顯示一示範性雙鑲 歆開口 65，其將用於形成在銅互連引線1〇之上對齊的一通 道。局部銅矽化物表面25實質上只形成在區段67内，即轉 化成銅矽化物之銅互連引線10之原上銅表面5的曝露部分 。上銅表面5未曝露及局部矽化的其他部分仍保持為未轉化 的銅。隨後，以此方式，圖7斷面圖中所示的第二介電層61 覆蓋上銅表面5並包括開口 65，透過開口65 •5之區段㈣露，此時只有區段67中的原上銅表面5=: 成銅矽化物表面25。因此開口65界定轉化成銅矽化物的該 上銅表面的局部部分。 圖9顯示上導電結構7卜其形成於開㈣之内以在區段^ 處與局部財化物表面25接觸。上導電結構71包括塊狀導 電材料77並可使用傳統方法形成。塊狀導電材㈣可為銅 、鋁或其他適當導電材料。在說明的具體實施例中，上導 電結構7!係一通道，並可使用鑲嵌過程形成，使頂表面81 84992 -17- 1278963 基本上與第二介電層61之上表面㈧丑正二 ^ 上衣面69共千面。根據其他示範 性具體實施例’上導電結構71可為任何其他鑲嵌結構，如 -與銅梦化物表面25接觸的互連引線。根據另—項示範性 具體實施例’可形成-非鑲嵌結構以填充開口65,該開口 界定轉化成銅矽化物表面25之原上銅表面5之局部部分（區 段67)。因此，本發明的一項優點係可在銅互連引線ι〇與上 導電結構71之間形成一阻障層（銅矽化物29)，而不必將一薄 膜沈積於-開口中，如具有—高縱橫比的開口 65，因而難 以在該開π中形成-連續阻障層。在其他示範性具體實施 例中，额外的阻障層可與銅矽化物29 一同使用。 圖10係在層101之表面103上面形成的鋼互連導線1〇5之 透视斷面圖。層101可為一介電層，或在一基板上或其他半 導體結構上形成的其他層。銅互連導線1〇5可使用各種技術 形成，如微影蝕刻及本技術中正在開發的圖案化與蝕刻程 序。可以預計，將會繼續開發本技術中圖案化及蝕刻銅之 改良方法。圖案化的銅互連導線105包括頂表面1〇7及側壁 1〇9，其均由銅構成。 如上所述，本發明之矽化/鈍化過程有利於用於鈍化銅互 連導線1 05之曝露表面（頂表面107及側壁！ 〇9)。作為純化過 程之結果，銅互連導線105的側壁及頂表面轉化成銅矽化 物。 圖Π顯示轉化後的側壁119及轉化後的頂表面117，其現已 為銅碎化物表面，包括在先前具體實施例中顯示及論述的 銅碎化物。由於銅矽化物表面Π 9及117抑制外擴散 84992 -18- 1278963 (〇Ut-diffusion)，因此圖！】令所示的硬化後的結構具有減少 來自銅互連導線Π)5之銅擴散的優點。銅_化物表面ιΐ7及 119也抑制銅沿著銅互連導線105與其上面形成的介電材料 或其他材料之間形成的邊界電遷移。由於銅矽化物，隨後 形成的材料’特別是氮切及碳切與鋼互連導線ι〇5的黏 著得到改善。堆積的形成也得到抑制。可形成各種導電材 料（包括可選擇的阻障層）’以與於碎化物表面Μ及ιΐ9内形 成的銅秒化物區域接觸。在其他具體實施例中，由於銅互 連導線H)5之糾化物表面起著阻障材料的作用，因此不使 用额外的阻障層。 以上所述僅說明本發明之原理。因此應明瞭，熟悉技術 人士 Γ设计出各種各樣的配置以具體化本發明之原理，雖 然該等配置並未在本文中明確說明或顯示，但係包含在本 卷月〈和精神中。而且，此中提及的所有範例和條件 語句主要係旨在僅用於教導目的，並f助理解本發明之原 里及發明者為推進技術所提出的概念，因此應理解本發明 、'不侷限所提及的具體範例和條件。此外，&中所有提 發明之原理、觀點及具體實施例的敘述，及其中的具 :知例係、曰在涵盖所有其結構和功能等效者。並且該等 等效者不僅包含目前既有者，亦包含未來開發之等效者， P不論其結構’但執行相同功能的所開發之任何元件。因 、本發明〈範轉不限於本文所示&所述的示ϋ性具體實 、例而疋具體化在隨附的申請專利範圍中。 【圖式簡單說明】 84992 -19. 1278963 從以上結合隨附圖式閱為 阅嗔本發明之詳細說明即可更好瞭 解本發明。需強調指出， 、 、 根據通行的做法，圖式的各種特 徵並非按比例输製。盘夕 、 相反’為清楚起見，各種特徵的 尺寸文〜放大或、%小。在所有圖式及說明書中，相同的數 字表示相同的元件。圖式中包含如下圖式： 圖1係-項示範性鑲嵌銅互連引線之斷面透視圖； 圖2顯示圖1的結構在曝露的銅表面已經轉化成銅碎化物 後的情形； 圖2A係圖2中-部分的展開斷面圖； 圖3係-斷面圖，其顯示在純化後的銅碎化物表面上形成 的一介電材料； 回·、斷面圖，其顯示在圖3所示的鈍化後的矽化銅表 面上形成的導電結構； 圖5係一平面圖，其顯示在銅互連引線上形成的一示範性 導電結構； 圖係if面圖，其顯示透過一介電質而形成的一開口且 曝露出邵分鋼表面； 圖7顯示圖6所顯示的結構，其已完成了梦化曝露的銅表 面的純化過程； 0系平面圖，其顯示銅互連導線之局部碎化區域； 圖9係-斷面圖，其顯示在圖7所示的開口中形成的導電 鑲嵌結構； 圖1 〇係在表面之上形成的銅導線之斷面透視圖；及 圖11顯示圖10中的結構，其中曝露的鋼表面上已形成銅碎 84992 -20- 1278963 化物。 【圖式代表符號說明】 1 基板 3 塊狀銅部分 5 上銅表面 7 開口 9 介電材料 10 銅互連引線 11 頂表面 12 上表面 13 阻障層 15 阻障層 17 邊緣 19 底層 21 接觸部分 23 下臥層 25 矽化銅表面 29 矽化銅 31 厚度 35 上介電層 35A 層 35B 層 37 頂表面 39 示範性導電i 84992 開口 可選擇阻障層 可選擇阻障層 塊狀導電材料 頂表面 區段 第二介電層 開口 區段 上表面 上導電結構 導電材料 頂表面 層 表面 銅互連導線 頂表面 側壁 轉化後的頂表面 轉化後的側壁 -22-2 shows the structure of FIG. 1 after the entire exposed upper copper surface 5 (shown in FIG. )) has substantially been completely converted into the copper telluride surface 25. In other embodiments, at least a portion of the exposed area of the upper copper surface 5 is converted to a copper telluride surface 25. Compared to the original Cu surface 5, the copper telluride surface is a rough surface with an increased surface area and is substantially free of oxidized copper which is not desirable. The increased surface area improves the adhesion to the film formed on/in contact with the copper telluride surface 25. The copper clastic surface 25 also has the advantage of inhibiting the formation of a buildup in the copper interconnect leads 10. Figure 2A is an expanded cross-sectional view of the surface of the original copper that has been converted to copper telluride. Figure 2A shows the original copper surface $ shown in the figure converted into a copper telluride surface 84992 -12 - 1278963 25 comprising a steel fragment 29 invading the bulk copper material 3. (4) The compound (9) is a part of the copper interconnecting lead which is transformed, and which is cut into the original copper surface and copper is combined to form a copper second compound. The process parameters are selected to ensure that copper fragments are formed by (iv) or other particulate chemicals (4) which penetrate into the original steel surface 5 and combine with Cu to convert a portion of the surface to copper bismuth 29. The steel telluride 29 can comprise a thickness 31 ranging from 20 to 2 GG, although other thicknesses can be used. Those skilled in the art will appreciate that the processing temperature and duration of the process can be varied to control the thickness 31 of the copper second. The thickness 31 can be selected along with the desired degree of deuteration, which is thick enough to prevent copper diffusion from the copper interconnect structure, but not too thick to minimize the increase in sheet resistance of copper in interconnect lead 10. The copper telluride surface 25 shown in the specific embodiment is a rough and irregular surface. The rough and irregular surface provides an additional surface area which improves adhesion to the film formed thereon. Choose from 35〇cC to 400. The temperature range of (: is performed for a short time to anneal to reduce the sheet resistance of the copper interconnect leads and to reduce the contact between the copper telluride surface Μ and any other conductive material formed in contact with the copper telluride surface 25. The optional annealing comprises a second or a grade of annealing time. The short-time annealing changes the phase of the initially formed copper telluride and/or the formation of additional copper telluride due to excessive amounts of germanium. This thin layer/contact resistance can be achieved. The annealing process can include nitrogen or other inert gas. According to other exemplary embodiments, the annealing process may not be employed. Figure 2 shows the structure after the formation of the copper fragmentation surface 25. According to an exemplary embodiment of 84992 • 13 1278963, the structure may be an intermediate structure. As an advantage of the present invention, the passivation/deuteration of the present invention may be in situ and along with subsequent formation of another film on the structure. The other film may be any film of various dielectric films used to form an overlying dielectric stack, according to an exemplary specific For example, the first layer directly formed on the surface of the child may be a tantalum nitride film, or a tantalum carbide film formed in situ using a deuteration/passivation process. FIG. 3 is a cross-sectional view, which is shown in FIG. The upper dielectric layer 35 is formed on substantially the same structure as shown, with the difference that the underlying layer 23, the barrier layers 13 and 15 have been removed for clarity. Therefore, it should be understood that although Not stated, but such features may be included in various embodiments, such as the specific embodiments described above. The upper dielectric layer 35 is formed over the upper surface and the copper telluride surface, as described above, The copper telluride surface comprises a copper telluride 29. The upper dielectric layer 35 can be a single dielectric film or a stack thereof that can represent a dielectric layer, some or all of which are formed in situ using the deuteration/passivation process. Low-k dielectric materials and Si-based materials may be used, which may be dielectric materials illustrated with the dielectric material 9 of Figure 1. In an exemplary embodiment, the upper dielectric layer 35 Can be a composite or stack of multiple single layers. The upper dielectric layer 35 can be The lines are separated by two layers of 35 and 35B. According to this exemplary embodiment, the dielectric layer 35 may be tantalum nitride or tantalum carbide, and the dielectric layer 35B may be a low-k dielectric material. As an example, in other non-standard embodiments, a different number of various dielectric films may be used to form the upper dielectric layer 35. The upper dielectric layer 35 may include one or more layers of hard mask film. One of the present inventions The aspect improves the adhesion between the deuterated copper telluride surface 25 and the upper dielectric layer 35, particularly when the dielectric layer in contact with the surface 25 of the deuterated copper telluride 84992 -14-1278963 is tantalum nitride or tantalum carbide. 4 shows the structure of FIG. 3 in which an exemplary (four) μ 39 has been formed to contact the copper telluride surface 25 of the copper interconnect lead through the bottom of the opening (four) formed in the upper dielectric layer 35. The opening 41 extends to the bottom of the upper dielectric layer h and exposes the section 51 of the (four) compound surface 25. In this: a specific embodiment, the opening 41 is a "double damascene opening, but in other embodiments, other openings may be used to provide contact with the copper interconnecting lead (4) copper telluride surface 25. Opening 41 Only the portion of the copper telluride surface 25 is exposed. The other portions of the copper telluride surface 25 are still covered by the upper dielectric layer h (which is shown more clearly in Figure 5). The conductive structure" includes optional barriers. Layers 43 and 45 and bulk conductive material 47. The optional barrier layers 43 and 45 are similar to the barrier layers 13 and 15 illustrated in conjunction with the copper interconnect leads 10, and the bulk conductive material 47 can be copper or other suitable electrically conductive material. According to an exemplary embodiment, an advantage of the present invention is that since the copper telluride surface 25 acts as a diffusion barrier between the copper interconnect leads 1 and the conductive structure 39, no optional barrier is required. Layers 43 and 45. In accordance with the illustrated exemplary embodiment, the electrically conductive structure 39 is a damascene structure that includes a planarized top surface 49 that is substantially coplanar with the top surface of the upper dielectric layer 35. In other demonstrations In other embodiments, a variety of other damascene and non-inlaid conductive structures can be used to contact the copper telluride surface 25. Figure 5 is a plan view showing the upper conductive structure 39 formed over and in contact with the copper interconnect leads 1 As shown in Fig. 4, in the exemplary embodiment, the conductive structure 39 is formed in a channel formed inside the opening (the opening 41 shown in Fig. 4), which contacts the copper interconnect of the copper interconnect lead 1〇. The region of the object surface 25 is in the range of 84992 -15 - 1278963 segment 51. The other portions of the copper-decomposed surface 25 are covered by the upper dielectric layer 35. The optional barrier layers 43 and 45 are not illustrated in Figure 5. According to the exemplary In a specific embodiment, the copper interconnecting leads are an interconnecting spring that extends in a long trench extending across the device, the conductive structure being a channel 'but other embodiments may be used, but other embodiments may be used - set, for example, in one In an exemplary embodiment, the upper inlaid interconnect structure extends to the bottom of the dielectric layer from which it is formed, according to the exemplary embodiment, two interconnect structures that can traverse each other in a generally vertical relationship In addition, according to other exemplary embodiments, the upper interconnect structure may be a non-mosaic structure. Another embodiment of the present invention is a partial deuteration of an exposed copper surface. FIG. 6 is a dielectric A cross-sectional view of an exemplary copper interconnect lead j 形成 formed within material 9. A second dielectric layer 61 is formed over the upper copper surface 5 and the top surface 11 of the dielectric material 9. As previously described, The second dielectric layer 61 can be any layer of various material or material layer stacks. For example, the second dielectric layer 61 can comprise or consist only of a germanium-based low-k dielectric layer and include at least one hard mask layer. The opening 65 extends through the second dielectric layer 61 and exposes the upper copper surface $ section 67. Although the exemplary opening 65 is shown as a dual damascene opening, in other exemplary embodiments , can still form a variety of other openings. With Thereafter, according to the passivation/deuteration process described above, the exposed portion 67 of the upper steel surface 5 of the copper interconnect lead turns can be passivated. The passivation/deuteration process is performed on the structure shown in FIG. 6 to form the structure shown in FIG. Figure 7 shows a localized copper bismuth telluride surface 25 formed in the exposed portion 67 of the upper copper surface of the copper interconnect lead 。. The other unexposed 84992 -16 - 1278963 of the upper copper surface 5 The fraction is not purified. It is infiltrated into the upper surface of the original copper and bonded to the copper interconnect lead 1 , copper to form a copper telluride 29 and erode the Cu interconnect lead 10 to expose the exposed portion of the upper copper surface 5 The copper in the conversion is converted to copper telluride 29. In this embodiment, the localized copper telluride 29 can serve as a copper interconnect lead 1 and a subsequently formed conductive structure in contact with the copper interconnect lead 1 〇 The barrier layer. This overcomes the disadvantage of forming a continuous barrier film within opening 65 to contact copper interconnect leads 10. Depending on the exemplary embodiment in which the opening 65 has a high aspect ratio, the barrier film formed using conventional methods tends to be discontinuous and create void regions within the opening. Figure 8 is a plan view of the structure of Figure 7. Figure 8 shows an exemplary dual damascene opening 65 that will be used to form a channel aligned over the copper interconnect leads 1〇. The localized copper telluride surface 25 is formed substantially only within the segment 67, i.e., the exposed portion of the copper surface 5 of the copper interconnect 5 that is converted to copper bismuth. The other portions of the upper copper surface 5 that were not exposed and partially deuterated remained as unconverted copper. Subsequently, in this manner, the second dielectric layer 61 shown in the cross-sectional view of FIG. 7 covers the copper surface 5 and includes an opening 65 through which the section (4) of the opening 65·5 is exposed, at this time only in the section 67 The original copper surface 5 =: into the copper halide surface 25. Thus opening 65 defines a local portion of the upper copper surface that is converted to copper bismuth. Figure 9 shows the upper conductive structure 7 formed within the opening (4) to contact the localized material surface 25 at the section ^. The upper conductive structure 71 includes a bulk conductive material 77 and can be formed using a conventional method. The bulk conductive material (4) may be copper, aluminum or other suitable electrically conductive material. In the illustrated embodiment, the upper conductive structure 7 is a channel and can be formed using a damascene process such that the top surface 81 84992 -17-1278963 is substantially opposite the upper surface of the second dielectric layer 61 (eight) ugly two tops Face 69 has a total of thousands of faces. The upper conductive structure 71 can be any other damascene structure, such as interconnecting leads that are in contact with the copper dreaming surface 25, according to other exemplary embodiments. According to another exemplary embodiment, a non-mosaic structure may be formed to fill the opening 65, which defines a partial portion (section 67) of the original copper surface 5 that is converted into the copper telluride surface 25. Therefore, an advantage of the present invention is that a barrier layer (copper telluride 29) can be formed between the copper interconnect lead ι and the upper conductive structure 71 without having to deposit a thin film in the opening, such as having - The high aspect ratio opening 65 makes it difficult to form a continuous barrier layer in the opening π. In other exemplary embodiments, an additional barrier layer can be used with the copper telluride 29. Figure 10 is a perspective cross-sectional view of a steel interconnecting wire 1〇5 formed over the surface 103 of the layer 101. Layer 101 can be a dielectric layer, or other layer formed on a substrate or other semiconductor structure. The copper interconnect wires 1〇5 can be formed using a variety of techniques, such as photolithographic etching and patterning and etching processes being developed in the art. It is anticipated that an improved method of patterning and etching copper in the art will continue to be developed. The patterned copper interconnect wires 105 include a top surface 1〇7 and sidewalls 1〇9, each of which is comprised of copper. As described above, the deuteration/passivation process of the present invention is advantageously used to passivate the exposed surface of the copper interconnect wire 105 (top surface 107 and sidewalls! 〇 9). As a result of the purification process, the sidewalls and top surface of the copper interconnect wires 105 are converted to copper bismuth. The figure shows the converted sidewall 119 and the converted top surface 117, which is now a copper fragmented surface, including the copper fragments shown and discussed in the previous specific examples. Since the surface of the copper telluride Π 9 and 117 inhibits the out-diffusion 84992 -18-1278963 (〇Ut-diffusion), the figure! The resulting hardened structure has the advantage of reducing copper diffusion from the copper interconnect wires. The copper-based surfaces ι 7 and 119 also inhibit the boundary electromigration of copper along the copper interconnect wires 105 and the dielectric material or other material formed thereon. Due to the copper bismuth compound, the adhesion of the subsequently formed material 'especially nitrogen cut and carbon cut to the steel interconnect wire ι 5 is improved. The formation of deposits is also suppressed. Various conductive materials (including optional barrier layers) can be formed to contact the copper sinter regions formed in the surface of the mash and ΐ9. In other embodiments, since the surface of the copper interconnect wire H) 5 acts as a barrier material, no additional barrier layer is used. The foregoing is merely illustrative of the principles of the invention. Therefore, it should be understood that the skilled artisan has been able to devise various embodiments of the present invention in the various embodiments of the present invention, which are not specifically described or illustrated herein, but are included in the present disclosure. Moreover, all of the examples and conditional statements referred to herein are primarily intended to be used for teaching purposes only, and to assist in understanding the concepts of the present invention and the inventors' concepts for advancing the technology, and therefore the present invention should be understood, Limit the specific examples and conditions mentioned. In addition, all of the principles, aspects, and embodiments of the invention are described in the <RTI ID=0.0>>> And the equivalents include not only the current owner but also the equivalent of future developments, regardless of the structure of the device, but any component developed to perform the same function. The present invention is not limited to the specific embodiments described herein and is embodied in the scope of the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood from the following detailed description of the invention. It should be emphasized that, according to the prevailing practice, the various features of the schema are not proportionally transmitted. Panxi, opposite 'For the sake of clarity, the size of the various features ~ magnified or small. In all figures and descriptions, the same numerals indicate the same elements. The drawings include the following figures: Figure 1 is a cross-sectional perspective view of an exemplary inlaid copper interconnect lead; Figure 2 shows the structure of Figure 1 after the exposed copper surface has been converted to copper shreds; Figure 2A Figure 2 is a cross-sectional view of the portion of Figure 2; Figure 3 is a cross-sectional view showing a dielectric material formed on the surface of the purified copper shreds; back and cross-sectional views, which are shown in Figure 3 Figure 5 is a plan view showing an exemplary conductive structure formed on a copper interconnect lead; Figure is a plan view showing a dielectric through a dielectric And forming an opening and exposing the surface of the steel strip; Figure 7 shows the structure shown in Figure 6, which has completed the purification process of the dream exposed copper surface; 0 series plan view, showing the partial break of the copper interconnect wire Figure 9 is a cross-sectional view showing a conductive damascene structure formed in the opening shown in Figure 7; Figure 1 is a cross-sectional perspective view of a copper wire formed on the surface of the tether; and Figure 11 is a view 10 in the structure in which the copper surface has been formed on the exposed steel surface 8499 2 -20- 1278963 Compound. [Description of Symbols] 1 Substrate 3 Bulk copper part 5 Upper copper surface 7 Opening 9 Dielectric material 10 Copper interconnecting lead 11 Top surface 12 Upper surface 13 Barrier layer 15 Barrier layer 17 Edge 19 Bottom layer 21 Contact part 23 Lower layer 25 Copper telluride surface 29 Copper telluride 31 Thickness 35 Upper dielectric layer 35A Layer 35B Layer 37 Top surface 39 Exemplary conductive i 84992 Opening optional barrier layer Selectable barrier layer Block-shaped conductive material Top surface section The upper surface of the opening portion of the second dielectric layer, the conductive structure, the top surface layer of the conductive material, the surface of the top surface of the copper interconnecting wire, and the sidewall of the top surface after conversion.