200408055 玖、發明說明： 【發明所屬之技術領域】 本發明一般係關於半導體積體電路及其形成方法。更特 疋& 本發明係關於在半導體積體電路及類似物中抑 銅擴散。 1 【先前技術】 在半導I:和體電路裝置及相似物中使用銅互連特徵正在 變仔越來越流行。通常使用鑲嵌處理方法形成鋼互連特徵 ，如通道及互連引線（也稱作導線）。使用銅作為一互連材料 能加快裝置速度，且與傳統使用如銘及銘合金等材料相比 ’銅互連特徵含有較少的電線電阻。然而，銅在金屬 電質中具有非常高的擴散速率’即使在低溫下也是如此。 銅擴散能導致戌漏及失去可靠性。防止銅擴散及失去可告 性的-個方法包括在通道、溝渠及其他開口内(傳統上在： 中形成鑲錢互連結物進㈣材料，純μ魅。阻 障材料將銅封裝在開口内。然而，在實施拋光操作以磨平 口亥結構並在介電質内形士、 山 、 y成鑲肷銅互連特徵後，卻曝露了上 方磨光的銅表面。如要咖 不將暴路的銅表面封裝或以其他方 :覆蓋，纟自曝露的鋼表面的銅會擴散進入或通過在銅互 連結構上面形成的導電及/或介電材料。 覆蓋銅表面及防止為彼』 ^ 止鋼摒欢炙—傳統技術係在隨後另一介 电免溥膜沈積在該鋼紝禮二 該鋼表面上面）形成二t ，在整個結構上面（包括 w後必然成為該：二:f化秒層。該氮化樣化 覆私負堆疊之一部分。該多層介 84992 200408055 電質堆疊明顯需要額外處理操作以形成氮化矽或碳化矽層 。此外，銅擴散或電移可能出現在碳化矽/鋼或氮化鋼二 面從而導致裝置可靠性降低。 1 因此，本技術需要一種方法及結構，以防止沿著銅/介電 質介面之銅電移及銅擴散進入並通過上方介電質及導電 料。 、包 【發明内容】 本發明提供一種方法，其藉由將銅互連結構之曝露的鋼 表面轉化成銅矽化物來直接鈍化該表面。在該鋼互連結構 上直接形成的薄銅矽化物層防止銅擴散及電移，並同時在 將該銅互連結構耦合至其他導電特徵而形成的接點内作為 一阻障層。在一項具體實施例中，該銅表面可在一原位順 序處理期間藉由矽烷鈍化，其中在該銅互連結構上面還形 成一上方介電層，如氮化矽或碳化矽。根據該項具體實施 例，可實施鈍化或銅矽化使得銅矽化物形成於該銅互連結 構之整個上表面。 在另一項示範性具體實施例中，本發明提供一上銅表面 、在孩表面上形成一介電層、形成透過該介電層的一開口 從而曝露上銅表面之一部分，隨後藉由將其轉化成銅矽化 物材料而局部鈍化該上銅表面曝露的部分。 在另一項示範性具體實施例中，本發明提供一半導體產 ，其包括在一基板上形成的一銅互連結構及包括一上表 面’其中至少該上表面的一部分係藉由矽與銅互連結構上 的鋼結合而形成的銅矽化物。 84992 200408055 【實施方式】 本發明係提供一種鈍化方法，其藉由在一矽環境（如矽烷） 中’將銅表面的曝露部分轉化成一銅矽化物而將一銅互連 結構曝露的銅（Cu)表面鈍化。該鈍化過程也可稱為一矽化尚 程。隨著矽滲入原先的銅表面並與其中的鋼結合，銅矽化 物得以形成。該銅矽化物用作防止銅從表面擴散進入任何 上方材料中，如上方導電材料及上方介電材料。銅矽化物 在一些區域内也作為金屬與金屬之間的阻障層，在該等區 域内銅互連結構與在銅碎化物區域内另一導電材料相接觸 。由最初曝露的銅表面形成的銅矽化物也防止沿著該銅表 面與上方介電材料’如碳化矽、氮化矽、或各種低k介電材 料之間所形成的介面發生電移。碳化矽或氮化矽材料通常 形成在使用鑲嵌處理技術而形成的鋼互連結構之上。此外 ’卜銅碎化物抑制堆積（hlllQek)形成及改善對所形成薄膜之附 著以接觸銅互連結構之銅碎化物表面。藉由將鋼表面曝露 於含石夕化學品（切垸）中而對銅表面實施的純化，可有益於 在原位與在銅互連結構上面形成氮化矽、碳化矽、或其他 介電質所用之處理操作一起實施。 ^發明也提供銅表面曝露部分的局部純化。根據本項具 月迁實施例’在銅表面上面形成一介電I，及為延伸透過該 介電質及曝露銅表面之一部分而形成一開口。隨後實施使 用a矽化予口口的鈍化過程，將銅表面之曝露部分轉化成銅 秒化物s该開口中可形成另一導電材料，其與作為阻障 層的銅石夕化物區域接觸。此外，可選擇使用獨立形成的阻 84992 200408055 障層作為另-導電材料的—部分。在本項具體實施例中， 該銅秒化物區域作為一金屬與金屬之間擴散的阻障，並也 克服了在具有高縱橫比的開口内形成阻障層的相關問題。 儘管銅互連技術通常使用鑲嵌處理技術形成銅互連结構 ，如通道、互連線及類似物，但目前仍在開發使用與微影 触刻技術相結合的㈣方法’將一表面上形成的銅薄膜圖 案化的技術。目而與在該項技術中使用的其他圖案化互連 材料相似’圖案化的銅包括一曝露的上表面，謂露的側 壁。本發明提供純化該圖案化的銅結構之所有曝露的表面 ’以在包括側壁的所有表面形成銅矽化物，從而鈍化該鋼 互連結構以防止沿著一介電層介面發生銅擴散及銅遷移， 該介電層係隨後形成在該圖案化的銅結構上。如在第一項 非局邵鈍化具體實施例中，原位鈍化/矽化有益於在原位與 隨後的沈積一上方介電薄膜同時實施。 圖1係一使用鑲嵌技術形成的銅互連結構之斷面透視圖 。在圖1所說明的具體實施例中，該範例性銅互連結構係鋼 互連引線10，其在基板丨上縱向延伸並能提供橫向分隔特徵 之間的接觸。銅互連引線10只作為範例，且在其他示範性 具體實施例中，根據本發明將鈍化/碎化的銅結構可能為一 通道，或其他使用鑲歲處理技術形成的導電結構。在另一 項π範性具體實施例中，如在圖丨〇及圖丨丨中所示，可使用微 影蚀刻圖案化及蝕刻的銅引線。 請繼續參照圖1，銅互連引線1 〇形成於基板1上面，更明 確地說，其形成於在介電材料9之内所形成的開口 7中。基 84992 200408055 板1可為由諸如矽、坤化鎵或其他適當材料所形成的半導體 晶圓。如在所述的該項具體實施例中所指定的，基板丨也可 代表在該晶圓上形成的一介電層或其他層。介電材料9可為 一基於矽的介電質，如碳氧化矽（silic〇n 〇xyear>bide ; SiOC-H)，可為一旋轉塗佈芳香族碳（spi卜〇n㈣腦^ carbon)，可為有機矽玻璃（〇rgan〇-siiicate_giass ; 〇SG)，可 為聚亞醯胺或磷矽玻璃（Phosphate Silicate Glass ; PSG)，或 任何與銅互連特徵一同使用的各種其他適當介電質。 在一項較佳具體實施例中，介電材料9為低k介電材料， 即，一介電常數小於4.0的材料。在該項示範性說明的具體 實施例中，開口 7係在介電材料9内形成的一雙鑲嵌開口。 該雙鑲嵌開口可使用傳統技術形成，並僅作為範例。在其 他示範性具體實施例中，可使用一單鑲嵌結構並可包括各 種形狀。儘管圖中所示之介電材料9為一單層，但介電材料 9可由多介電層構成。例如，一獨立介電層可與雙鑲嵌開口 7之母層對應。在另一項具體貫施例中，介電材料9可為 一多層介電質堆疊，其中至少包括一硬光罩層，其可協助 形成该示範性雙鑲嵌（雙層）開口 7。圖中顯示開口 7延伸至介 電材料9的底層19及在基板1上面形成的下臥層23之接觸部 分21。這用於說明該項具體實施例，其中銅互連引線1〇與 一通道相似，與一下臥組件電性接觸。這只作為範例，在 其他不範性具體實施例中，開口 7可具有其他形狀，並可能 不向下延伸到底層19,反而可由介電材料9完全包圍。根據 該項說明性具體實施例，視銅互連引線丨〇的功能及結構情 84992 -10- 200408055 況’下臥層23可為一硬光罩、一阻障層、一導電材料、一 介電材料或任何其他各種材料。根據另一項示範性具體實 施例，下臥層23亦可不存在。 在本說明性具體實施例中，銅互連引線1〇係由塊狀銅部 分3及兩阻障層π及15形成。可使用傳統方法形成該等阻障 層及在其上面形成塊狀鋼材料。該等阻障層從侧面及下面 有效封裝銅互連引線1 〇的塊狀銅部分3。在一項示範性具體 實施例中，下阻障層13可由銓（丁 〇形成，而上阻障層 氮化鈕（ΉΝ)形成。該等薄膜只作為範例，在其他示範性具 體實施中，可使用由鈦、氮化鈦、鎢及鈦鎢形成的其他阻 障層。根據其他示範性具體實施例，可使用各種矽化物作 為一阻障層。在各種示範性具體實施例中，只使用一單層 阻障層。根據另一項範例性具體實施例，可不包括阻障層 。圖1顯示使用拋光或其他合適的鑲嵌技術將該結構實質上 平面化並在開口 7内形成銅互連引線丨〇後的結構。銅互連引 線10包括上表面12，其基本為平面並與介電材料9的頂表面 11共平面。上表面12包括上銅表面5及邊緣I?，其由阻障層 形成。在可選擇阻障層及之後的塊狀銅材料3於開口 7中形 成後，可採用本技術中的各種拖光及其他技術來形成圖i中 所不的結構。 隨後將圖1中所示的結構鈍化以形成圖2中所示的結構。 根據本示範性具體貫施例’上銅表面5的全部都得到曝露， 並使用本發明的鈍化/矽化過程，全部上銅表面5都實質上都 轉化成銅矽化物。該鈍化/矽化過程有利於在3〇〇至4〇(rc 84992 • 11 - 200408055 溫度範圍内使用—矽户 、 ^ ^ 並包括一流動速率（其範圍為300 至M〇0 sccm)、-壓力(其範圍為1至1〇 t㈣、及射頻電聚 功率（其範圍13.56 MHz時為50至讀）。根據一項示範 ^八把實施例，孩矽烷流動速率可大約為300 sccm，且該過 可G括5 ton·的壓力、一 35〇〇c的溫度、至！，_ 的-射頻電漿功率。在其他示範性具體實施例巾，可使用 其他石夕來源的化學氣體。此外，上述數值僅為範例性數值 據/、他示範性具體實施例，可使用不同的程序參數 ' 藉由使兒漿化學品中的矽滲入曝露的銅表面並與其 中的銅反應’將上銅表面5曝露的部分轉化成銅矽化物。可 y成銅夕化物的各種相態。熟知此技術之人士明白，矽化 程度會隨著時間之增加而增加。在-項具fi實施例中，實 施孩過程的時間範圍為5至2G分，但根據需要的碎化程度也 可採用其他的處理時間。 〜2 2顯示圖1的結構在整個曝露的上銅表面5(如圖1所示〕 實貝上已經全邵轉化成銅矽化物表面25後的情形。在其他 具體實施例中，至少上銅表面5之曝露區域的-部分轉化成 為銅矽化物表面25。與原Cu表面5相比，銅矽化物表面25為 —表面知增加的粗糙表面，並且基本不含有不應有的氧化 銅。增加的表面積改善了對在銅矽化物表面25上面形成並 入"接觸之薄膜的黏著。銅矽化物表面2 5也具有抑制在銅 互連引線10中形成堆積之優點。 圖2 A係已轉化成銅矽化物之原銅表面的一展開斷面圖。 圖2A顯示在圖丨中顯示的原上銅表面5轉化成銅矽化物表面 39R 84992 -12- 200408055 25，其包括侵入塊狀銅材料3 J Θ化物29。銅矽化物29代 表銅互連引線10轉化後的一部分，並 ”中碎滲入原上銅表面 並Μ其中的銅結合形成銅梦化物 W化物孩過程參數之選擇要確 保藉由來自珍垸或其㈣氣體化學品的㈣成财化物， 其參入原上鋼表面5,並與Cu結合，進而將該表面之上部分 轉化成銅>5夕化物2 9。銅珍化物7 q i —化 、 /化物29可包括一厚度31，其範圍 為20至200埃，但也可採用並仙戶 /、他与度。熟知本技術之人會明 白、’可改變處理溫度及處理過程持續時間來控制銅碎化物 29之厚度31。厚度31可與需要㈣化程度一同選擇，其要 足夠厚以防止來自銅互連結構的銅擴散，但又不能太厚， 以使互連引線10中銅之薄層電阻的增加幅度最小。在所述 具體實施例中顯示的銅#化物表面25係—㈣及不規則表 面。該粗糙及不規則的表面提供額外表面積，其會改善對 上面形成的薄膜的黏著。 可選擇在350〇C至400〇C的溫度範圍執行一短時間退火過 程，以降低銅互連引線的薄層電阻及降低銅矽化物表面25 與任何為與銅矽化物表面25接觸而形成的其他導電材料之 間的接觸電阻。該可選擇的退火包括秒或分等級的一退火 時間。咸#因為短時間退火改變了最初形成的該銅矽化物 的相態及/或因為矽過量會引起形成额外的銅矽化物，故可 以貫現降低該薄層/接觸電阻。該退火過程可包括氮氣或其 他惰性氣體。根據其他示範性具體實施例，可不採用該退 火過程。 圖2顯示銅矽化物表面25形成後的結構。根據一項示範性 84992 • 13 - 200408055 具體實施例，該結構可以為一中間結構，作為本發明一優 點係本發明的純化/碎化可在原位且與隨後在該結構上面形 成另外一薄膜一同進行。該另一薄膜可為用於形成一上覆 介電堆疊的各種介電薄膜之任一薄膜，根據一項示範性具 體實施例，在該表面直接生成的第一層可為一氮化矽薄膜 ，或使用矽化/鈍化過程在原位形成的一碳化矽薄膜。 圖3係一斷面圖，其顯示在與圖2所示結構大體相同的結 構上形成的上介電層35,其不同點是，為清晰起見，已將 下臥層23、阻障層13及15移除。因此應明白，儘管沒有說 明，但該等特徵可包括在各種具體實施例中，如所述的具 體實施例。上介電層35形成於上表面u及銅矽化物表面25 之上，如上所述，該銅矽化物表面包括銅矽化物29。上介 電層35可以為一單層介電薄膜或其可代表一介電層的堆疊 ，其中一部分或全部皆為使用該矽化/鈍化過程在原位形成 、。可使用低k介電材料及基於以的材料，該等介電材料可以 為=1中介電材料9-道說明的介電材料。在—項示範性 具體實施例中，上介電層35可以為多個單層的複合或堆疊 。上介電層35可藉由虛線分開的35八與训兩層構成。根據 孩項示範性具體實施例，介電層35A可以為氮切或碳切 ’而介電層35B可以為-低時電材料。這僅作為範例，而 在其他π範性具體實施例中，可使用不同數量的各種介電 薄膜形成上介電層35。上介兩 上；丨私層35可包括一層或數層硬光 罩薄膜。本發明的一個方面係改善了碎化_化物表面 5與上介電層35之間的黏著，特別是當與矽化的銅矽化物 84992 -14- 200408055 表面25接觸的介電層為氮化矽或碳化矽時。 圖4顯示圖3中的結構，其中已經形成一示範性導電結構 39 ’以穿過在上介電層35中形成的開口_底部與銅互連 引線丨〇的銅石夕化物表面25相接觸。開口41延伸到上介電層 35的底部，並將銅石夕化物表面^的^㈣曝露。在該項示 範：具體實施例中，開口41係一雙鑲嵌開口，但在其他具 把貫犯例巾I以用其他開口，以提供與銅互連引線1 〇的 銅珍化物表面25的接觸。開口41僅曝露了銅珍化物表面25 的：々分。銅矽化物表面25的其他部分仍藉由上介電層35 覆蓋（其在圖5中顯示得更清楚）。導電結構39包括可選擇的 阻障層43及45與塊狀導電材料47。可選擇的阻障層43及“ 與結合銅互連引線1G—道說明的阻障層似15相似，而塊 狀導迅材料47可以為銅或其他適當的導電材料。根據一項 不範性具體實施例，本發明的-項優點為由於銅矽化物表 為在銅互連引線1 〇及導電結構3 9之間的擴散阻障層 ，需要可選擇的阻障層43及45。根據所說明的示範性 八貫施例，導電結構3 9係一鑲嵌結構，其包括一平面化 ^頂表面49 ’該頂表面49實質上與上介電層35的頂表面37 /、平面在其他不範性具體實施例中，可使用其他各種鑲 後與非镶嵌導電結構接觸銅矽化物表面25。 圖 5 你一.φ ^ t 、十面圖，其顯示在銅互連引線10上面形成並盥直 接觸的上導電結構39,如圖4所示。在該項示範性具體實施 、 私結構3 9係在一開口内部（圖4中所示的開口 41)形 成的通道’其接觸銅互連引線1〇的銅矽化物表面25之區200408055 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates generally to semiconductor integrated circuits and methods of forming the same. More specifically, the present invention relates to suppressing copper diffusion in semiconductor integrated circuits and the like. 1 [Prior art] The use of copper interconnect features in semiconductor I: and body circuit devices and the like is becoming increasingly popular. Damascene processing methods are commonly used to form steel interconnect features such as channels and interconnect leads (also known as wires). The use of copper as an interconnect material can speed up the device, and the copper interconnect feature contains less wire resistance than traditional materials such as Ming and Ming alloys. However, copper has a very high diffusion rate ' in metallic materials, even at low temperatures. Copper diffusion can cause leaks and loss of reliability. One method to prevent copper from diffusing and losing its reportability is to form channels, trenches, and other openings (traditionally in: copper inserts are formed into the material, pure μ charm. Barrier materials encapsulate copper in the openings However, after the polishing operation was performed to smooth the mouth and the structure, and the copper interconnected features were embedded in the dielectric, the copper surface was exposed, and the polished copper surface was exposed. The copper surface is encapsulated or otherwise: covered, the copper from the exposed steel surface will diffuse into or through the conductive and / or dielectric materials formed on the copper interconnect structure. Covering the copper surface and preventing it The steel is overwhelming—the traditional technique is to form a second t after another dielectric free film is deposited on the steel surface of the steel. This will form the second t over the entire structure (including w must be: two: f seconds) Layer. This nitride-like overlay layer is part of the private stack. The multilayer dielectric layer 92492 200408055 obviously requires additional processing operations to form a silicon nitride or silicon carbide layer. In addition, copper diffusion or electromigration may occur in silicon carbide / Steel or nitrided steel As a result, the reliability of the device is reduced. 1 Therefore, the present technology requires a method and structure to prevent copper electromigration and copper diffusion along the copper / dielectric interface from entering and passing through the upper dielectric and conductive material. [Content] The present invention provides a method for directly passivating the exposed steel surface of a copper interconnect structure by converting the surface to a copper silicide. A thin copper silicide layer formed directly on the steel interconnect structure prevents copper diffusion And electromigration, and at the same time as a barrier layer in a contact formed by coupling the copper interconnect structure to other conductive features. In a specific embodiment, the copper surface can be borrowed during an in-situ sequential process. Passivation by silane, wherein an upper dielectric layer, such as silicon nitride or silicon carbide, is also formed on the copper interconnect structure. According to this specific embodiment, passivation or copper silicidation may be performed so that copper silicide is formed on the copper interconnect. The entire upper surface of the structure. In another exemplary embodiment, the present invention provides an upper copper surface, a dielectric layer formed on the surface of the child, and an opening through the dielectric layer is formed from A portion of the upper copper surface is exposed, and then the exposed portion of the upper copper surface is partially passivated by converting it to a copper silicide material. In another exemplary embodiment, the present invention provides a semiconductor product including: A copper interconnect structure formed on a substrate and including an upper surface 'at least a portion of the upper surface is a copper silicide formed by combining silicon with steel on the copper interconnect structure. 84992 200408055 [Embodiment] The present invention provides a passivation method for passivating a copper (Cu) surface exposed by a copper interconnect structure by converting an exposed portion of a copper surface into a copper silicide in a silicon environment (such as silane). The passivation This process can also be referred to as a silicidation process. As silicon infiltrates the original copper surface and combines with the steel in it, a copper silicide is formed. This copper silicide is used to prevent copper from diffusing from the surface into any upper material, such as above Conductive materials and upper dielectric materials. Copper silicide also acts as a metal-to-metal barrier in some areas, where the copper interconnect structure is in contact with another conductive material in the copper debris area. The copper silicide formed from the initially exposed copper surface also prevents electromigration from occurring along the copper surface and the interface formed between the upper dielectric material such as silicon carbide, silicon nitride, or various low-k dielectric materials. Silicon carbide or silicon nitride materials are often formed on steel interconnect structures formed using damascene processing techniques. In addition, copper shatter suppresses the formation of hlllQek and improves the adhesion of the formed film to the surface of the copper shatter of the copper interconnect structure. Purification of the copper surface by exposing the surface of the steel to a slab-containing chemical (cutting tin) can be beneficial for the formation of silicon nitride, silicon carbide, or other dielectrics in situ and on copper interconnect structures The processing operations used by the quality are implemented together. ^ The invention also provides local purification of exposed portions of the copper surface. According to this embodiment, a dielectric I is formed on the copper surface, and an opening is formed to extend through the dielectric and expose a portion of the copper surface. Subsequently, a passivation process using a silicidation to the mouth is performed, and the exposed portion of the copper surface is converted into copper sintered compounds. Another conductive material can be formed in the opening, which is in contact with the chalcedrite region as a barrier layer. In addition, it is optional to use a separately formed barrier layer 84992 200408055 as part of another conductive material. In this specific embodiment, the copper second compound region serves as a barrier to metal-to-metal diffusion, and also overcomes the problems associated with forming a barrier layer in an opening with a high aspect ratio. Although copper interconnect technology typically uses damascene processing techniques to form copper interconnect structures, such as channels, interconnects, and the like, a method of combining the lithography and lithography technique to combine Copper thin film patterning technology. Similar to other patterned interconnect materials used in this technology, the patterned copper includes an exposed upper surface, called exposed sidewalls. The present invention provides purification of all exposed surfaces of the patterned copper structure to form copper silicide on all surfaces including sidewalls, thereby passivating the steel interconnect structure to prevent copper diffusion and copper migration along a dielectric layer interface. The dielectric layer is then formed on the patterned copper structure. As in the first non-local passivation embodiment, in-situ passivation / silicidation is beneficial for simultaneous implementation of in-situ and subsequent deposition of an upper dielectric film. Figure 1 is a cross-sectional perspective view of a copper interconnect structure formed using a damascene technique. In the specific embodiment illustrated in FIG. 1, the exemplary copper interconnect structure is a steel interconnect lead 10 that extends longitudinally on the substrate and can provide contact between laterally spaced features. The copper interconnect lead 10 is used as an example only, and in other exemplary embodiments, the passivated / fragmented copper structure according to the present invention may be a channel, or other conductive structures formed using a damascene process technique. In another embodiment of the π paradigm, as shown in Figs. ○ and 丨, lithographic etching patterned and etched copper leads may be used. Continuing to refer to FIG. 1, a copper interconnection lead 10 is formed on the substrate 1, and more specifically, it is formed in an opening 7 formed in the dielectric material 9. The base 84992 200408055 board 1 may be a semiconductor wafer formed of, for example, silicon, gallium or other suitable materials. As specified in the specific embodiment described, the substrate may also represent a dielectric layer or other layer formed on the wafer. The dielectric material 9 may be a silicon-based dielectric, such as silicon oxycarbide (silicone × bide; SiOC-H), and may be a spin-coated aromatic carbon (spi, carbon, carbon). , Which can be organic silicon glass (〇rgan〇-siiicate_giass; 〇SG), can be polyimide or phosphosilicate glass (Phosphate Silicate Glass; PSG), or any other suitable dielectric used with copper interconnect features quality. In a preferred embodiment, the dielectric material 9 is a low-k dielectric material, that is, a material having a dielectric constant less than 4.0. In the exemplary embodiment of this exemplary description, the opening 7 is a double damascene opening formed in the dielectric material 9. This dual damascene opening can be formed using conventional techniques and is only an example. In other exemplary embodiments, a single damascene structure may be used and may include various shapes. Although the dielectric material 9 shown in the figure is a single layer, the dielectric material 9 may be composed of multiple dielectric layers. For example, an independent dielectric layer may correspond to the mother layer of the dual damascene openings 7. In another specific embodiment, the dielectric material 9 may be a multi-layer dielectric stack including at least a hard mask layer, which may assist in forming the exemplary dual damascene (dual-layer) opening 7. The figure shows that the opening 7 extends to the contact layer 21 of the bottom layer 19 of the dielectric material 9 and the underlying layer 23 formed on the substrate 1. This is used to illustrate this specific embodiment, in which the copper interconnect lead 10 is similar to a channel and is in electrical contact with the lower component. This is only an example. In other non-specific embodiments, the opening 7 may have other shapes, and may not extend down to the bottom layer 19, but may be completely surrounded by the dielectric material 9. According to this illustrative embodiment, the function and structure of the copper interconnect lead 849 are as follows: 84992 -10- 200408055 The lower layer 23 may be a hard mask, a barrier layer, a conductive material, a dielectric Electrical materials or any other various materials. According to another exemplary embodiment, the lower layer 23 may not be present. In this illustrative embodiment, the copper interconnect lead 10 is formed of a bulk copper portion 3 and two barrier layers π and 15. These barrier layers can be formed and formed with a bulk steel material using conventional methods. These barrier layers effectively encapsulate the bulk copper portions 3 of the copper interconnect leads 10 from the sides and below. In an exemplary embodiment, the lower barrier layer 13 may be formed of ytterbium (butadiene), and the upper barrier layer nitride button (ZN). These films are only examples, and in other exemplary implementations, Other barrier layers formed of titanium, titanium nitride, tungsten, and titanium tungsten can be used. According to other exemplary embodiments, various silicides can be used as a barrier layer. In various exemplary embodiments, only the barrier layers are used. A single barrier layer. According to another exemplary embodiment, the barrier layer may not be included. FIG. 1 shows that the structure is substantially planarized using polishing or other suitable damascene techniques and a copper interconnect is formed within the opening 7 The structure behind the lead. The copper interconnect lead 10 includes an upper surface 12 which is substantially planar and coplanar with the top surface 11 of the dielectric material 9. The upper surface 12 includes an upper copper surface 5 and an edge I? Barrier layer formation. After the optional barrier layer and the subsequent bulk copper material 3 are formed in the opening 7, various mopping and other techniques in this technology can be used to form the structure not shown in FIG. I. The structure shown in 1 is passivated to The structure shown in Figure 2. According to this exemplary embodiment, all of the upper copper surface 5 is exposed, and using the passivation / silicidation process of the present invention, all of the upper copper surface 5 is substantially converted into copper. Silicide. This passivation / silicidation process facilitates use in the temperature range of 300 to 40 (rc 84992 • 11-200408055 temperature range—silicon, ^ ^, and includes a flow rate (with a range of 300 to OO sccm) , -Pressure (with a range of 1 to 10 t㈣), and radio frequency power (50 to read at a range of 13.56 MHz). According to a demonstration example, the flow rate of silane can be about 300 sccm, In addition, the pressure may include a pressure of 5 ton ·, a temperature of 3500 ° C, and a power of RF plasma power. In other exemplary embodiments, chemical gases from other Shixi sources may be used. In addition, the above values are only exemplary values and other exemplary embodiments, and different program parameters can be used 'by infiltrating and reacting with silicon in the chemical of silicon in the exposed copper surface' The exposed part of the copper surface 5 is converted into copper silicide It can form various phases of copper compounds. Those who are familiar with this technology understand that the degree of silicification will increase with time. In the fi-fi embodiment, the time range for implementing the child process is 5 to 2G minutes, However, other processing times can also be used according to the degree of fragmentation required. ~ 2 2 shows the structure of Figure 1 on the entire exposed upper copper surface 5 (as shown in Figure 1). The surface has been completely converted into a copper silicide surface. The situation after 25. In other specific embodiments, at least part of the exposed area of the upper copper surface 5 is converted into a copper silicide surface 25. Compared with the original Cu surface 5, the copper silicide surface 25 is- Rough surface and contains essentially no unwanted copper oxide. The increased surface area improves adhesion to the thin film formed on the copper silicide surface 25 to incorporate " contacts. The copper silicide surface 25 also has the advantage of suppressing the formation of deposits in the copper interconnect lead 10. Figure 2 is a developed cross-sectional view of the original copper surface that has been converted into copper silicide. FIG. 2A shows that the original copper surface 5 shown in FIG. 1 is converted into a copper silicide surface 39R 84992 -12- 200408055 25, which includes an intrusive bulk copper material 3 J Θ compound 29. The copper silicide 29 represents a converted part of the copper interconnect lead 10, and the copper infiltrates into the original copper surface and the copper in it forms a copper dream compound. The process parameters are selected to ensure that The gaseous chemical compound of plutonium gas is incorporated into the original steel surface 5 and combined with Cu to further convert the upper part of the surface into copper > 5xixide 2 9. Copper precipitant 7 qi -chemical, / Chemical 29 can include a thickness 31 ranging from 20 to 200 Angstroms, but it can also be used with Sendo / Others. Those skilled in the art will understand that 'the processing temperature and the duration of the process can be changed to control The thickness 31 of the copper shatter compound 29. The thickness 31 can be selected together with the degree of saponification, and it must be thick enough to prevent copper diffusion from the copper interconnect structure, but not too thick to make the copper in the interconnect lead 10 thin The increase in layer resistance is the smallest. The copper compound surface 25 series shown in the specific embodiment-irregular and irregular surfaces. This rough and irregular surface provides additional surface area, which will improve adhesion to the film formed above Optional in 3 Perform a short-time annealing process at a temperature range of 50 ° C to 400 ° C to reduce the sheet resistance of the copper interconnect leads and lower the copper silicide surface 25 and any other conductive materials formed in contact with the copper silicide surface 25 The contact resistance between the two. The optional annealing includes an annealing time of seconds or grades. Because the short time annealing changes the phase state of the copper silicide that is initially formed and / or the excess silicon may cause the formation of additional The copper silicide can consistently reduce the thin layer / contact resistance. The annealing process may include nitrogen or other inert gases. According to other exemplary embodiments, the annealing process may not be used. Figure 2 shows the formation of the copper silicide surface 25 According to an exemplary 84992 • 13-200408055 specific embodiment, the structure may be an intermediate structure. As an advantage of the present invention, the purification / fragmentation of the present invention may be in situ and subsequent to the structure. The formation of another thin film is performed at the same time. The other thin film may be any of various thin films for forming an overlying dielectric stack. In a specific embodiment, the first layer directly formed on the surface may be a silicon nitride film, or a silicon carbide film formed in situ using a silicidation / passivation process. FIG. 3 is a cross-sectional view, which is shown in FIG. The upper dielectric layer 35 formed on the structure shown in FIG. 2 is substantially the same. The difference is that the lower layer 23, the barrier layers 13 and 15 have been removed for clarity. It should be understood, although not described However, these features may be included in various specific embodiments, such as those described. The upper dielectric layer 35 is formed on the upper surface u and the copper silicide surface 25. As described above, the copper silicide surface It includes copper silicide 29. The upper dielectric layer 35 may be a single dielectric film or it may represent a stack of dielectric layers, some or all of which are formed in-situ using the silicidation / passivation process. Low-k dielectric materials and materials based thereon may be used, and these dielectric materials may be the dielectric materials described in the 1-channel dielectric materials. In one exemplary embodiment, the upper dielectric layer 35 may be a composite or a stack of a plurality of single layers. The upper dielectric layer 35 may be composed of two layers separated by a dotted line. According to an exemplary embodiment of the invention, the dielectric layer 35A may be nitrogen-cut or carbon-cut 'and the dielectric layer 35B may be a low-time-current material. This is merely an example, and in other embodiments of the? -Norm, the upper dielectric layer 35 may be formed using a different number of various dielectric films. The upper layer and the upper layer are two layers; the private layer 35 may include one or more layers of hard mask films. One aspect of the present invention is to improve the adhesion between the fragmentation surface 5 and the upper dielectric layer 35, especially when the dielectric layer in contact with the silicided copper silicide 84992 -14- 200408055 surface 25 is silicon nitride. Or silicon carbide. FIG. 4 shows the structure in FIG. 3, in which an exemplary conductive structure 39 'has been formed to pass through the opening formed in the upper dielectric layer 35 to contact the copper oxide surface 25 of the copper interconnect lead. . The opening 41 extends to the bottom of the upper dielectric layer 35, and exposes the surface of the cuprite compound. In this demonstration: in a specific embodiment, the opening 41 is a pair of inlay openings, but other openings are used in other cases to provide contact with the copper surface 25 of the copper interconnect lead 10 . The opening 41 only exposes the surface of the copper precipitating material 25: centipede. The rest of the copper silicide surface 25 is still covered by the upper dielectric layer 35 (which is shown more clearly in FIG. 5). The conductive structure 39 includes optional barrier layers 43 and 45 and a block-shaped conductive material 47. The optional barrier layer 43 and "are similar to the barrier layer described in connection with the copper interconnect lead 1G-15, and the bulk conductive material 47 may be copper or other suitable conductive materials. According to an irregularity In a specific embodiment, one advantage of the present invention is that since the copper silicide is a diffusion barrier layer between the copper interconnect lead 10 and the conductive structure 39, optional barrier layers 43 and 45 are required. The illustrated exemplary eight-through embodiment, the conductive structure 39 is a mosaic structure, which includes a planarized top surface 49. The top surface 49 is substantially the same as the top surface 37 of the upper dielectric layer 35. In the exemplary embodiment, various other inlaid and non-inlaid conductive structures may be used to contact the copper silicide surface 25. Fig. 5a. Φ ^ t, a ten-sided view showing the formation and cleaning of the copper interconnect leads The directly conductive upper conductive structure 39 is shown in Fig. 4. In this exemplary implementation, the private structure 39 is a channel formed inside an opening (opening 41 shown in Fig. 4), which contacts the copper interconnect. Area of copper silicide surface 25 of lead 10
84992 -15 - 200408055 段51。銅矽化物表面25的其他部分藉由上介電層35覆蓋。 圖5中沒有圖示可選擇阻障層43及45。 根據所述示範性具體實施例，銅互連引線1 〇為一互連引 線，其在一橫穿過該裝置延伸的長溝渠内延伸，導電結構 3 9為一通道，但根據其他示範性實施例，也可以使用其他 配置。例如，在一項示範性具體實施例中，該上部鑲欲互 連結構延伸到其從中形成的該介電層的底部，根據該項示 範性具體實施例，可以在以大體垂直關係相互穿越的兩互 連結構之間形成接觸。此外，根據其他示範性具體實施例 ’該上互連結構可為一非鑲嵌結構。 本發明之另一項具體實施例為一曝露的銅表面之局部矽 化。圖6係在介電材料9之内形成的一示範性銅互連引線1〇 的一斷面圖。第二介電層61形成在上銅表面5及介電材料9 的頂表面11之上。如前面所述，第二介電層61可為各種材料 或材料層堆疊的任一層。例如，第二介電層6丨可包括或僅 由基於矽的低k介電層形成且至少包括一硬光罩層。形成開 口 65係為穿過第二介電層61延伸並將上銅表面5之區段67 曝硌出來。儘管所示的示範性開口 6 5係一雙鑲嵌開口，但 在其他不範性具體實施例中，仍可形成各種其他開口。隨 後根據上述鈍化/矽化過程，可將鋼互連引線丨〇的上銅表面5 曝露的區段67鈍化。鈍化/矽化過程係在圖6所示的結構上面 貫施，以形成圖7所示的結構。 圖7顯不局邵鋼矽化物表面25，其形成在銅互連引線1〇之 原銅上表面之曝露的區段67内。上銅表面5之其他未曝露的 84992 -16- 200408055 部分不鈍化。隨著矽滲入原銅上表面並與銅互連引線1〇的 銅結合，形成銅矽化物29並侵蝕Cu互連引線1〇，以將上銅 表面5之曝露的區段67中的銅轉化成鋼矽化物“。在該項具 體實施例中，局部銅矽化物29可作為銅互連引線〗〇及一隨 後形成的與銅互連引線！ 〇接觸的—導電結構之間的阻障層 。這可克服在開口 65内形成—連續阻障層薄膜的缺點以與 銅互連引線1G接觸。根據開口 65具有—高縱横比的示範性 ,體實施例，使用傳統方法形成的阻障層薄膜傾向於不連 續並在開口内產生空洞區域。 圖8係圖7中所示的結構之平面圖。圖8顯示—示範性雙镶 嵌開口 65，其將用於形成在銅互連引線1〇之上對齊的一通 道。局部銅矽化物表面25實質上只形成在區段”内，即轉 化成銅硬化物之銅互連引線1G之原上鋼表面5的曝露部分 。上銅表面5未曝露及局㈣化的其他部分仍保持為未轉化 的銅。隨後，以此方式，圖7斷面圖中所示的第二介電層Ο 覆蓋上銅表面5並包括開π65，透過開口 65，將原上銅表面 5之區段67曝露，此時只有區段67中的原上銅表面5已轉化 成銅碎化物表面2 5。因Α α u此開口65界疋轉化成銅矽化物的該 上銅表面的局部部分。 圖9顯示上導電結構71，其形成於開口 65之内以在區段67 處與局部銅碎化物表面25接觸。上導電結構71包括塊狀導 電材料77並可使用傳統方法形成。塊狀導電材料77可為銅 銘或其他適§導電材料。在說明的具體實施例中，上導 電結構71係-通道’並可使用鑲嵌過程形成，使頂表面Μ -17- 200408055 基本上與第二介電層61之上表 两⑽共千面。根據其他示範 性具體實施例’上導電結構71可為任何其他鑲 一與銅矽化物表面25接觸的互連引線。 ^ Ή求报據另一項示範性 具體實施例，可形成一非鑲嵌結構以填充開口W，該開口 界定轉化成销硬化物表面25之原、上銅表面Μ⑴ 段67)。因此’本發明的—項優點係可在銅互連引線丨〇與上 導電結構7 1之間形成一阻障層（銅碎化物2 9 )，而不必將一薄 膜沈積於一開口中，如且右一古狹拉仏乂《 Τ如/、百n縱杈比的開口 65，因而難 以在該開口中形成—連續阻障層。在其他示範性具體實施 例中，額外的阻障層可與銅矽化物29一同使用。 圖10係在層101之表面103上面形成的銅互連導線1〇5之 透視斷面圖。層1G1可為—介電層，或在—基板上或其他半 導體結構上形成的其他層。銅互連導線1()5可使用各種技術 形成’如微影蝕刻及本技術中正在開發的圖案化與蝕刻程 序:可以預計’將會繼續開發本技術中圖案化及敍刻銅之 改艮方法。圖案化的銅互連導線105包括頂表面107及侧壁 1 0 9 ’其均由銅構成。 、如上所述，本發明之矽化/鈍化過程有利於用於鈍化銅互 連導線1 05之曝露表面（頂表面107及側壁1〇9)。作為鈍化過 程之結果，銅互連導線105的側壁及頂表面轉化成銅矽化 物。 圖11顯示轉化後的側壁119及轉化後的頂表面117，其現已 為銅矽化物表面，包括在先前具體實施例中顯示及論述的 銅碎化物。由於銅矽化物表面丨丨9及u 7抑制外擴散 4(44 84992 -18- 200408055 (out-diffusi〇n)，因此圖 η 由祕 一 [ 、、；U此圖11中所不的矽化後的結構具有減少 來自’同互連導線1 〇 5之銅擴散的展 辦狀的k點。銅矽化物表面1 1 7及 11 9也抑制銅沿著銅互連導岣 ,^ 有別立逑等、.皋1〇5與其上面形成的介電材料 或其他材料之間形成的邊界電遷移。由於㈣化物，隨後 形成的材料’特別是氮切及碳切與銅互連導線Μ的黏 著得到改善。堆積的形成也㈣㈣。可以各材 科（包括可選擇的阻障層），以與於碎化物表面η?及ιΐ9内形 成的㈣化物區域接觸。在其他具體實施例中，由於銅互 連導、泉1 ()5<銅秒化物表面起著阻障材料的作㈤，因此不使 用额外的阻障層。 、上所逑僅說明本發明〈原理。因此應明瞭，熟悉技術 人士 :設計出各種各樣的配置以具體化本發明之原理，雖 然該等配置並未在本文中明確說明或顯示，但係包含在本 發明之範4和精神中。而jl，此中提及的所有範例和條件 語句主要係旨在僅用於教導目的，並幫助理解本發明之原 理及U者為推進技術所提出的概念，因此應理解本發明 並不侷限於所提及的具體範例和條件。此外，此中所有提 及本發明之原5里、觀點及具體實施例的敘述，及其中的具 體範例1旨在涵蓋所有其結構和功能等效者。並且該等 等放者不僅包含目前既有者，亦包含未來開發之等效者， 即不响其結冑，但執行相同功能的所開發之任何元件。因 此本發明惑範疇不限於本文所示及所述的示範性具體實 施例。而是具體化在隨附的申請專利範圍中。 【圖式簡單說明】 405 84992 -19- 200408055 從以上結合隨附圖式閱讀本發明之詳細說明即 解本發明。需強調指出，根據通行的做法，圖式的各特 徵並非按比例緣製。與之相反，為清楚起見，各種特徵的 尺寸故意放大或縮小。纟所有圖式及說明書中，相同的數 字表示相同的元件。圖式中包含如下圖式： 圖1係一項示範性鑲嵌鋼互連引線之斷面透视圖丨 圖2顯π圖！的結構在曝露的銅表面已經轉化成 後的情形； 物 圖2A係圖2中一部分的展開斷面圖； 圖3係一斷面圖，其顯示在鈍化後的銅矽化物表面上形 的一介電材料； 7 圖4係一斷面圖，其顯示在圖3所示的鈍化後的矽化銅表 面上形成的導電結構； 圖5係一平面圖，其顯示在銅互連引線上形成的-示範性 導電結構； 圖6係一斷面圖，其顯示透過一介電質而形成的一開口且 曝露出部分銅表面； 圖7顯TF圖6所顯示的結構，其已完成了矽化曝露的鋼表 面的鈍化過程； 圖8係一平面圖，其顯示銅互連導線之局部矽化區域； 圖係斷面圖’其顯示在圖7所示的開口中形成的導電 鑲嵌結構； 圖10係在一表面之上形成的銅導線之斷面透視圖；及 圖11顯不圖1 〇中的結構，其中曝露的銅表面上已形成鋼矽 406 84992 -20- 200408055 化物。 【圖式代表符號說明】 1 基板 3 塊狀銅部分 5 上銅表面 7 開口 9 介電材料 10 銅互連引線 11 頂表面 12 上表面 13 阻障層 15 阻障層 17 邊緣 19 底層 21 接觸部分 23 下臥層 25 碎化銅表面 29 矽化銅 31 厚度 35 上介電層 35A 層 35B 層 37 頂表面 39 示範性導電結構 -21 84992 開口 可選擇阻障層 可選擇阻障層 塊狀導電材料 頂表面 區段 第二介電層 開口 區段 上表面 上導電結構 導電材料 頂表面 層 表面 銅亙連導線 頂表面 侧壁 轉化後的頂表面 轉化後的侧壁 -22-84992 -15-200408055 paragraph 51. The other parts of the copper silicide surface 25 are covered by the upper dielectric layer 35. The optional barrier layers 43 and 45 are not shown in FIG. 5. According to the exemplary embodiment, the copper interconnect lead 10 is an interconnect lead that extends in a long trench extending across the device, and the conductive structure 39 is a channel, but according to other exemplary implementations For example, other configurations can also be used. For example, in an exemplary embodiment, the upper embedded interconnect structure extends to the bottom of the dielectric layer from which it is formed. According to the exemplary embodiment, it can pass through each other in a substantially vertical relationship. Contacts are formed between the two interconnected structures. In addition, according to other exemplary embodiments, the upper interconnection structure may be a non-mosaic structure. Another embodiment of the invention is the local silicidation of an exposed copper surface. FIG. 6 is a cross-sectional view of an exemplary copper interconnect lead 10 formed within a dielectric material 9. A second dielectric layer 61 is formed over the upper copper surface 5 and the top surface 11 of the dielectric material 9. As mentioned earlier, the second dielectric layer 61 may be any of a variety of materials or a stack of material layers. For example, the second dielectric layer 6 may include or be formed only of a silicon-based low-k dielectric layer and at least include a hard mask layer. The opening 65 is formed to extend through the second dielectric layer 61 and expose a section 67 of the upper copper surface 5. Although the exemplary opening 65 shown is a double inlay opening, various other openings may be formed in other non-limiting embodiments. The exposed section 67 of the upper copper surface 5 of the steel interconnect lead can then be passivated according to the passivation / silicidation process described above. The passivation / silicidation process is performed on the structure shown in FIG. 6 to form the structure shown in FIG. Fig. 7 shows an unfavorable surface of silicide steel 25 formed in the exposed section 67 of the upper surface of the original copper of the copper interconnect lead 10. The other unexposed 84992 -16- 200408055 parts of the upper copper surface 5 are not passivated. As the silicon penetrates the upper surface of the original copper and combines with the copper of the copper interconnect lead 10, a copper silicide 29 is formed and the Cu interconnect lead 10 is eroded to convert the copper in the exposed section 67 of the upper copper surface 5 Steel-forming silicide ". In this specific embodiment, the local copper silicide 29 can be used as a copper interconnect lead. 0 and a subsequently formed copper interconnect lead! Contact-a barrier layer between conductive structures. This can overcome the shortcomings of forming a continuous barrier film in the opening 65 to contact the copper interconnect lead 1G. According to an exemplary embodiment of the opening 65 having a high aspect ratio, a barrier layer formed using a conventional method The film tends to be discontinuous and creates void areas within the openings. Figure 8 is a plan view of the structure shown in Figure 7. Figure 8 shows-an exemplary dual damascene opening 65 that will be used to form copper interconnect leads 10 A channel aligned on the top. The local copper silicide surface 25 is formed substantially only in the section ", that is, the exposed portion of the original upper steel surface 5 of the copper interconnect lead 1G converted to a copper hardened object. Other portions of the upper copper surface 5 that are not exposed and localized remain unconverted copper. Then, in this way, the second dielectric layer 0 shown in the cross-sectional view of FIG. 7 covers the upper copper surface 5 and includes an opening π 65. Through the opening 65, the section 67 of the original upper copper surface 5 is exposed. The original upper copper surface 5 in section 67 has been transformed into a copper shredded surface 25. Due to A α u, the opening 65 is converted into a local part of the upper copper surface of copper silicide. FIG. 9 shows an upper conductive structure 71 that is formed within the opening 65 to contact the local copper flake surface 25 at the section 67. The upper conductive structure 71 includes a bulk conductive material 77 and can be formed using a conventional method. The bulk conductive material 77 may be copper or other suitable conductive materials. In the illustrated embodiment, the upper conductive structure 71 is a channel and can be formed using a damascene process so that the top surface M -17-200408055 is substantially on the same surface as the upper surface of the second dielectric layer 61. According to other exemplary embodiments, the upper conductive structure 71 may be any other interconnection lead inlaid with the copper silicide surface 25. ^ According to another exemplary embodiment, a non-mosaic structure can be formed to fill the opening W, which defines the original, upper copper surface M⑴ section 67 converted into the pin hardened surface 25). Therefore, an advantage of the present invention is that a barrier layer (copper fragment 29) can be formed between the copper interconnect lead and the upper conductive structure 71, without having to deposit a thin film in an opening, such as Furthermore, the ancient opening of the right narrow opening "Tru /, hundred n vertical ratio ratio 65, so it is difficult to form a continuous barrier layer in the opening. In other exemplary embodiments, an additional barrier layer may be used with the copper silicide 29. Fig. 10 is a perspective sectional view of a copper interconnecting wire 105 formed on the surface 103 of the layer 101. Layer 1G1 may be a dielectric layer, or other layers formed on a substrate or other semiconductor structure. The copper interconnect wires 1 () 5 can be formed using various techniques such as lithographic etching and the patterning and etching processes being developed in this technology: it is expected that the patterning and engraving of copper in this technology will continue to be developed method. The patterned copper interconnect wire 105 includes a top surface 107 and side walls 10 9 ', each of which is composed of copper. As described above, the silicidation / passivation process of the present invention is advantageous for passivating the exposed surface (top surface 107 and side wall 109) of the copper interconnecting wire 105. As a result of the passivation process, the sidewalls and top surfaces of the copper interconnect wires 105 are converted into copper silicide. Figure 11 shows the converted side wall 119 and the converted top surface 117, which are now copper silicide surfaces, including the copper shreds shown and discussed in previous embodiments. Because the surface of copper silicide 丨 9 and u 7 inhibit external diffusion 4 (44 84992 -18- 200408055 (out-diffusion), the figure η is shown by the secret one [,,; U after the silicidation not shown in Figure 11 The structure has exhibited k-points that reduce the diffusion of copper from the same interconnect wire 105. The copper silicide surface 1 1 7 and 11 9 also suppress copper conduction along the copper interconnect, ^ 有 立 立 逑Etc. The boundary electromigration formed between. 皋 105 and the dielectric material or other materials formed thereon. Due to the hafnium compound, the subsequent formation of the material 'especially the nitrogen cut and carbon cut and the adhesion of the copper interconnect wire M was obtained Improvement. The formation of stacks is also difficult. Various materials (including optional barrier layers) can be used to contact the hafnium compound areas formed on the surface of the broken material η? And ιΐ9. In other specific embodiments, due to copper mutual Liandao, Quan 1 () 5 < The surface of the copper second compound acts as a barrier material, so no additional barrier layer is used. The above description only explains the principle of the present invention. Therefore, it should be clear to those skilled in the art: Various configurations have been devised to embody the principles of the invention, although such The device is not explicitly illustrated or shown in this document, but is included in the spirit and spirit of the present invention. And jl, all examples and conditional statements mentioned here are mainly for teaching purposes only and to help understand The principles of the present invention and the concepts put forward by the propulsion technology should be understood that the present invention is not limited to the specific examples and conditions mentioned. In addition, all of the original references, viewpoints, and specifics of the present invention are mentioned here. The description of the embodiment, and the specific example 1 in it, are intended to cover all its structural and functional equivalents. And this waiter includes not only the existing ones, but also the equivalents of future development, that is, it does not ring the knot胄, but any element developed to perform the same function. Therefore, the scope of the present invention is not limited to the exemplary embodiments shown and described herein. Instead, it is embodied in the scope of the accompanying patent application. [Schematic simple Explanation] 405 84992 -19- 200408055 From the above, the detailed description of the present invention will be explained in conjunction with the accompanying drawings. It should be emphasized that according to common practice, the features of the drawings are not to scale. In contrast, for the sake of clarity, the dimensions of various features are intentionally enlarged or reduced. 纟 In all drawings and descriptions, the same numbers represent the same elements. The drawings include the following drawings: Figure 1 is an example Cross-sectional perspective view of the inlaid steel inlaid steel lead 丨 Figure 2 shows the π diagram! The structure of the exposed copper surface has been transformed into the situation; Figure 2A is a partial sectional view of Figure 2; Figure 3 is a broken A plan view showing a dielectric material shaped on the surface of the copper silicide after passivation; FIG. 4 is a sectional view showing a conductive structure formed on the surface of the copper silicide after passivation shown in FIG. 3; 5 is a plan view showing an exemplary conductive structure formed on a copper interconnect lead; FIG. 6 is a cross-sectional view showing an opening formed through a dielectric and exposing a portion of the copper surface; 7 shows the structure shown in Figure 6 of the TF, which has completed the passivation process of the siliconized exposed steel surface; Figure 8 is a plan view showing the localized siliconized area of the copper interconnecting wire; Figure is a sectional view 'It is shown in the figure The guide formed in the opening shown in 7 Mosaic structure; Figure 10 is a cross-sectional perspective view of a copper wire formed on a surface; and Figure 11 shows the structure in Figure 10, in which steel silicon has been formed on the exposed copper surface 406 84992 -20- 200408055 compound . [Illustration of representative symbols of the figure] 1 Substrate 3 Bulk copper part 5 Upper copper surface 7 Opening 9 Dielectric material 10 Copper interconnect lead 11 Top surface 12 Top surface 13 Barrier layer 15 Barrier layer 17 Edge 19 Bottom layer 21 Contact portion 23 Underlying layer 25 Broken copper surface 29 Copper silicide 31 Thickness 35 Upper dielectric layer 35A layer 35B layer 37 Top surface 39 Exemplary conductive structure-21 84992 Opening optional barrier layer optional barrier layer bulk conductive material top Surface section The upper surface of the second dielectric layer opening section is a conductive structure on the top surface of the conductive material. The surface of the top surface layer is copper-coupling conductors.