JPH10209272A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of restricting a shape degradation of a conductive wiring sidewall part in a multi-wiring which is a structure that a room for a misalignment between a lower conductive wiring and a connection hole is provided; and its manufacturing method. SOLUTION: First, a lower conductive wire 2 in which a room for a misalignment for a connection hole is not provided is formed on an underlayer insulation film 1. Next, an interlayer flattening insulation film is deposited on the underlayer insulation film 1 and the lower conductive wire 2. Next, photoresist patternings for processing the connection hole are formed. Next, the connection hole with the lower conductive wire 2 is processed by anisotropic dry-etching. Next, a resist hardening layer is removed by an ashing process. Next, a modified layer 11 is formed in a sidewall part of the lower conductive wire 2 exposed via the connection hole by a plasma process 10. Next, resist is removed by a chemical liquid cleaning process. Next, after the modified layer 11 is removed by reverse sputter cleaning, a closely adhered layer metal 7 is formed as a film on the entire surface. Next, a buried metal 8 is formed as a film on the entire surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for use in, for example, an VLSI and a method of manufacturing the same, and more particularly to a multilayer device having a structure in which a lower conductor wiring and a connection hole have no margin for misalignment. The present invention relates to a semiconductor device suitable for application to a super LSI having wiring and the like and a method for manufacturing the same.

[0002]

2. Description of the Related Art
The concept of design rules has been used to minimize the probability that the functionality of a fabricated IC will be impaired by random geometric deformation of the IC elements.

In recent years, as semiconductor devices have become more highly integrated and miniaturized, attention has been paid to a structure that does not provide a margin for misalignment between a substrate and a conductor wiring or a connection hole between conductor wirings and a conductor wiring. Normal conductor wiring is not formed with the minimum design rule above the connection hole, but is formed with a loose design rule that takes into account the margin for covering the connection hole and misalignment of the conductor wiring to the connection hole. . Therefore, as the miniaturization progresses, the degree of integration is governed by the overlapped portion. Therefore, realizing connection holes and conductor wiring having a structure that does not provide a margin for misalignment is one of the technical aspects for high integration. It becomes a breakthrough.

[0004] The problems of the present technology are described as prior art in FIGS.
0 will be described. A lower conductor wiring 2 is formed on a base insulating film 1, and an interlayer planarizing insulating film 3 is deposited (FIG. 9).
A). Thereafter, a photoresist pattern 4 for forming a connection hole is formed (FIG. 9B), and the connection hole 5 with the lower conductor wiring is processed by anisotropic dry etching (FIG. 9C). Examples of the forming conditions of the lower conductor wiring and the processing conditions of the connection hole are shown below.

Lower conductor wiring: formed by magnetron sputtering method Ti20 nm (0.52 Pa, 2 kW, Ar35 sccm, 300 ° C.) TiN 20 nm (0.78 Pa, 6 kW, N2 42 sccm, Ar21 sccm, 300 ° C.) Al-0.5% Cu 500 nm (0.52 Pa, 15 kW) , Ar65sccm, 300 ℃) Ti10nm (0.52Pa, 2kW, Ar35sccm, 300 ℃) TiN100nm (0.78Pa, 6kW, N2 42sccm, Ar21sccm, 300 ℃) Lower conductor wiring processing: Anisotropic dry etching BCl3 / Cl2 = 100 / 150sccm , 1Pa, Microwave 400mA, RF 110W Just + 40% over etching Connection hole processing: Anisotropic dry etching CO / C4F8 / Ar = 100/7 / 200sccm, 2Pa, RF 1450W Just + 30% over etching

Thereafter, the resist hardened layer by etching is removed by O ₂ ashing (FIG. 10A), and the resist is removed by chemical cleaning (FIG. 10B). The resist removal conditions are shown below. Resist removal: Amine organic solvent 15 minutes + running water treatment 1
0 minutes

In the case where the connection hole formed through this process does not have a margin for misalignment with the lower conductor wiring, the connection hole is dug 6 in the Al alloy portion where the side wall of the conductor wiring is exposed. Thereafter, reverse sputtering cleaning is performed by a magnetron sputtering apparatus to form an adhesion layer metal 7 on the entire surface.
A tungsten film 8 is entirely formed as a buried metal by a thermal CVD method (FIG. 10C). Examples of the respective film forming conditions are shown below.

Adhesion layer metal formation: film formation by magnetron sputtering method RF Etch 20 nm (0.52 Pa, 500 W, Ar5 sccm, no heating) TiN 30 nm (0.78 Pa, 6.5 kW, N2 135 sccm, Ar15 sccm, 150 ° C.) Blanket W film CVD: 600nm (10.7kPa, WF6: H2: Ar = 40: 400: 2250sccm, 450 ℃)

In the thus formed buried metal connection hole, the above-described digging of the Al alloy portion occurs, which causes insufficient adhesion due to deterioration of the adhesion layer coverage and induces void formation in the tungsten film. For this reason, there is a concern that contact resistance may be increased or yield may be reduced due to poor contact between the lower conductor wiring and the embedded metal, and furthermore, wiring reliability may be degraded. The digging of the Al alloy part is due to the fact that fluorine adhering at the time of forming the connection hole forms a fluoride with Al and cannot be completely removed by the ashing treatment on the Al alloy side wall part, so that it elutes during the organic cleaning at the time of removing the resist. Conceivable.

The present invention has been made in view of such a problem, and suppresses deterioration of the shape of a side wall portion of a conductor wiring in a multilayer wiring having a structure in which a lower conductor wiring and a connection hole have no allowance for misalignment. It is an object of the present invention to provide a semiconductor device capable of forming a contact hole of a highly integrated and fine semiconductor device without impairing contact characteristics and wiring reliability, and a method for manufacturing the same.

[0011]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a lower conductor wiring having no margin for misalignment with a connection hole on a base insulating film is provided. A step of depositing an interlayer planarization insulating film on the conductor wiring, a step of forming a photoresist pattern for processing a connection hole, and a step of processing a connection hole with the lower conductor wiring by anisotropic dry etching Removing the hardened resist layer by ashing, forming a modified layer on the side wall of the lower conductor wiring exposed through the connection hole, removing the resist by a chemical cleaning process, Is removed by reverse sputter cleaning, and then a step of forming a metal film on the entire surface of the adhesion layer and a step of forming a metal film on the entire surface of the buried metal.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a lower conductor wiring having no margin for misalignment with respect to the connection hole on the base insulating film, depositing an interlayer planarization insulating film on the base insulation film and the lower conductor wiring, Forming a photoresist pattern for processing, forming a connection hole with the lower conductor wiring by anisotropic dry etching, etching the lower conductor wiring at the bottom of the connection hole, The method includes a step of removing by an ashing process, a step of removing a resist by a chemical solution cleaning process, and a step of forming a burying metal on the entire surface after forming an adhesive layer metal on the entire surface.

Further, in the semiconductor device of the present invention, a lower conductor wiring which does not provide a margin for misalignment with respect to a connection hole is formed on a base insulating film, and an interlayer planarization insulating film is formed on the base insulating film and the lower conductor wiring. A film is formed and an interlayer planarization insulating film is formed.
A connection hole for removing a part of the lower conductor wiring is formed, and a buried metal is formed on the connection hole and the interlayer flattening insulating film.

According to the semiconductor device and the method of manufacturing the same of the present invention, the modified layer is formed on the side wall of the lower conductor exposed through the connection hole, or the lower conductor at the bottom of the connection hole is etched. Thereby, in a multilayer wiring having a structure in which the lower conductor wiring and the connection hole do not have a margin for misalignment, it is possible to suppress the deterioration of the shape of the side wall of the conductor wiring.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor device and the method of manufacturing the same according to the present invention will be described below with reference to FIGS.

Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. A lower conductor wiring 2 is formed on a base insulating film 1, and an interlayer planarizing insulating film 3 is deposited (FIG. 1A). Thereafter, a photoresist patterning 4 for forming a connection hole is formed (FIG. 1B).
The connection hole 5 with the lower conductor wiring is processed by anisotropic dry etching (FIG. 1C). Examples of the forming conditions of the lower conductor wiring and the processing conditions of the connection hole are shown below. Lower conductor wiring: formed by magnetron sputtering method Ti20nm (0.52Pa, 2kW, Ar35sccm, 300 ° C) TiN20nm (0.78Pa, 6kW, N2 42sccm, Ar21sccm, 300 ° C) Al-0.5% Cu500nm (0.52Pa, 15kW, Ar65sccm, 300 ℃) Ti10nm (0.52Pa, 2kW, Ar35sccm, 300 ℃) TiN100nm (0.78Pa, 6kW, N2 42sccm, Ar21sccm, 300 ℃) Lower conductor wiring processing: Anisotropic dry etching BCl3 / Cl2 = 100 / 150sccm, 1Pa, Microwave 400mA, RF 110W Just + 40% over etching Connection hole processing: Anisotropic dry etching CO / C4F8 / Ar = 100/7 / 200sccm, 2Pa, RF 1450W Just + 30% over etching

Next, the resist cured layer formed by etching is
₂ After removal by ashing (FIG. 1D), nitrogen plasma treatment 10 is performed to form an Al nitride layer 11 on the side wall of the conductor wiring (FIG. 2A). The thickness of the nitride layer is preferably 5 nm or more and 20 nm or less.

If the thickness of the nitride layer is less than 5 nm, it is not possible to prevent digging in the Al alloy portion in the region where the side wall of the conductor wiring is exposed, and the thickness of the nitride layer is 20 nm. If the thickness is larger, the nitride layer cannot be removed by reverse sputter cleaning in the step of forming the adhesion layer metal described later. Thereafter, the resist is removed by a chemical cleaning process (FIG. 2B). The conditions for nitrogen plasma treatment and resist removal are as follows.

Nitrogen plasma treatment: Parallel plate type RIE system, N2 150 sccm, 200 W, 0.1 Torr, 20 sec, room temperature Resist removal: Amine organic solvent 15 minutes + running water treatment 1
0 minutes

Even if the connection hole formed through this process has a structure in which there is no allowance for misalignment with the lower conductor wiring, the shape of the connection hole does not deteriorate because the side wall of the conductor wiring is protected by the nitride layer. Thereafter, an adhesion layer metal 7 is formed on the entire surface by, for example, a magnetron sputtering method. The nitride layer can be removed by reverse sputter cleaning in the step of forming the adhesion layer metal. Next, a tungsten film 8 is entirely formed as a buried metal by a thermal CVD method (FIG. 2C). Examples of the respective film forming conditions are shown below.

Adhesion layer metal formation: Film formation by magnetron sputtering method RF Etch 20 nm (0.52 Pa, 500 W, Ar5 sccm, no heating) TiN 30 nm (0.78 Pa, 6.5 kW, N2 135 sccm, Ar15 sccm, 150 ° C.) Blanket W film CVD: 600nm (10.7kPa, WF6: H2: Ar = 40: 400: 2250sccm, 450 ° C)

The contact hole of the buried metal formed in this way has a good contact state with the side wall of the lower conductor wiring, so that the contact layer metal and the tungsten film have good adhesion and the buried state of the tungsten film is also good. Met. For this reason, the contact resistance and the yield were almost the same as those of a normal connection hole having no structure having a margin for misalignment, and there was no significant difference in the electromigration life. The gas for plasma processing is not limited to nitrogen, but oxygen, hydrogen,
These mixed gases may be used.

Embodiment 2 Embodiment 2 of the present invention will be described with reference to FIGS. An upper conductor wiring 2 is formed on a base insulating film 1, and an interlayer planarizing insulating film 3 is deposited (FIG. 3A). Thereafter, a photoresist pattern 4 for forming a connection hole is formed (FIG. 3B).
The joint hole 5 with the lower conductor wiring is processed by anisotropic dry etching (FIG. 3C). Examples of the forming conditions of the lower conductor wiring and the processing conditions of the connection hole are shown below. Lower conductor wiring: formed by magnetron sputtering method Ti20nm (0.52Pa, 2kW, Ar35sccm, 300 ° C) TiN20nm (0.78Pa, 6kW, N2 42sccm, Ar21sccm, 300 ° C) Al-0.5% Cu500nm (0.52Pa, 15kW, Ar65sccm, 300 ℃) Ti10nm (0.52Pa, 2kW, Ar35sccm, 300 ℃) TiN100nm (0.78Pa, 6kW, N2 42sccm, Ar21sccm, 300 ℃) Lower conductor wiring processing: Anisotropic dry etching BCl3 / Cl2 = 100 / 150sccm, 1Pa, Microwave 400mA, RF 110W Just + 40% over etching Connection hole processing: Anisotropic dry etching CO / C4F8 / Ar = 100/7 / 200sccm, 2Pa, RF 1450W Just + 30% over etching

Next, the resist cured layer formed by etching is
₍₂ ) After removal by ashing (FIG. 3D), a hot hydroxylation treatment 12 is performed, and an Al oxide layer 1
3 (FIG. 4A). Thereafter, the resist is removed by a chemical cleaning process (FIG. 4B). The conditions for warm water oxidation and resist removal are as follows. The thickness of the oxide layer is 5 nm or more and 20 n
m or less.

If the thickness of the oxide layer is less than 5 nm, it is not possible to prevent digging in the Al alloy portion in the region where the side wall of the conductor wiring is exposed, and the thickness of the oxide layer is 20 nm. If the thickness is larger, the oxide layer cannot be removed by reverse sputter cleaning in the step of forming the adhesion layer metal described later.

Hot water oxidation: pure water, 100 ° C., 15 minutes Resist removal: amine organic solvent for 15 minutes + running water treatment 1
0 minutes

Even if the connection hole formed through this process has a structure in which there is no allowance for misalignment with the lower conductor wiring, the shape of the connection hole does not deteriorate because the side wall of the conductor wiring is protected by the oxide layer. Thereafter, an adhesion layer metal 7 is formed on the entire surface by, for example, a magnetron sputtering method. The oxide layer can be removed by reverse sputter cleaning in the step of forming the adhesion layer metal. Next, a tungsten film 8 is entirely formed as a buried metal by a thermal CVD method (FIG. 4C). Examples of the respective film forming conditions are shown below.

Adhesion layer metal formation: Film formation by magnetron sputtering method RF Etch 20 nm (0.52 Pa, 500 W, Ar5 sccm, no heating) TiN 30 nm (0.78 Pa, 6.5 kW, N2 135 sccm, Ar15 sccm, 150 ° C.) Blanket W film CVD: 600 nm (10.7 kPa, WF6: H2: Ar = 40: 400: 2250sccm, 450 ° C)

The contact hole of the buried metal formed in this manner has a good contact state with the side wall of the lower conductor wiring, so that the adhesion layer metal and the tungsten film have good adhesion and the buried state of the tungsten film is good. Met. For this reason, the contact resistance and the yield were almost the same as those of a normal connection hole having no structure having a margin for misalignment, and there was no significant difference in the electromigration life. The hot water treatment temperature may be 100 ° C. or lower as long as it can suppress Al digging.

Third Embodiment A third embodiment of the present invention will be described with reference to FIGS. A lower conductor wiring 2 is formed on a base insulating film 1, and an interlayer planarizing insulating film 3 is deposited (FIG. 5A). Thereafter, a photoresist pattern 4 for forming a connection hole is formed (FIG. 5B).
The connection hole 5 with the lower conductor wiring is processed by anisotropic dry etching (FIG. 5C). Examples of the forming conditions of the lower conductor wiring and the processing conditions of the connection hole are shown below.

Lower conductor wiring: formed by magnetron sputtering Ti20 nm (0.52 Pa, 2 kW, Ar35 sccm, 300 ° C.) TiN 20 nm (0.78 Pa, 6 kW, N2 42 sccm, Ar21 sccm, 300 ° C.) Al-0.5% Cu 500 nm (0.52 Pa, 15 kW) , Ar65sccm, 300 ℃) Ti10nm (0.52Pa, 2kW, Ar35sccm, 300 ℃) TiN100nm (0.78Pa, 6kW, N2 42sccm, Ar21sccm, 300 ℃) Lower conductor wiring processing: Anisotropic dry etching BCl3 / Cl2 = 100 / 150sccm , 1Pa, Microwave 400mA, RF 110W Just + 40% over etching Connection hole processing: Anisotropic dry etching CO / C4F8 / Ar = 100/7 / 200sccm, 2Pa, RF 1450W Just + 30% over etching

Next, the hardened resist layer by etching is
₂ After removal by ashing (FIG. 5D), oxygen ion irradiation 14 is performed to form an Al oxide layer 15 on the side wall of the conductor wiring (FIG. 6A). Thereafter, the resist is removed by a chemical cleaning process (FIG. 6B). Ion irradiation,
The resist removal conditions are shown below. The thickness of the oxide layer is preferably 5 nm or more and 20 nm or less.

If the thickness of the oxide layer is less than 5 nm, it is not possible to prevent digging in the Al alloy portion in the region where the side wall of the conductor wiring is exposed, and the thickness of the oxide layer is 20 nm. If the thickness is larger, the oxide layer cannot be removed by reverse sputter cleaning in the step of forming the adhesion layer metal described later.

Ion irradiation: low current ion irradiator, O
₂ +, 150keV, 1E18ions / cm ² , no heating, 7 ° tilt Resist removal: amine organic solvent 15 minutes + running water treatment 1
0 minutes

Even if the connection hole formed through this step has a structure in which there is no allowance for misalignment with the lower conductor wiring, the shape of the connection hole does not deteriorate because the side wall of the conductor wiring is protected by the oxide layer. Thereafter, an adhesion layer metal 7 is formed on the entire surface by, for example, a magnetron sputtering method. The oxide layer can be removed by reverse sputter cleaning in the step of forming the adhesion layer metal. Next, a tungsten film 8 is entirely formed as a buried metal by a thermal CVD method (FIG. 6C). Examples of the respective film forming conditions are shown below.

Adhesion layer metal formation: Film formation by magnetron sputtering method RF Etch 20 nm (0.52 Pa, 500 W, Ar5 sccm, no heating) TiN 30 nm (0.78 Pa, 6.5 kW, N2 135 sccm, Ar15 sccm, 150 ° C.) Blanket W film CVD: 600 nm (10.7 kPa, WF6: H2: Ar = 40: 400: 2250sccm, 450 ° C)

The contact hole of the buried metal formed in this way has a good contact state with the lower conductor wiring side wall, so that the adhesion layer metal and the tungsten film have good adhesion, and the buried state of the tungsten film is also good. Met. For this reason, the contact resistance and the yield were almost the same as those of a normal connection hole having no structure having a margin for misalignment, and there was no significant difference in the electromigration life. The ion irradiation dose may be other than 1E18 ions / cm ^{2 as} long as it can suppress the excavation of Al. The ion species is not limited to oxygen ions, and hydrogen ions, nitrogen ions, and the like can be used. Further, the irradiation angle is preferably 7 ° or more and 45 ° or less from the efficiency of reforming the side wall.

Fourth Embodiment A fourth embodiment of the present invention will be described with reference to FIGS. A lower conductor wiring 2 is formed on a base insulating film 1, and an interlayer planarizing insulating film 3 is deposited (FIG. 7A). Thereafter, a photoresist patterning 4 for forming a connection hole is formed (FIG. 7B).
The connection hole 5 with the lower conductor wiring is processed by anisotropic dry etching (FIG. 7C). Examples of the forming conditions of the lower conductor wiring and the processing conditions of the connection hole are shown below.

Lower conductor wiring: formed by magnetron sputtering Ti20 nm (0.52 Pa, 2 kW, Ar35 sccm, 300 ° C.) TiN 20 nm (0.78 Pa, 6 kW, N2 42 sccm, Ar21 sccm, 300 ° C.) Al-0.5% Cu 500 nm (0.52 Pa, 15 kW) , Ar65sccm, 300 ℃) Ti10nm (0.52Pa, 2kW, Ar35sccm, 300 ℃) TiN100nm (0.78Pa, 6kW, N2 42sccm, Ar21sccm, 300 ℃) Lower conductor wiring processing: Anisotropic dry etching BCl3 / Cl2 = 100 / 150sccm , 1Pa, Microwave 400mA, RF 110W Just + 40% over etching Connection hole processing: Anisotropic dry etching CO / C4F8 / Ar = 100/7 / 200sccm, 2Pa, RF 1450W Just + 30% over etching

Thereafter, the lower conductor wiring at the bottom of the connection hole is etched by anisotropic dry etching (FIG. 7D).
Next, after the resist hardened layer by etching is removed by O ₂ ashing (FIG. 8A), the resist is removed by chemical cleaning (FIG. 8B). The processing conditions for the conductor wiring at the bottom of the connection hole and the conditions for removing the resist are shown below.

Connection hole bottom conductor wiring processing: BCl3 / Cl2 = 100 /
150sccm, 1Pa, Microwave 400mA, RF100W, Al300nm Etch Resist removal: Amine organic solvent 15 minutes + water flow treatment 1
0 minutes

Even if the connection hole formed through this process has a structure in which there is no allowance for misalignment with the lower conductor wiring, the deterioration of the shape due to the removal of the region with the fluorine remaining during the processing of the connection hole will not occur. Does not happen. Thereafter, an adhesion layer metal 7 is formed over the entire surface by, for example, a magnetron sputtering method, and a tungsten film 8 is embedded as a buried metal by a thermal CV method.
The entire surface is formed by the method D (FIG. 8C). Examples of the respective film forming conditions are shown below.

Adhesion layer metal formation: Film formation by magnetron sputtering method RF Etch 20 nm (0.52 Pa, 500 W, Ar5 sccm, no heating) Ti5 nm (0.52 Pa, 2 kW, Ar35 sccm, 150 ° C.) TiN 30 nm (0.78 Pa, 6.5 kW, N2) 135sccm, Ar15sccm, 150 ° C) Blanket W film CVD: 600nm (10.7kPa, WF6: H2: Ar = 40: 400: 2250sccm, 450 ° C)

The contact hole of the buried metal formed in this way has a good contact state with the side wall of the lower conductor wiring, so that the adhesion layer metal and the tungsten film have good adhesion and the buried state of the tungsten film is also good. Met. For this reason, the contact resistance and the yield were almost the same as those of a normal connection hole having no structure having a margin for misalignment, and there was no significant difference in the electromigration life.

The etching amount at the time of processing the conductor wiring at the bottom of the connection hole is preferably 200 nm or more and 500 nm or less in the Al alloy portion. If the etching amount is smaller than 200 nm in the Al alloy portion, the fluorine attached at the time of forming the contact hole is insufficient to remove the fluoride formed by reacting with Al, and the etching amount is set to 500 nm or less. This is because the thickness of the Al alloy part of the lower conductor part is 500 nm.

As described above, according to this example, in a multilayer wiring having a structure in which the lower conductor wiring and the connection hole do not have a margin for misalignment, it is possible to suppress deterioration of the shape of the side wall of the conductor wiring. A highly integrated and fine connection hole of a semiconductor device can be formed without deteriorating contact characteristics and wiring reliability.

The lower conductor wiring is not limited to the one used in the above embodiment. That is, a metal having a laminated structure of a metal such as an aluminum alloy, copper, or a copper alloy, or a high-melting metal such as titanium, a titanium alloy, tungsten, or a tungsten alloy can be used.

The present invention is not limited to the above-described embodiment, but may adopt various other configurations without departing from the gist of the present invention.

[0049]

As described above, in a multilayer wiring having a structure in which the lower conductor wiring and the connection hole do not have a margin for misalignment, deterioration in the shape of the side wall of the conductor wiring can be suppressed, and the contact characteristics and A highly integrated and fine connection hole of a semiconductor device can be formed without impairing wiring reliability.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process in Example 1 (part 1).

FIG. 2 is a cross-sectional view illustrating a manufacturing step in the first embodiment (part 2).

FIG. 3 is a cross-sectional view showing a manufacturing step in Example 2 (part 1).

FIG. 4 is a cross-sectional view showing a manufacturing step in the second embodiment (part 2).

FIG. 5 is a cross-sectional view showing a manufacturing step in the third embodiment (part 1).

FIG. 6 is a sectional view showing a manufacturing step in the third embodiment (part 2).

FIG. 7 is a cross-sectional view showing a manufacturing step in the fourth embodiment (part 1).

FIG. 8 is a sectional view showing a manufacturing step in the fourth embodiment (part 2).

FIG. 9 is a cross-sectional view showing a manufacturing process in a conventional example (part 1).

FIG. 10 is a sectional view showing a manufacturing step in the conventional example (part 2).

[Explanation of symbols]

1 base insulating film, 2 lower conductor wiring, 3 interlayer insulating film,
4 Photoresist, 5 connection holes, 6 Excavation of conductor wiring,
7 adhesion layer metal, 8 buried metal, 9 buried void, 10 plasma treatment, 11 modified layer by plasma treatment, 12 temperature oxidation treatment, 13 modified layer by hot oxidation treatment, 14 ion irradiation treatment, 15 modification by ion irradiation treatment Quality layer

Claims (24)

[Claims] A step of forming a lower conductor wiring having no margin for misalignment with respect to a connection hole on a base insulating film; and forming an interlayer planarization insulating film on the base insulating film and the lower conductor wiring. Depositing, forming a photoresist pattern for processing a connection hole, processing a connection hole with a lower conductor wiring by anisotropic dry etching, and removing a resist hardened layer by ashing processing Forming a modified layer on the side wall of the lower conductor wiring exposed through the connection hole; removing resist by a chemical cleaning process; removing the modified layer by reverse sputter cleaning; A method of manufacturing a semiconductor device, comprising: a step of forming a metal film over the entire surface; and a step of forming a buried metal film over the entire surface. 2. The step of forming a modified layer on a side wall portion of a lower conductor wiring exposed through a connection hole, comprising:
2. The method according to claim 1, wherein a modified layer is formed on a side wall of the lower conductor wiring. 3. The step of forming a modified layer on a side wall portion of a lower conductor wiring exposed through a connection hole, the plasma processing comprises:
2. The method of manufacturing a semiconductor device according to claim 1, wherein a modified layer having a thickness in a range of 5 nm or more and 20 nm or less is formed on a lower conductor wiring side wall. 4. The step of forming a modified layer on the side wall of the lower conductor wiring exposed through the connection hole is performed by a plasma treatment using nitrogen, oxygen, hydrogen, or a mixed gas of oxygen and hydrogen. 2. The method according to claim 1, wherein a modified layer is formed on the side wall. 5. The step of forming a modified layer on the side wall of the lower conductor wiring exposed through the connection hole is performed by plasma treatment using nitrogen, oxygen, hydrogen, or a mixed gas of oxygen and hydrogen. The thickness is 5 nm or more and 20 nm on the side wall.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a modified layer having the following range is formed. 6. The step of forming a modified layer on the lower conductor wiring sidewall exposed through the connection hole, wherein a nitride layer is formed on the lower conductor wiring sidewall by nitrogen plasma treatment. 2. The method for manufacturing a semiconductor device according to claim 1. 7. The step of forming a modified layer on the side wall of the lower conductor exposed through the connection hole is performed by a nitrogen plasma treatment to a thickness of 5 nm to 20 nm on the side of the lower conductor wiring.
2. The method according to claim 1, wherein a nitride layer having the following range is formed. 8. The lower conductor wiring is made of an aluminum alloy,
Metals such as copper and copper alloys, or a laminated structure of these and high-melting metals such as titanium, titanium-based alloys, tungsten, and tungsten-based alloys, and modified into lower conductor wiring sidewalls exposed through connection holes 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the layer, a nitride layer having a thickness of 5 nm or more and 20 nm or less is formed on the side wall of the lower conductor wiring by nitrogen plasma treatment. . 9. The step of forming a modified layer on a side wall portion of a lower conductor wiring exposed through a connection hole is performed by performing a hot hydroxylation treatment.
2. The method according to claim 1, wherein an oxide layer is formed on a side wall of the lower conductor wiring. 10. The step of forming a modified layer on the side wall of the lower conductor exposed through the connection hole is performed by hot water oxidation to form a film having a thickness of 5 nm or more and 20 nm on the side wall of the lower conductor.
2. The method according to claim 1, wherein an oxide layer having the following range is formed. 11. The lower conductor wiring has a laminated structure of a metal such as an aluminum alloy, copper, a copper alloy, or a high melting point metal such as titanium, a titanium alloy, tungsten, or a tungsten alloy. The step of forming the modified layer on the side wall of the lower conductor wiring exposed through the hole includes forming an oxide layer having a thickness in the range of 5 nm or more and 20 nm or less on the side wall of the lower conductor wiring by hot water oxidation. The method for manufacturing a semiconductor device according to claim 1, wherein: 12. The step of forming a modified layer on a side wall portion of a lower conductor wiring exposed through a connection hole, wherein the reforming layer is formed on a side wall portion of the lower conductor wiring by ion irradiation treatment. Item 2. A method for manufacturing a semiconductor device according to Item 1. 13. The step of forming a modified layer on the lower conductor wiring side wall exposed through the connection hole, wherein the film thickness is 5 nm to 20 nm on the lower conductor wiring side wall by ion irradiation treatment.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a modified layer having the following range is formed. 14. The step of forming a modified layer on the side wall of the lower conductor exposed through the connection hole is performed by irradiating oxygen, hydrogen, or nitrogen ions with the modified layer on the side of the lower conductor wiring. 2. The method according to claim 1, wherein
The manufacturing method of the semiconductor device described in the above. 15. The step of forming a modified layer on the lower conductor wiring side wall exposed through the connection hole includes the step of irradiating oxygen ion, hydrogen ion, or nitrogen ion with a film thickness on the lower conductor wiring side wall. 2. The method according to claim 1, wherein a modified layer having a thickness of 5 nm or more and 20 nm or less is formed. 16. The step of forming a modified layer on a side wall portion of a lower conductor wiring exposed through a connection hole includes forming an oxide layer on a side wall portion of the lower conductor wiring by oxygen ion irradiation treatment. Item 2. A method for manufacturing a semiconductor device according to Item 1. 17. The step of forming a modified layer on the lower conductor wiring side wall exposed through the connection hole includes the step of forming a film with a thickness of 5 nm or more on the lower conductor wiring side wall by oxygen ion irradiation treatment.
2. The method for manufacturing a semiconductor device according to claim 1, wherein an oxide layer having a thickness of not more than nm is formed. 18. The lower conductor wiring has a laminated structure of a metal such as an aluminum-based alloy, copper, or a copper alloy, or a high-melting-point metal such as titanium, a titanium-based alloy, tungsten, or a tungsten-based alloy. The step of forming the modified layer on the lower conductor wiring side wall exposed through the hole includes forming an oxide layer having a thickness in the range of 5 nm or more and 20 nm or less on the lower conductor wiring side wall by oxygen ion irradiation treatment. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: 19. A step of forming a lower conductor wiring having no allowance for misalignment with respect to a connection hole on a base insulating film; and forming an interlayer planarization insulating film on the base insulating film and the lower conductor wiring. Depositing, forming a photoresist pattern for processing a connection hole, processing a connection hole with a lower conductor wiring by anisotropic dry etching, and etching the lower conductor wiring at the bottom of the connection hole A step of removing the resist hardened layer by ashing, a step of removing the resist by a chemical cleaning treatment, and a step of depositing the entire surface of the adhesion layer metal and then depositing the embedded metal. Manufacturing method of a semiconductor device. 20. The semiconductor according to claim 19, wherein in the step of etching the lower conductor wiring at the bottom of the connection hole, the lower conductor wiring is etched within a range of not less than 200 nm and less than the thickness of the lower conductor wire. Device manufacturing method. 21. The lower conductor wiring has a laminated structure of a metal such as an aluminum-based alloy, copper, or a copper alloy, or a high-melting-point metal such as titanium, a titanium-based alloy, tungsten, or a tungsten-based alloy. 20. The step of etching the lower conductor wiring at the bottom of the hole, wherein the lower conductor wiring is etched within a range of not less than 200 nm and less than the thickness of the lower conductor wiring.
The manufacturing method of the semiconductor device described in the above. 22. A lower conductor wiring having no margin for misalignment with respect to the connection hole is formed on a base insulating film, and an interlayer planarization insulating film is formed on the base insulating film and the lower conductor wiring. A semiconductor device, wherein a connection hole for partially removing the lower conductor wiring is formed in the interlayer planarization insulating film, and a buried metal is formed on the connection hole and the interlayer planarization insulating film. 23. The semiconductor according to claim 22, wherein the connection hole deletes the lower conductor wiring from an upper part of the lower conductor wiring within a range of 200 nm or more and less than a thickness of the lower conductor wiring. apparatus. 24. The lower conductor wiring has a laminated structure of a metal such as an aluminum alloy, copper, a copper alloy, or a high melting point metal such as titanium, a titanium alloy, tungsten, or a tungsten alloy. The hole is formed so that the lower conductor wiring is 2
23. The semiconductor device according to claim 22, wherein the semiconductor device is deleted within a range of not less than 00 nm and less than the thickness of the lower conductor line.