CN107665877B - Component carrier with buried conductive strips - Google Patents
Component carrier with buried conductive strips Download PDFInfo
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- CN107665877B CN107665877B CN201610615063.7A CN201610615063A CN107665877B CN 107665877 B CN107665877 B CN 107665877B CN 201610615063 A CN201610615063 A CN 201610615063A CN 107665877 B CN107665877 B CN 107665877B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Abstract
The invention provides an element carrier and a method for electrically contacting a conductive strip, wherein the conductive strip is buried in an electrically insulating structure covered with an electrically conductive layer. The method includes i) forming a clearance hole in the conductive layer above the conductive strip, thereby exposing at least a portion of the electrically insulating structure below the clearance hole; ii) selectively removing exposed material of the electrically insulating structure, thereby exposing top and side surfaces of the conductive strip; and iii) covering at least a portion of the top surface and at least a portion of the side surface with a conductive material.
Description
Technical Field
The present invention generally relates to component carriers to be assembled with electronic components to form electronic assemblies. The invention relates in particular to an element carrier with a buried conductive strip (conductor track) and to a method for electrically contacting a conductive strip buried in an element carrier.
Background
Signal noise, which is severely limited by the roughness of interconnect structures such as conductive strips and clearance holes (access holes) formed within component carriers, is a common problem for high-speed digital circuit signal integrity. Therefore, various conductive layers such as very low profile copper foils and non-roughening adhesion promotion treatments have been introduced to address such problems associated with circuit trace (circuit trace).
However, the "accidental" antenna effect caused by the roughness of the vertical interconnect defined by mechanically drilled or laser drilled clearance holes still presents a serious obstacle to the further development of signal speed. Furthermore, vertical interconnects have been identified as a common weakness with respect to resistance to thermal and mechanical stresses.
Conventionally, the formation of clearance holes having a diameter in the μm range by laser irradiation is one of the key techniques in the production of High Density Interconnect (HDI) component carriers. Commercially available laser drilling systems typically utilize two laser technologies: CO22Laser technology and UV laser technology.
However, the application of these laser drilling methods may result in flaws in the walls of the clearance hole. For example, in the presence of conventional CO2During the process of laser beam making clearance holes in the component carrier, structures are obtained in which undercuts, cracks, glass bumps and slot wedges are usually present.
These disadvantages result in signal noise and limit signal integrity of, for example, high speed digital circuits.
Disclosure of Invention
The object of the invention is to reduce noise significantly, improve signal integrity to a high degree, and further increase the high speed signal rate in the component carrier.
In order to achieve the above object, a component carrier and a method for conducting a conductive tape according to the present invention are provided.
According to an exemplary embodiment of the invention, a component carrier is provided, comprising an electrically insulating structure, a conductive strip buried or embedded within the electrically insulating structure, and a patterned electrically conductive layer on the electrically insulating structure. Furthermore, the component carrier comprises clearance holes extending through the electrically insulating structure and the patterned electrically conductive layer and at least partially filled with electrically conductive material to cover at least a part of the top surface and at least a part of the side surface of the electrically conductive strip.
The described component carrier is based on the idea that a conductive strip buried within the electrically insulating structure of the component carrier can be easily accessed through or via suitable clearance holes. Since the conductive material at least partially covers both the clearance hole and the top and side surfaces of the conductive strip, a good and reliable conductivity can be obtained in the area of the clearance hole. The conductive material may be applied separately to the conductive strip through the clearance hole, for example, to contact the conductive strip with another conductive strip. This may provide the advantage that there will be multiple options to connect the conductive strip or strips. Thus, the flexibility of the conductive strip or strips within the contact element carrier is increased compared to the known art, which results in a better performance of the signal integrity, especially in case of high frequency applications.
According to another exemplary embodiment of the present invention, a method of electrically contacting a conductive strip is provided, wherein the conductive strip is buried within an electrically insulating structure covered with an electrically conductive layer. The method comprises the following steps: i) forming a clearance hole in the conductive layer above the conductive strip, thereby exposing at least a portion of the electrically insulating structure below the clearance hole; ii) selectively removing exposed material of the electrically insulating structure, thereby exposing top and side surfaces of the conductive strip; and iii) covering at least a portion of the top surface and at least a portion of the side surface with a conductive material.
The described method is based on the idea that clearance holes are formed in the electrically conductive layer and the electrically insulating structure of the component carrier, wherein the clearance holes expose the conductive strips buried in the electrically insulating structure. When the clearance holes are formed, a portion of the electrically conductive layer and a portion of the electrically insulating structure are selectively removed to expose the electrically conductive strap. Conductive material is then applied to the top and side surfaces of the conductive strip to, for example, connect the conductive strip with a further conductive strip. This may provide the advantage that the buried conductive tracks within the electrically insulating structure of the component carrier may be easily manufactured, since established process techniques may be applied. Furthermore, through the clearance holes, the conductive material may be individually applied to the conductive strip and/or strips to establish a high flexibility of multiple connections between the conductive strip and/or strips. In this way, the performance of the signal integrity can be improved, especially in the case of high frequency applications. Furthermore, due to the implementation of contactless (landless)/landless applications, a higher density of component carriers may be achieved.
In the context of the present application, the term "element carrier" may particularly denote any support structure capable of accommodating one or more electronic components thereon and/or therein for providing both mechanical support and electrical connectivity.
In the context of the present application, the term "clearance hole" may particularly denote a vertical structure within the component carrier. The formation of the clearance hole may be accomplished by laser drilling, by mechanical drilling, by photolithography, by etching techniques, or by a combination thereof. The clearance hole may also be referred to as a vertical interconnect access (via). The shape of the clearance hole may be tapered. Thus, an upper portion of the clearance hole extending from the top surface of the component carrier in the direction of the bottom surface of the component carrier may comprise a wider diameter than a lower portion of the clearance hole. The shape of the clearance hole may include other shapes such as a tube. Furthermore, the sidewalls of the clearance hole may be smooth and may be free of undercuts or cracks. The sidewalls of the clearance hole may include an angle θ relative to a bottom plane of the clearance hole and an angle relative to a top surface of the clearance hole. These angles may be precisely defined and the angle with respect to the bottom plane of the clearance hole and the angle with respect to the top surface of the clearance hole may be respectively equal throughout the entire circumference of the clearance hole.
In the context of the present application, the term "patterned conductive layer" may particularly denote a spatially or structurally patterned conductive layer, such as a copper foil. For example, the pattern of the conductive layer may be formed by a photolithographic process, by etching, or by mechanical drilling or laser drilling.
In the following, further exemplary embodiments of the contact method of the component carrier and the conductive strip will be explained.
According to an embodiment, the element carrier comprises at least one further conductive strip buried within the electrically insulating structure, wherein the conductive strip and the further conductive strip are interconnected to each other, in particular in a pad-free manner. This may provide the advantage that pads are avoided and thus signal integrity may be improved, in particular for high frequency applications.
The conductive strips may additionally be made of the same material as the conductive strips, such as copper or another conductive metal. The conductive strip and the further conductive strip may be buried or embedded within the same electrically insulating structure. The conductive strip and the further conductive strip may also be buried in different layers of the electrically insulating structure. The conductive strips and the further conductive strips may be oriented perpendicular to each other or in any other geometrical relationship with respect to each other. In addition, the number of the conductive strips is not limited, and a plurality of conductive strips may be present inside or on top of one element carrier. The conductive strips may comprise different geometric shapes, for example, the shape of the conductive strips in cross-section may be formed as a circle, square, rectangle, or trapezoid. The conductive strips may additionally have the same geometry as the conductive strips. Alternatively, the conductive strips may comprise another geometry as well as the conductive strips.
The pads are typically used to interconnect the conductive strips and serve to provide a large tolerance area at the intersection of the conductive strips. However, landless interconnects have the advantage of greatly improved signal integrity, particularly in the case of high frequency applications such as high speed digital circuits. This is advantageous to avoid pads in these cases where the pads introduce interference.
In the context of the present application, the term "pad-free" may particularly denote an interconnection between two conductive strips establishing an interconnection without the use of pads. In other words, at least two conductive strips may be interconnected at an intersection region or intersection area without an expansion or widening. The term "no pad" may also be referred to as "no contact". In this regard, the pads are conventionally used to interconnect conductive strips and function to provide a large tolerance area between conductive strips in the crossover region. Especially in the case of high frequency applications, signal integrity is defined by the bond pads.
According to a further embodiment, the conductive strip and the further conductive strip intersect within the electrically insulating structure when viewed in a direction parallel to a normal vector to the plane of the conductive layer. Furthermore, the crossing region between the conductive strip and the further conductive strip is located within the clearance hole. Since the conductive strips can extend in all possible geometrical directions through the electrically insulating layer of the component carrier and can be interconnected in each desired manner, this offers the advantage that the design of the component carrier can be realized in an extremely flexible manner.
The conductive layer may be placed on the electrically insulating structure in the form of a layer, and thus the conductive layer may be considered as a plane. Mathematically, each planar structure has a normal vector, where this normal vector can be used to define a viewing direction parallel to the normal vector. The viewing direction can also be defined as a top view (from above) on a conductive layer placed on or above the component carrier. In the viewing direction, the conductive strips and the further conductive strips may be perpendicular with respect to each other, and the crossing regions may have a crossing form or shape. Thus, the conductive strips may be at least substantially at the same depth level or at different depth levels within the electrically insulating structure with respect to the viewing direction.
According to a further embodiment, the conductive strip and the further conductive strip are interconnected in a pad-free manner by the conductive material. This may provide the advantage of a highly improved signal integrity due to the pad-less approach, especially in the case of high-speed digital circuits. Furthermore, the interconnections can be established in a fast and flexible manner.
The conductive material may be applied to the crossing areas of the conductive strip and the further conductive strip by a chemical or physical process, for example by an electrical, electroplating, filling, vapour deposition or mechanical process or a combination of these processes.
According to a further embodiment, the clearance hole is at least partially filled with an electrically conductive material. This may provide the advantage that a very large area is covered by the conductive material, as a result of which the crossing areas of the conductive strips are interconnected very reliably and with large tolerances, thereby making manufacture easier. Furthermore, the disadvantages of pad connection are avoided.
In this embodiment, the clearance hole may be completely or partially filled with a conductive material. Filling the clearance hole may be accomplished by a chemical process or a physical process, such as by an electrical process, an electroplating process, or a mechanical process, or a combination of these processes. The conductive material may be filled to a level within the clearance hole such that the conductive material contacts the conductive layer. The conductive material may be filled to a level within the clearance hole such that the conductive material is not in contact with the conductive layer.
According to a further embodiment, the conductive material is formed by vapor deposition within the clearance hole. This may provide the advantage that a very large area may be covered by the conductive material, so that the crossing areas of the conductive strips may be interconnected in a reliable manner. Furthermore, the interconnection may be achieved with relatively large tolerances, thereby making the manufacture of the interconnection easier. Furthermore, the known disadvantages of pad connections can be avoided. In addition, since only a small amount of conductive material is required for vapor deposition, material resources can be saved.
In this embodiment, the conductive material has been completely or partially vapor deposited in the clearance hole. In this regard, it is noted that vapor deposition of the conductive material may also be combined with other processes of the conductive material, such as galvanic deposition.
According to a further embodiment, the clearance hole comprises a predetermined sidewall angle and a predetermined depth.
The walls of the clearance hole may include an angle θ relative to a bottom plane of the clearance hole and an angle relative to a top plane of the clearance hole. These angles may be precisely defined, i.e., predefined, and the angle with respect to the bottom plane of the clearance hole and the angle with respect to the top plane of the clearance hole may be equal throughout the entire circumference of the clearance hole.
According to a further embodiment, the clearance hole is crack-free and/or undercut-free. This may provide the advantages of significantly reduced sidewall roughness, clean and reliable clearance hole bottom connections, no wedges at the clearance hole bottom connections, optimized clearance hole geometry for more efficient and safe metallization and clearance hole filling processes, reduced clearance hole size and spacing. The described clearance hole geometry may have the following advantages: more efficient and safe metallization and clearance hole filling processes, reduced clearance hole size and spacing, higher interconnect density, increased conductive anode wire (CAF) resistance, increased Thermal Cycling Test (TCT) performance, minimized "accidental" antenna effects, minimized cross talk, reduced signal noise and/or increased signal integrity at higher signal clock frequencies, and options to be implemented in standard HDI or substrate manufacturing processes.
Such high quality clearance holes may be formed by laser means, in particular excimer lasers. The use of smooth sidewall clearance holes, particularly glass for reinforcing build-up structures, may not be previously known in the interconnect industry. In the context of the present application, the term "build-up-enhancing glass" may particularly denote a glass cloth filled with a resin, such as FR4, a prepreg material or similar.
According to a further embodiment, for the example of a printed circuit board as component carrier, the clearance hole is a via hole with a diameter in the range of 25 μm-200 μm, in particular 50 μm-100 μm. The skilled person is aware of the fact that smaller diameters are used for substrate technology. This may provide the advantage that the described component carrier may be provided with usual clearance holes. As a result, well-known process techniques for forming so-called μ -level via (micro-level via) clearance holes may be utilized. Such small vias can be made by UV-lasers or excimer lasers (especially for dimensions smaller than 50 μm). CO22Lasers may be particularly useful for producing sizes greater than 50 μm (although such lasers may also be useful for producing sizes less than 50 microns).
According to a further embodiment, the component carrier comprises or consists of a stack of at least one further electrically insulating layer structure and at least one further electrically conductive layer structure.
For example, the component carrier can be a laminate (laminate) composed of the electrically insulating layer structure and the electrically conductive layer structure mentioned, in particular, by applying mechanical pressure, optionally supported by thermal energy. The mentioned stack may form a plate-like component carrier which is capable of providing a large mounting surface for further electronic components but which is very thin and compact.
The term "layer structure" may particularly denote a continuous layer, a patterned layer or a spatial structure layer or a plurality of non-continuous islands (isles) within a common layer. Thus, the component carrier described herein may also comprise a multilayer structure of electrically insulating structures and a multilayer structure of electrically conducting layer structures, wherein the number of layers is not limited.
According to a further embodiment, the at least one electrically insulating layer structure and/or the at least one further electrically insulating structure comprises at least one of the group consisting of plexiglas, in particular bismaleimide triazine resin, cyanate ester, glass, in particular glass fibre, prepreg material, polyimide, liquid crystal polymer, build-up film (epoxy-build-up film), FR4 material, ceramic and metal oxide. While prepreg or FR4 is generally preferred, other materials may be used.
This may provide the advantage that the described element carrier with its advantageous effects may be achieved by using well known and recognised process techniques.
According to a further embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum and nickel.
Moreover, this may provide the advantage that the described element carrier with its advantageous effects may be achieved by employing well known and accepted process techniques.
It is pointed out that copper may be a preferred material in order to realize the described element plate in a simple and efficient manner. It is further noted that other materials for forming the conductive layer structure may also be used.
According to a further embodiment, the element carrier is shaped like a plate.
This may provide the advantage that the component carrier may be realized with a compact design, wherein the component carrier may nevertheless provide a large space base for mounting a plurality of electronic components thereon.
According to a further embodiment, the component carrier is a multilayer component carrier. In particular, the component carrier is a composite of several layer structures which are stacked on one another and joined together by applying pressure, if appropriate with the application of heat. At least some of the layers of the multilayer structure may be or may be realized by so-called prepreg layers.
According to a further embodiment, the component carrier is configured as one of the group consisting of a printed circuit board and a substrate.
In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier which is formed by laminating some electrically conductive layer structures with some electrically insulating layer structures, for example by applying pressure, possibly accompanied by a supply of thermal energy. As a preferred material for PCB technology, the electrically conductive layer structure is made of copper, while the electrically insulating layer structure may comprise resin and/or glass fibre, so-called prepreg material or FR4 material. The various conductive layer structures can be connected to each other in a desired manner by forming through-holes through the laminate, for example by laser drilling or mechanical drilling, and by filling them with a conductive material, in particular copper, so as to form vias as through-hole connections. In addition to one or more electronic components that may be embedded in a printed circuit board, printed circuit boards are typically configured to receive one or more electronic components on one or both opposing surfaces of a plate-like printed circuit board. They may be joined to the respective major surfaces by brazing.
According to a further embodiment, a method is described that includes forming a pattern in a conductive layer by a photolithographic process and using such pattern as a conformal mask for forming clearance holes.
The creation of the clearance sidewalls may be accomplished by a variety of different process techniques. This may be accomplished, for example, by etching a pattern of clearance holes in the conductive layer in a photolithographic process and using such pattern as a conformal mask for clearance holes drilled using a cold ablation process. Another option is to apply a projection mask ablation process in which a mask containing the desired clearance hole pattern with a determined magnification ratio is placed in the optical path of the laser beam. Also, a combination of a multi-laser beam generator and a deflection mirror processing device can be performed. In this method, at least two laser spots, which are assigned to different laser devices and have a defined focal spot size, are simultaneously guided to the desired position of the respective clearance hole. This may provide the advantage that the area of the clearance hole to be placed will be accurately defined.
According to a further embodiment, forming the clearance hole and/or selectively removing the exposed material is at least partially performed by laser ablation. This may provide the following advantages: the clearance hole is formed by laser ablation and laser drilling, respectively, which may be more accurate, faster, and better adjusted by the user than other processes such as mechanical drilling or etching.
According to a further embodiment, the forming of the clearance hole is performed by a first type of laser device, the selectively removing of the exposed material is performed by a second type of laser device, wherein the second type of laser device is different from the first type of laser device.
Combined with conventional CO2Laser or UV laser, Laser Direct Drilling (LDD) process may follow the excimer laser ablation procedure to complete clearance holes and/or clean areas around conduction bands, such as contact pad (bonding pad) connections, where CO2A laser or UV laser is used to create clearance holes in the conductive layer, such as via openings in copper foil used as a conformal mask.
This may provide the advantage that the intensity of each type of laser radiation with respect to wavelength and physical properties may be applied separately. For example, CO2Lasers are not suitable for ablating metals such as copper. Thus, CO2The laser beam may ablate the electrically insulating layer and then stop ablating when in contact with the conductive tape. The conductive band may be formed by, for example, reflecting CO2The laser beam is made of copper metal. Other types of lasers, such as excimer lasers or UV lasers, may then be applied to ablate the copper of the conductive strips.
According to a further embodiment, in order to form the clearanceHoles and/or for selectively removing exposed material, using a material selected from the group consisting of excimer laser, CO2Laser means in the group consisting of a laser, a UV laser and an N-YAG laser.
The state of the art laser drilling processes in high density interconnect (HDL) applications are typically based on CO2A laser. CO22The laser emits infrared light having a wavelength between 9.3 μm and 10.6 μm. By CO2The laser beam created holes show typical shapes with copper overhang (copper overhand) and cracks along the glass fiber. Furthermore, when using a CO2 laser beam, the bottom of the clearance hole cannot be precisely defined and a wedge of polymer material can be left behind. This can be considered a serious reliability problem. CO22Lasers may be fully capable of ablating organic substrates, however, they cannot guarantee the formation of residue-free holes because of the CO2The laser beam is reflected by the metal layers, and therefore, energy absorption by each metal layer is reduced. Thus, chemical desmutting or plasma etching may be required as another continuous process step to clean the final residue from the bottom of the clearance hole. In case of one attempt to use CO2Where the laser completely removes all residues, a high amount of laser energy may be required, which may often lead to increased undercutting and undesirable delamination risks. In addition, CO2The relatively long wavelength of the laser may limit the formation of clearance holes less than 50 μm (microns) in diameter.
Most UV Diode Pumped Solid State (DPSS) lasers operate at a frequency tripled wavelength of 355nm for the formation of clearance holes with diameters in the μm range. Ultraviolet light having a wavelength of 355nm will be absorbed by a variety of materials such as copper, epoxy, polyimide, and glass. Furthermore, such light will be emitted with very short high power pulses. Accurate focusing to a small spot resulting in very high power density can produce a very concentrated plasma that allows precise ablation of various materials. The advantages of the new generation of lasers may be high peak power, high repetition rate, excellent beam quality. They can also be obtained with frequency conversion down to the fourth harmonic (266 nm). The combination of high beam quality and short wavelength can produce very small spot sizes (5 μm-20 μm) at the area of application and allow the formation of small clearance holes with diameters in the μm range. The small spot size and low average power of the UV DPSS laser may help slow the formation speed because the beam may be induced to form clearance holes with a μm range diameter greater than 25 microns. The standard mean gap aperture may comprise a diameter of 75 microns or 100 microns, which translates to a slower processing speed for a single UV DPSS laser. Femtosecond lasers can include superior processing quality and the ability to produce much smaller features.
In this respect, it is mentioned that material ablation by excimer laser devices is a precision patterning dry process. In the context of the present application, the term "dry" may particularly denote a treatment that does not use wet chemistry.
Thus, a strong ultraviolet beam from an excimer laser can be used to directly pattern a material. This technique is used in industrial applications for patterning both organic and inorganic materials. Excimer lasers can be used at the following UV laser wavelengths: 157nm, 193nm, 248nm, 308nm, and 351 nm. Excimer laser micromachining may allow each laser pulse to remove material in succession. Uniform power distribution over the area may allow for controlled and continuous removal of material to a desired depth. In the fabrication of microelectronic devices, laser ablation may be used to pattern electrically insulating layers. Excimer laser projection ablation is very similar to optical projection lithography, both using a photomask or reticle (reticle) that includes a host pattern. Short wavelengths provide two major advantages: it may allow very small features to be produced and the impact on surrounding materials due to non-thermal interactions may be minimal. Although such as neodymium-doped yttrium aluminum garnet (Nd: YAG) lasers and CO2Other lasers of lasers are also widely used in HDI technology, but excimer laser ablation may be indispensable as it achieves "fine" micro-and nano-fabrication. This is particularly true for hard and delicate materials. The wavelength, pulse duration, and pulse energy of the excimer laser can be advantageous for performing a "cold ablation" process. In the context of the present application, the term "cold ablation process" may particularly denote a treatment without thermal shock to the material, i.e. vaporization without melting in between.
An excimer laser can project a pattern onto a sample with a minimal Heat Affected Zone (HAZ). The minimum HAZ is caused by the short interaction time between the laser beam and the material. In addition, the short pulse duration of the excimer can also be a factor. Furthermore, picosecond lasers and femtosecond lasers are now available. This type of laser is designed to further reduce the HAZ. They are also characterized by higher etch rates, strong material absorption, increased surface roughness, and lower ablation thresholds.
According to a further embodiment, the method further comprises cleaning the area around the conductive strip by an excimer laser. This may provide the advantage that the excimer laser is more accurate and does not require an additional wet chemical step. Thus, resources and time can be saved.
This excimer laser cleaning step can replace the traditional wet chemical decontamination process.
Drawings
The aspects defined above and further aspects of the present invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.
Fig. 1 shows a cross-sectional view of an element carrier with a buried conductive strip according to an exemplary embodiment of the present invention.
Fig. 2 shows a sectional view illustrating a first process step of producing the component carrier shown in fig. 1.
Fig. 3-5 show top views of component carriers according to further embodiments of the invention.
Fig. 6 shows a cross-sectional view of a structure obtained during execution of a method of manufacturing a component carrier according to an exemplary embodiment of the invention.
Fig. 7 shows a cross-sectional view of a structure obtained during execution of a method of manufacturing a component carrier according to another exemplary embodiment of the invention.
Fig. 7' shows a cross-sectional view of the structure of fig. 7, rotated 90 ° about a normal vector to the plane of the patterned conductive layer compared to fig. 7.
Fig. 8 shows a cross-sectional view of a structure obtained during the manufacture of a component carrier according to another exemplary embodiment of the present invention.
Fig. 9 shows a cross-sectional view of a structure obtained during execution of a method of manufacturing a component carrier according to an exemplary embodiment of the invention.
Fig. 10 shows a cross-sectional view of a structure obtained during execution of a method of manufacturing a component carrier according to another exemplary embodiment of the invention.
Fig. 11 shows a top view of a component carrier according to a further embodiment of the invention.
Detailed Description
In different drawings, similar or identical elements are provided with the same reference signs.
Before exemplary embodiments will be described in further detail with reference to the accompanying drawings, some basic considerations will be outlined based on the exemplary embodiments of the present invention that have been developed.
According to an exemplary embodiment of the invention, the improved shape of the clearance hole and the improved sidewall roughness in the clearance hole are provided by using a cold ablation laser micro-machining process for clearance hole formation. Polymer and glass materials exposed to short pulse laser beam irradiation at high energy density are continuously removed in an ablation process to form a preferably smooth V-shaped clearance hole. Due to the high absorption, the reflected laser beam cannot penetrate the sidewalls, which eliminates the risk of copper overhang. The minimized thermal interaction prevents any cracking along the glass fiber.
According to an exemplary embodiment of the invention, the production process may be performed by excimer laser micromachining, short pulse solid state UV lasers (picosecond lasers or femtosecond lasers) or a combined sequence of IR and UV lasers.
According to an exemplary embodiment of the invention, if it is associated with an established CO2By creating clearance holes with diameters in the μm range in a cold ablation process, a significant reduction in hole wall roughness may be achieved compared to a UV laser drilling scheme.
According to the exemplary embodiments of the present invention, it is possible to provide significantly reduced noise and highly improved signal integrity, thereby achieving further improvement in the clock rate of a high-speed signal. Clearance holes with defined sidewall angles allow for efficient metallization and higher reliability performance. Based on the crack-free overhang-free formation, reduction in the size and distance of the clearance hole can be achieved, thereby enabling an increase in the interconnection density and further miniaturization of electronic devices with enhanced functions.
Fig. 1 shows a component carrier 100 according to an embodiment of the invention. The element carrier comprises an electrically insulating structure 102, a conductive strip 104 buried within the electrically insulating structure 102, and a patterned conductive layer 106 on or over the electrically insulating structure 102. Furthermore, the component carrier 100 comprises clearance holes 108, the clearance holes 108 extending through the electrically insulating structure 102 and the patterned electrically conductive layer 106 and being at least partially filled with an electrically conductive material 110 so as to cover a top surface 111 of the conductive strip 104 and side surfaces 112 of the conductive strip 104. Furthermore, the conductive material 110 covers the sidewalls 109 of the clearance hole 108 such that the conductive material 110 covers the electrically insulating structure 102 and the conductive strip 104. The shape of the conductive strip 104 has a trapezoidal shape with a top surface 111 and two side surfaces 112 of equal length. The bottom surface of the conductive strap 104 is longer than the top surface 111. The sidewalls 120 of the clearance hole 108 are smooth and free of undercuts and cracks. In addition, there is a wall angle θ defined by the bottom plane of the clearance hole 108 and the sidewall 120. In addition, there is an ablation depth d of the clearance hole 108. Within the component carrier 100, there is a three-dimensional interface between the clearance hole 108 and the conductive strip 104 due to the top surface 111 and the side surfaces 112.
Fig. 2 shows an embodiment of a raw component carrier 200 for manufacturing a component carrier according to an embodiment of the invention. The component carrier 200 comprises an electrically insulating structure 102 with an electrically conductive layer 106 on top. A plurality of conductive strips 104 are buried within the electrically insulating structure 102 of the green component carrier 200.
Fig. 3 shows a top view of an embodiment of the component carrier 100. Similar to the cross-sectional view in fig. 1, the component carrier 100 is covered by a conductive layer 106. The conductive strips 104 are buried within electrically insulating structures (not shown here). Further, the area where the clearance hole 108 is drilled is indicated by circle 310. The circle illustrates the maximum diameter of the conical clearance hole 108.
Fig. 4 shows a top view of a further embodiment of the component carrier 100. In addition to the conductive strip 104, there is an additional conductive strip 210. Thus, the conductive strip 104 and the further conductive strip 210 intersect within an electrically insulating structure (not shown). In this embodiment, the conductive strip 104 and the further conductive strip 210 are oriented perpendicular to each other. The intersection region 410 between the conductive strip 104 and the additional conductive strip 210 is located in a central region of the clearance hole 108.
Fig. 5 shows a top view of a further embodiment of the component carrier 100. Fig. 5 shows the conductive strip 104 and the further conductive strip 210, wherein the conductive strips 104, 210 extend in directions perpendicular to each other from an intersection region 410 in the region where the clearance hole 108 is drilled. Thereby, the conductor track 104 and the further conductor track 210, respectively, extend from the intersection region 410 in only one direction. In this embodiment, the conductive strip 104 and the further conductive strip 210 are interconnected by a crossover region 410 to form a right angle connection.
Fig. 6 shows a cross-sectional view of a structure obtained during execution of a method of manufacturing a component carrier according to an exemplary embodiment of the invention.
Fig. 6a shows a raw component carrier 600 with an electrically conductive layer 106 and an electrically insulating structure 102. Furthermore, fig. 6a shows the conductive strip 104 and the further conductive strip 210. Thus, the conductive strip 104 and the further conductive strip 210 intersect within the electrically insulating structure 102 in an imaginary intersection area 410, when viewed in a direction parallel to a normal vector to the plane of the electrically conductive layer 106. Thus, the conductive strips 104, 210 do not intersect in a cross-sectional plane.
Fig. 6b shows that after fig. 6a, clearance holes 108 have been drilled through the conductive layer 106, through the electrically insulating structure 102 and also through the conductive strip 104. An imaginary intersection area 410 between the conductive strip 104 and the further conductive strip 210 is located within the clearance hole 108. For example, material that reaches (but does not include) the conductive strips 104 may be removed by Laser Direct Drilling (LDD) or Copper Direct Drilling (CDD), and material of the conductive strips 104 may be removed by an excimer laser or a UV laser.
Fig. 6c shows that the clearance hole 108 has been filled with a conductive material 304, such as copper. In this embodiment, the conductive strip 104 and the further conductive strip 210 are interconnected to each other by a conductive material 304, the conductive material 304 being filled in the clearance hole 108 in a pad-free manner. In this embodiment, the conductive material 304 also contacts the conductive layer 106.
Fig. 6d shows an alternative structure to that shown in fig. 6 a. As such, a portion of patterned conductive layer 106 has been removed through the conformal mask to expose electrically insulating structure 102.
Fig. 7 shows a cross-sectional view of a structure obtained during execution of a method of manufacturing a component carrier according to another exemplary embodiment of the invention.
Fig. 7a shows an electrically insulating structure 102 with a conductive layer 106 on top and with a buried conductive strip 104.
Fig. 7b shows that after fig. 7a, clearance holes 108 have been drilled through the electrically conductive layer 106 and the electrically insulating structure 102. In this manner, the conductive strip 104 with its side walls or surfaces 112 has been exposed.
FIG. 7c shows that after FIG. 7b, conductive material 110 (during the first copper deposition process) has been deposited to cover and connect the conductive layer 106, the electrically insulating structure 102 and the conductive strap 104.
Fig. 7d shows that after fig. 7c, the clearance hole 108 (during the second copper deposition process) has been completely filled with the conductive material 304. This process of completely filling the conductive material 304 is optional.
Fig. 7e shows that after fig. 7d, a portion of the conductive material 304 that had previously covered the conductive layer 106 has been structured together with the conductive layer 106 and the conductive material 110 to form a further patterned conductive layer 750 (which is a conductive tape).
Fig. 7' shows a cross-sectional view of the structure of fig. 7, rotated 90 ° about a normal vector to the plane of the patterned conductive layer compared to fig. 7.
Fig. 7 a' shows an electrically insulating structure 102 with a conductive layer 106 on top and with a buried conductive strip 104.
Fig. 7b 'shows that after fig. 7 a', clearance hole 108 has been perforated through electrically conductive layer 106 and electrically insulating structure 102. In this manner, the conductive band 104 has been exposed.
FIG. 7c 'shows that after FIG. 7 b', conductive material 110 has been deposited to cover and connect conductive layer 106, electrically insulating structure 102 and conductive strip 104.
Fig. 7d 'shows that after fig. 7 c', the front clearance hole 108 has been completely filled with the conductive material 304. This process of completely filling with the conductive material 304 is optional.
Fig. 7 e' shows the further patterned conductive layer 750 in a direction rotated by 90 deg. compared to fig. 7 e. The generally V-shaped recess shown in figure 7 e' may also be circular.
Fig. 8 illustrates a photolithographic process for forming a pattern in conductive layer 106. This pattern is used as a conformal mask for forming the clearance holes 108 according to embodiments described herein.
Fig. 8a shows an unfinished element carrier 800 comprising a core layer 810, an electrically insulating structure 102, an electrically conductive layer 106 covered by a sacrificial layer 806, and an electrically conductive strip 104 buried within the electrically insulating structure 102.
Fig. 8b shows a component carrier 801, in which a step of removing the sacrificial layer 806 at the regions in which the clearance holes 108 to be drilled are respectively formed has been carried out.
Fig. 8c shows the component carrier 802, wherein the step of etching the conductive layer 106 has been performed.
Fig. 8d shows the element carrier 803, wherein a final step of removing the sacrificial layer has been performed.
Fig. 8e shows a component carrier 804 in which clearance holes 108 have been formed by laser ablation to provide access to the conductive strips 104.
Still referring to fig. 8, which is optional (with respect to conformal mask and large window processing after the excimer laser process), Laser Direct Drilling (LDD) or Copper Direct Drilling (CDD) may also be performed.
Fig. 9 shows a component carrier 100 identical to the component carrier of fig. 1. Laser apparatus 900 is used to perform controlled depth ablation of electrically conductive layer 106 and electrically insulating structure 102 with laser beam 901. The laser device 900 may be a conventional CO2A laser or a UV laser.
Fig. 10 shows a cross-sectional view of a structure obtained during execution of a method of manufacturing a component carrier according to an exemplary embodiment of the present invention. The component carrier 100 is the same as the component carrier of fig. 1. The laser device 950 is used to perform controlled depth ablation of the conductive strips 104 and the electrically insulating structures 102 with a laser beam 951. According to an exemplary embodiment described herein, the laser device 950 is an excimer laser or a UV laser. The laser beam 951 of the laser device 950 ablates the top surface 111 and the side surface 112 of the conductive ribbon 104 such that, in cross-section, the shape of the conductive ribbon 104 is trapezoidal. In addition, the laser beam 951 ablates the sidewalls 120 of the clearance hole 108 so that these sidewalls 120 are smooth and free of undercuts and cracks.
Fig. 11 shows a top view of a component carrier 100 according to a further embodiment of the invention. There are shown parallel conductive strips 104 in the horizontal direction and a patterned conductive layer structure 106 perpendicular to these conductive strips 104, the patterned conductive layer structure 106 intersecting the conductive strips 104 when viewed in top plan view. At a particular intersection 1100, the clearance hole has been, for example, passed through the CO, as described above2Laser followed by excimer laser or UV laser drilling (perpendicular to the plane of the paper in fig. 11). At these particular intersections 1100, the conductive strip 104 and the patterned conductive layer structure 106 are electrically connected in a pad-free or contact-free manner, since the clearance holes 108 have been filled with a conductive material, as has been shown above. The conductive strip 104 may be a buried conductive strip (i.e., may extend in another plane or layer than the patterned conductive layer structure 106).
It should be noted that the term "comprising" does not exclude other elements or steps and the "a" or "an" does not exclude a plurality. Also elements described in association with different embodiments may be combined.
It should be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.
The practice of the invention is not limited to the preferred embodiments shown in the drawings and described above. On the contrary, many variations are possible using the principles according to the invention and the solutions shown, even in the case of fundamentally different embodiments.
Claims (27)
1. A component carrier (100) comprising:
an electrically insulating structure (102);
a conductive strip (104) buried within the electrically insulating structure (102);
a patterned electrically conductive layer (106) on the electrically insulating structure (102);
a clearance hole (108) extending through the electrically insulating structure (102) and the patterned electrically conductive layer (106) and at least partially filled with an electrically conductive material (110) to cover at least a portion of a top surface (111) and at least a portion of a side surface (112) of the electrically conductive strip (104),
wherein the element carrier (100) comprises at least one further conductive strip (210) buried within the electrically insulating structure (102),
wherein the conductive strip (104) and the further conductive strip (210) are interconnected in a landless manner by the conductive material (110).
2. The component carrier (100) according to claim 1,
wherein the conductive strip (104) and the further conductive strip (210) intersect within the electrically insulating structure (102) when viewed in a direction parallel to a normal vector to the plane of the electrically conductive layer (106), and
wherein an intersection region (410) between the conductive strip (104) and the further conductive strip (210) is located within the clearance hole (108).
3. The component carrier (100) according to claim 1 or 2, wherein the clearance hole (108) is at least partially filled (304) with the electrically conductive material (110).
4. The component carrier (100) according to claim 1 or 2, wherein the electrically conductive material (110) results from a vapor deposition (404) within the clearance hole (108).
5. The component carrier (100) according to claim 1 or 2, wherein the clearance hole (108) comprises a predetermined sidewall angle (θ) and a predetermined depth (d).
6. The element carrier (100) according to claim 1 or 2, wherein the clearance hole (108) is crack-free and/or undercut-free.
7. The component carrier (100) according to claim 1 or 2, wherein the clearance hole (108) is a via hole with a diameter in the range of 25 μ ι η -125 μ ι η.
8. The component carrier (100) according to claim 7, wherein the clearance hole (108) is a via hole with a diameter in the range of 75-100 μm.
9. The component carrier (100) according to claim 1 or 2, wherein the component carrier (100) comprises or consists of a stack of at least one further electrically insulating structure and at least one further electrically conductive layer.
10. The element carrier (100) according to claim 9, wherein the electrically insulating structure (102) and/or the at least one further electrically insulating structure comprises at least one of the group consisting of a resin, a cyanate ester, glass, a prepreg material, a polyimide, a liquid crystal polymer, an epoxy build-up film, a FR4 material, a ceramic, and a metal oxide.
11. The component carrier (100) according to claim 10, wherein the resin is bismaleimide triazine resin and the glass is glass fiber.
12. The component carrier (100) according to claim 9, wherein the electrically conductive layer (106) and/or the at least one further electrically conductive layer comprises at least one of the group consisting of copper, aluminum and nickel.
13. The component carrier (100) according to claim 1 or 2, wherein the component carrier (100) is shaped like a plate.
14. The component carrier (100) according to claim 1 or 2, wherein the component carrier (100) is a multilayer component carrier.
15. The component carrier (100) according to claim 1 or 2, wherein the component carrier (100) is configured as one of the group consisting of a printed circuit board and a substrate.
16. The component carrier (100) according to claim 1 or 2, wherein the electrically conductive tape (104) and the patterned electrically conductive layer (106) are electrically coupled by the electrically conductive material (110) without a pad.
17. A method of electrically contacting a conductive strip (104) buried within an electrically insulating structure (102) covered with an electrically conductive layer (106), the method comprising:
forming a clearance hole (108) in a conductive layer (106) above the conductive strap (104), thereby exposing at least a portion of the electrically insulating structure (102) below the clearance hole (108);
selectively removing exposed material of the electrically insulating structure (102) thereby exposing a top surface (111) and side surfaces (112) of the electrically conductive strap (104);
covering at least a portion of the top surface (111) and at least a portion of the side surface (112) with a conductive material (110), an
-interconnecting the conductive strip (104) and a further conductive strip (210) in a landless manner by means of the conductive material (110).
18. The method of claim 17, further comprising:
forming a pattern in the conductive layer (106) by a lithographic process, and
the pattern is used as a conformal mask for forming the clearance hole (108).
19. The method of claim 17, further comprising:
processing the conductive layer (106) by laser direct drilling or copper direct drilling for forming the clearance hole (108).
20. The method of any of claims 17-19, wherein forming the clearance hole (108) and selectively removing exposed material is performed at least in part by laser ablation.
21. The method of claim 20, wherein forming the clearance hole (108) is performed by a first type of laser device (900), selectively removing exposed material is performed by a second type of laser device (950), wherein the second type of laser device (950) is different from the first type of laser device (900).
22. The method of claim 20, wherein for forming the clearance hole (108) and/or selectively removing exposed material, use is made of a material selected from the group consisting of excimer laser, CO2Laser, UV laser, short pulse laser, and Nd: YAG laser (900, 950).
23. The method of claim 22, wherein the short pulse laser is one of a picosecond laser and a femtosecond laser.
24. The method of any one of claims 17-19, further comprising:
the area around the conduction band (104) is cleaned by an excimer laser.
25. The method of any one of claims 17-19,
wherein the conductive strip (104) and the further conductive strip (210) intersect within the electrically insulating structure (102) when viewed in a direction parallel to a normal vector to the plane of the electrically conductive layer (106), and
wherein an intersection region (410) between the conductive strip (104) and the further conductive strip (210) is located within the clearance hole (108).
26. The method of claim 25, wherein interconnecting further comprises:
filling the clearance hole (108) with the conductive material (110).
27. The method of claim 25, wherein interconnecting further comprises:
vapor depositing the conductive material (110) within the clearance hole (108).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610615063.7A CN107665877B (en) | 2016-07-29 | 2016-07-29 | Component carrier with buried conductive strips |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610615063.7A CN107665877B (en) | 2016-07-29 | 2016-07-29 | Component carrier with buried conductive strips |
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| Publication Number | Publication Date |
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| CN107665877B true CN107665877B (en) | 2021-05-25 |
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| US5286674A (en) * | 1992-03-02 | 1994-02-15 | Motorola, Inc. | Method for forming a via structure and semiconductor device having the same |
| JPH10209272A (en) * | 1997-01-16 | 1998-08-07 | Sony Corp | Semiconductor device and its manufacture |
| CN102318452A (en) * | 2009-02-12 | 2012-01-11 | 住友电木株式会社 | Resin composition for wiring board, resin sheet for wiring board, composite body, method for producing composite body, and semiconductor device |
| CN105321930A (en) * | 2014-06-02 | 2016-02-10 | 英飞凌科技股份有限公司 | Vias and methods of formation thereof |
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2016
- 2016-07-29 CN CN201610615063.7A patent/CN107665877B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5286674A (en) * | 1992-03-02 | 1994-02-15 | Motorola, Inc. | Method for forming a via structure and semiconductor device having the same |
| JPH10209272A (en) * | 1997-01-16 | 1998-08-07 | Sony Corp | Semiconductor device and its manufacture |
| CN102318452A (en) * | 2009-02-12 | 2012-01-11 | 住友电木株式会社 | Resin composition for wiring board, resin sheet for wiring board, composite body, method for producing composite body, and semiconductor device |
| CN105321930A (en) * | 2014-06-02 | 2016-02-10 | 英飞凌科技股份有限公司 | Vias and methods of formation thereof |
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