JP2003163266A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device suppressing process increase such as patterning, reducing an inter-wiring capacity, superior in adhesion and mechanical strength with a dispersion barrier film covering a wiring material and superior in manufacture of an insulating film, and to provide the semiconductor device. <P>SOLUTION: The manufacturing method of the semiconductor device and the semiconductor device have a process for forming a wiring groove 13 on a first insulating film 12 on a substrate 11, a process for forming a side wall layer 14 on a side wall of the wiring groove 13, a process for burying a conductive material in the inside of the wiring groove 13 forming the side wall layer 14 to form wiring 17, and a process for providing a space (a) with a constant width (w) between the side wall of the wiring groove 13 and the wiring 17 by selectively removing the side wall layer 14. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a step of forming a wiring by filling a wiring groove formed in an insulating film with a conductive material. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with the increasing demand for miniaturization and high speed of semiconductor devices, miniaturization and multi-layering of wiring have been accelerated. In a semiconductor device having such a multilayer wiring process, wiring delay is a factor of signal delay of the semiconductor device. In order to improve such wiring delay, it is important to reduce wiring resistance and wiring capacitance. At present, regarding the reduction of wiring resistance, it has a lower resistance than aluminum alloy wiring that has been used conventionally,
Copper wiring technology, which has excellent electromigration resistance, has been drawing attention and is being studied for practical use.

As a technique for processing a copper wiring, a so-called trench wiring method such as a single damascene method or a dual damascene method is regarded as promising because dry etching of copper is generally not easy. The grooved wiring is formed by forming a predetermined groove in an insulating film such as silicon oxide in advance, burying the wiring material in the groove, and thereafter, surplus wiring material outside the groove is chemically mechanically polished (hereinafter referred to as CMP). , CMP is Chem
It is a wiring formed by removing it by the abbreviation of "Chemical Mechanical Polishing". As a method of embedding a wiring material in the groove, a method of performing reflow after forming a film by sputtering, an electrolytic plating method, and the like are being studied. In such a copper wiring, in order to prevent the diffusion of copper into the insulating film, the wiring is covered with a diffusion barrier film such as silicon nitride or tantalum nitride (TaN).

[0004]

However, since the diffusion barrier film covering the copper wiring as described above generally has a relatively high relative dielectric constant, it has been a factor of increasing the capacitance between wirings. Further, silicon oxide having a relatively high relative dielectric constant is used for the interlayer insulating film, which increases the capacitance between wirings. Therefore, in order to reduce the capacitance between wires,
The use of a low dielectric constant insulating film as an interlayer insulating film is being studied.

However, in order to reduce the capacitance between wirings,
When a low-dielectric-constant insulating film is used for the interlayer insulating film, it is used as a mask when peeling the diffusion barrier film or forming a groove due to a decrease in adhesion with the diffusion barrier film that covers the wiring material, compared to a silicon oxide film. Side etching of the interlayer insulating film when ashing the existing resist, deterioration of the side wall shape of the groove after etching (bowing shape, etc.), CM
There is a problem of insufficient mechanical strength against stress such as P.

Further, in-air wiring may be considered in order to reduce the capacitance between wirings, but there is a problem of insufficient mechanical strength.
Therefore, there is an example of an aerial wiring in which a pillar is formed of an insulating film in order to compensate for the lack of strength, but there is a problem that it leads to an increase in steps such as patterning for forming the pillar.

Therefore, it is possible to suppress an increase in the number of steps such as patterning, reduce the inter-wiring capacitance, and also have excellent adhesion and mechanical strength with the diffusion barrier film that covers the wiring material.
A semiconductor device manufacturing method and a semiconductor device having excellent workability of an insulating film have been desired.

[0008]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to claim 1 of the present invention comprises a step of forming a wiring groove in an insulating film on a substrate. A step of forming a side wall layer on the side wall of the wiring groove, a step of forming a wiring by burying a conductive material inside the wiring groove in which the side wall layer is formed, and selectively removing the side wall layer Then, a step of providing a space of a constant width between the side wall of the wiring groove and the wiring.

According to such a method of manufacturing a semiconductor device, the sidewall of the wiring groove formed in the insulating film is covered with the sidewall layer, the wiring is formed, and then the sidewall layer is removed. A space having a constant width corresponding to the side wall width is provided in a self-aligned manner with the side wall of the wiring groove. As a result, the substantial relative permittivity of the insulating film can be reduced and the inter-wiring capacitance can be reduced without increasing the number of steps such as patterning. Therefore, since the inter-wiring capacitance can be reduced without using a low dielectric constant insulating film as the insulating film, various problems that occur when the low dielectric constant insulating film is used can be avoided, and It is possible to obtain a semiconductor device having excellent adhesiveness and workability of the insulating film, and having sufficient mechanical strength against stress such as CMP in the manufacturing process.

According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, which includes a step of forming a wiring groove and a connection hole communicating with the bottom of the wiring groove in an insulating film on a substrate, the wiring groove, and A step of forming a sidewall layer on the side wall of the connection hole, a step of burying a conductive material inside the wiring groove and the connection hole, forming a wiring inside the wiring groove and forming a via inside the connection hole, By selectively removing the sidewall layer, a space having a constant width is provided between the sidewall of the wiring groove and the wiring, and a space is provided between the sidewall of the connection hole and the via. There is.

According to the method of manufacturing a semiconductor device as described above, not only the wiring groove but also a space can be provided between the sidewall of the connection hole and the via. Therefore, a comparison with the manufacturing method according to claim 1 is made. As a result, the relative dielectric constant of the insulating film can be further lowered, and the inter-wiring capacitance can be reduced.

Further, a semiconductor device according to a third aspect of the present invention includes an insulating film formed on a substrate, a wiring groove formed in the insulating film, and a wiring formed inside the wiring groove. In the semiconductor device provided, the wiring is provided with a space having a constant width with respect to the side wall of the wiring groove.

According to the semiconductor device having such a structure, since the wiring is provided with a space having a constant width with respect to the sidewall of the wiring groove, the substantial relative permittivity of the insulating film is lowered. Therefore, the capacitance between wirings can be reduced.
Further, since the space is provided with a constant width, it is possible to make the capacitance between wirings uniform in the same layer when the wirings are evenly provided.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In each embodiment, the configuration of the semiconductor device will be described in the order of manufacturing steps. (First embodiment)

An example of an embodiment relating to a method of manufacturing a semiconductor device of the present invention will be described with reference to manufacturing process sectional views of FIGS. First, as shown in FIG. 1A, a plasma CVD (Ch
The first insulating film 12 made of silicon oxide is formed by the emical vapor deposition method. As an example of film forming conditions, silane (SiH ₄ ) [flow rate: 1
00 cm ³ / min] and nitrous oxide (N ₂ O) [flow rate: 1
800 cm ³ / min] and nitrogen (N ₂ ) [Flow rate: 1000
cm ³ / min] and the RF (Radio F
requency) power of 400 W, film forming atmosphere pressure of 670
Pa, substrate heating temperature 380 ° C., film thickness 500 nm
Set to. The gas flow rate indicates the volumetric flow rate in the standard state.

Next, the first insulating film 12 is removed by reactive etching using a resist pattern (not shown) as a mask, and a wiring groove 13 is formed in the first insulating film 12. As an example of the reactive etching conditions, cyclobutane octafluoride (C ₄ F ₈ ) [flow rate: 9 cm is used as an etching gas.
³ / min] and carbon monoxide (CO) [flow rate: 50 cm ³ /
min] and Argon (Ar) [Flow rate: 200 cm ³ / m
in] and oxygen (O ₂ ) [flow rate: 5 cm ³ / min], RF power is set to 1760 W and etching atmosphere pressure is set to 4.8 Pa.

Here, the depth of the wiring groove 13 is, for example, 3
It should be 50 nm. In the drawings, the cross section of the wiring groove 13 in the short side direction is shown. In addition, the opening width of the wiring groove 13 in the short side direction is a constant width (100 on one side 100 mm) from the desired width of the wiring formed inside the wiring groove 13.
Widely formed (about nm).

Then, after removing the resist pattern,
As shown in FIG. 1B, the wiring groove 1 is formed by the CVD method.
In a state of covering the inner wall of No. 3, the side wall layer 14 made of, for example, amorphous carbon fluorine is applied to the first insulating film 1.
A film is formed on 2. As an example of the film forming conditions, tetrafluoromethane (CF ₄ ) [flow rate: 25 cm ³ /
min] and methane (CH ₄ ) [Flow rate: 40 cm ³ / mi
n] and hydrogen (H ₂ ) [flow rate: 130 cm ³ / min] and Ar
[Flow rate: 50 cm ³ / min], the RF power of the CVD device is 2500 W, and the pressure in the film forming atmosphere is 0.1 P.
a, the film thickness is set to 150 nm.

Here, the film thickness of the portion of the side wall layer 14 that covers the side wall of the wiring groove 13 is 100 n.
In order to obtain m, the film thickness was set to 150 nm as a film forming condition for coverage of 75%. However, the film thickness is set to correspond to the coverage so that a desired film thickness can be obtained on the sidewall of the wiring groove 13. Set. In addition, the sidewall layer 14
Since the opening width of the wiring groove 13 after the formation of the wiring becomes the wiring width of the wiring formed in a later process, the film thickness of the sidewall layer 14 is optimized so that the desired wiring width is maintained. .

The film-forming method here is C with good coverage.
The VD method is preferred. As the sidewall layer 14,
Although amorphous carbon is used in the present embodiment, it is not limited to this, and it may be formed of a material having excellent coverage and capable of etching the first insulating film 12 at a selection ratio of at least 3 or more. When the first insulating film 12 is made of silicon oxide, amorphous carbon, amorphous carbon hydrogen, carbon, or silicon nitride may be used.

Then, as shown in FIG. 1C, the side wall layer 14 is etched back by reactive etching so that the side wall layer 14 remains only on the side wall of the wiring groove 13. As an example of the reactive etching conditions, the etching gas is O ₂ [flow rate: 60 cm ³ / min].
Using, the RF power is set to 500 W, the etching atmosphere pressure is set to 20 Pa, and the substrate heating temperature is set to 220 ° C.

Next, as shown in FIG. 1 (4), the diffusion barrier film 15 is covered with the first insulating film by magnetron sputtering in a state of covering the inner wall of the wiring groove 13 whose side wall is covered with the side wall layer 14. A film is formed on the film 12. As the diffusion barrier film 15, one having an effect of preventing diffusion of a metal used as a wiring material is used. In the present embodiment, copper is used as the wiring material, and TaN having a copper diffusion preventing effect is formed. As an example of film forming conditions, Ar is used as a process gas.
[Flow rate: 100 cm ³ / min], the DC power of the magnetron sputtering device was 5 kW, the film forming atmosphere pressure was 0.4 Pa, the substrate heating temperature was 350 ° C., and the film thickness was 50
Set to nm. As the diffusion barrier film 15 here, titanium nitride, titanium oxynitride, titanium silicon nitride,
Tantalum, tantalum oxynitride, tantalum silicon nitride, tungsten nitride, tungsten nitride silicon, tungsten oxynitride, or the like may be used. The film forming method may use the CVD method.

Following the formation of the diffusion barrier film 15,
A plating seed layer (not shown) serving as a base metal for electrolytic plating is formed on the surface of the diffusion barrier layer 15 here by magnetron sputtering. As an example of the film forming conditions, Ar is used as a process gas [flow rate: 100
cm ³ / min], the DC power of the magnetron sputtering apparatus is 10 kW, the pressure in the film forming atmosphere is 0.3 Pa,
The substrate heating temperature is set to 400 ° C. and the film thickness is set to 150 nm.

Next, a metal film 16 made of, for example, copper is deposited on the surface of the diffusion barrier film 15 by an electrolytic plating method, and the wiring groove 1 whose side wall is covered with the sidewall layer 14 is formed.
3, the metal film 16 is embedded in a state in which the diffusion barrier film 15 is interposed. As an example of the electroplating conditions, a sulfuric acid bath is used as a plating solution, and an applied current having a current density of 10 mA / cm ² is applied to deposit 700 nm of copper.
The metal film 16 is formed by electroless plating, MOCVD (Metal).
It may be deposited by an organic CVD) method or a sputtering method, and may be subjected to a high temperature reflow treatment in order to improve the embedding property. In these cases, it is not necessary to form the plating seed layer as described above.

After that, as shown in FIG. 2A, the extra metal film (16) (including the plating seed layer) and the diffusion barrier layer 15 on the first insulating film 12 are polished by a normal CMP method. And then planarized. The slurry used for polishing at this time is an aluminum oxide type, and the slurry and H ₂ O ₂ are mixed and used at a ratio of 3: 1. This flattening process is performed until at least the upper portion of the sidewall layer 14 is polished. Then, a wiring 17 made of a metal film (16) (including a plating seed layer (not shown)) is provided inside the wiring groove 13 via a diffusion barrier layer 15.
To form.

Next, as shown in FIG. 2B, the magneto
By the long sputtering method, the
Then, TaN is applied to the first insulating film 12 so as to cover the wiring 17.
A film is formed on top. As an example of film formation conditions, process gas
Ar [gas flow rate: 100 cm ³/ Min]
DC power of Netron sputtering equipment is 5kW, film forming atmosphere
Internal pressure 0.4Pa, substrate heating temperature 350 ° C, film formation
Set the thickness to 50 nm. The antioxidant film 18 is made of copper.
Has anti-oxidant effect and anti-diffusion effect, and is suitable for etching
Select a film that can be more patterned. This embodiment
Then, TaN was used, but it is not limited to this.
Titanium nitride, titanium oxynitride, titanium silicon nitride,
Tantalum, tantalum oxynitride, tantalum silicon nitride, nitrogen
Tungsten oxide, silicon nitride silicon, oxynitride
Using tungsten, silicon nitride, silicon oxynitride, etc.
Good. Further, a CVD method may be used as the film forming method.

Next, the antioxidant film 18 other than on the wiring 17 is removed by reactive etching using a resist pattern (not shown) as a mask so that the antioxidant film 18 remains only on the wiring 17. Then, the resist pattern is removed by ashing. Here, the anti-oxidation film 18 formed on the entire surface of the first insulating film 12 so as to cover the wiring 17 is patterned so that the anti-oxidation film 18 is left only on the wiring 17. However, on the surface of the wiring 17, a film that forms the oxidation preventing film 18 in a self-aligned manner is formed on the entire surface of the first insulating film 12, and after the oxidation preventing film 18 is formed on the surface of the wiring 17, this film is formed. By removing
The antioxidant film 18 may be formed only on the wiring 17. In this case, it is not necessary to pattern the antioxidant film 18.

Next, as shown in FIG. 2C, the sidewall layer (14) is selectively removed by reactive etching. As an example of the reactive etching conditions, O ₂ [flow rate: 3000 cm ³ / min] is used as an etching gas, RF power is 2500 W, etching atmosphere pressure is 200 Pa, and substrate heating temperature is 220 ° C. As a result, a constant width w (here, 100 n is provided between the sidewall of the wiring groove 13 and the wiring 17 covered with the diffusion barrier film 15).
The space a of m) is provided.

Here, FIG. 3 is a sectional view taken along the line AA 'in the state of FIG. As shown in this figure, inside the wiring groove 13 formed in the first insulating film 12, the wiring 17 covered with the diffusion barrier film 15 has a space of a constant width w with respect to the sidewall of the wiring groove 13. a is provided. The space a is provided not only in the long side direction but also in the short side direction over the entire circumference of the wiring groove 13.

Then, again, as shown in FIG.
This space a, which is characteristic of the present invention, can reduce the substantial relative dielectric constant of the first insulating film 12, so that the space a
It is preferable to form the width w of the same as wide. However, since the width w of the space a is determined by the opening width of the wiring groove 13 with respect to the width of the wiring 17, if the width w of the space a is too wide in the portion where the wiring 17 is densely arranged, the space between the wirings 17 is increased. The width of the first insulating film 12 in the
Patterning at the time of forming the wiring groove 13 in 2 becomes difficult. Further, it becomes difficult to form the upper layer of the first insulating film 12 while maintaining the width w and the height of the space a, and the mechanical strength of the obtained semiconductor device also decreases. Therefore, the width w of the space a, that is, the opening width of the wiring groove 13 with respect to the width of the wiring 17 is adjusted within a range where such a problem does not occur.

Although the sidewall layer (14) is removed by dry etching here, it may be removed by wet etching, and the removing method is appropriately selected depending on the material of the sidewall layer (14). And Further, when the sidewall layer (14) is formed of a material that can be removed by etching together with the resist used for patterning the antioxidant film 18 in the previous step, the sidewall layer (14) and the anti-oxidation agent can be used together. It is also possible to simplify the manufacturing process by removing the resist pattern after processing the film 18.

Next, as shown in FIG. 2 (4), an intermediate insulating film 19 functioning as an etching stopper, for example, silicon nitride, is covered with the first insulating film 12 by the CVD method while covering the antioxidant film 18. A film is formed on top. Here, the intermediate insulating film 19 is formed on the sidewall of the wiring groove 13 and the diffusion barrier film 15.
The width w of the space a provided between the wiring 17 and the wiring 17
A film is formed on the first insulating film 12 in a state where the height is maintained. Therefore, the coverage at the time of film formation is reduced, and the intermediate insulating film 19 is formed so as to bridge over the antioxidant film 18 on the wiring 17 and the first insulating film 12.

An example of the film forming conditions for the intermediate insulating film 19 is that the process gas contains N ₂ [flow rate: 4000 cm ³
/ Min] and SiH ₄ [flow rate: 80 cm ³ / min] and ammonia (NH ₃ ) [flow rate: 15 cm ³ / min], RF power of the CVD apparatus is 850 W, film formation atmosphere pressure is 570 Pa, and substrate heating temperature is Is set to 350 ° C. and the film thickness is set to 50 nm. The intermediate insulating film 19 also has an effect of preventing diffusion of copper from the wiring 17. Also,
When the relative dielectric constant of the intermediate insulating film 19 is high, the pass may be cut by patterning in order to prevent the pass from having a high capacitance. The intermediate insulating film 19 is not limited to silicon nitride, and may be any film that prevents diffusion of copper and serves as an etching stopper when forming a connection hole in a later step. Specifically, it may be made of silicon carbide, silicon oxycarbide, silicon oxynitride, silicon oxide, or the like. Further, the intermediate insulating film 19 may be formed by a magnetron sputtering method.

Then, as shown in FIG. 4A, a second insulating film 20 is formed on the intermediate insulating film 19. The second insulating film 20 is made of, for example, silicon oxide, and is formed as shown in FIG.
A film having a thickness of 600 nm is formed under the same film forming conditions as those for the first insulating film 12 described using.

Next, the second insulating film 2 is formed by the CVD method.
An intermediate insulating film 21 made of, for example, silicon nitride is formed to a thickness of 50 nm on 0. The intermediate insulating film 19 described with reference to FIG. 2D is formed under the same film forming conditions.

Subsequently, the third insulating film 22 is replaced with the intermediate insulating film 2.
Form on 1. The third insulating film 22 is made of, for example, silicon oxide, and is formed to a thickness of 400 nm under the same film forming conditions as the first insulating film 12 described with reference to FIG.

Then, as shown in FIG. 4B, a wiring groove 24 is formed in the third insulating film 22 by reactive etching using a resist pattern (not shown) as a mask, and then the connection hole 23 is formed. The intermediate insulating film 21 and the second insulating film 20 are sequentially removed by etching by using a resist pattern (not shown) for forming the mask as a mask to communicate with the bottom of the wiring groove 24. The connection hole 23 is formed in the second insulating film 20. At this time, the intermediate insulating film 19 functions as an etching stopper. Here, the opening widths of the wiring groove 24 and the connection hole 23 are equal to each other.
The wiring formed inside 4 and the via formed inside the connection hole 23 are formed to have a certain width (about 100 nm on each side) wider than a desired width.

Here, the intermediate insulating film 21 and the third insulating film 22 are formed on the second insulating film 20, the wiring groove 24 is formed in the third insulating film 22, and then the second insulating film 22 is formed. A connection hole 23 was formed in the film 20. However, the method is not limited to this method, and a mask used when the intermediate insulating film 21 is formed on the second insulating film 20 and then the intermediate insulating film 21 is formed with the connection hole 23 in the second insulating film 20. So that the third insulating film 22 is formed on the second insulating film 20.
And the second insulating film 20 is removed together with the third insulating film 22 by performing reactive etching using the resist pattern for forming the wiring groove 24 as a mask. The connection hole 23 may be formed.

Subsequently, as shown in FIG. 4C, the sidewall layer 28 is formed so as to cover the inner walls of the wiring groove 24 and the connection hole 23. The sidewall layer 28 is made of, for example, amorphous carbon fluorine, and is formed as shown in FIG.
Under the same film forming conditions as the side wall layer (14) described with reference to, the film is formed to have a film thickness of 100 nm on the side walls of the wiring groove 24 and the connection hole 23. And
By reactive etching, the sidewall layer 28 is etched back and removed so that the sidewall layer 28 covers the sidewalls of the wiring trench 24 and the connection hole 23.

Then, the intermediate insulating film 19 at the bottom of the connection hole 23 is removed by reactive etching using a resist pattern (not shown) as a mask. Here, as an example of the reactive etching conditions, Ar [flow rate: 100 cm ³ / min] and O ₂ [flow rate: 20 cm ³ /
min] and trifluoromethane (CHF ₃ ) [flow rate: 20 c
m ³ / min], the RF power is set to 520 W and the etching atmosphere pressure is set to 5.7 Pa.

Then, as shown in FIG. 5A, a diffusion barrier film 29 and a plating seed layer (not shown) are formed in the wiring groove 24 and the connection hole 23 where the sidewall layer 28 is formed by magnetron sputtering. Form a film. Here, for example, the diffusion barrier film 29 is made of TaN and the plating seed layer is made of copper, and the diffusion barrier film 1 described with reference to FIG.
5 and the plating seed layer are formed under the same film forming conditions. After that, for example, on the above surface by an electrolytic plating method,
A metal film (not shown) made of copper is deposited to form a wiring groove 24 and a connection hole 23 whose sidewalls are covered with a sidewall layer 28.
Then, a metal film is embedded with the diffusion barrier film 29 interposed therebetween, and the excess metal film is removed by the CMP method to be planarized. In this way, the wiring 27 and the via 26 made of a metal film are formed in the wiring groove 24 and the connection hole 23, respectively.
The electrolytic plating conditions and CMP conditions here are as shown in FIG.
It is assumed that the wiring 17 is formed under the same conditions as described in (4) and FIG.

Next, as shown in FIG. 5B, an anti-oxidation film 30 is formed on the wiring 27. The antioxidant film 30 is made of, for example, TaN, and is formed under the same film formation conditions as the antioxidant film 18 described with reference to FIG. After that, the wiring 2 is formed by reactive etching using the resist pattern as a mask in the same manner as the oxidation preventive film 18.
The anti-oxidation film 30 other than on 7 is removed. Then, the sidewall layer 28 is selectively removed by reactive etching. As a result, a constant width (here, 100) is provided between the sidewalls of the wiring groove 24 and the connection hole 23 and the wiring 27 and the via 26 covered with the diffusion barrier film 29.
nm) spaces b and c are provided.

When the wiring groove 24 and the connection hole 23 are formed to have a step, the side wall layer 28 formed on the side wall of the connection hole 23 covers the upper portion with the diffusion barrier film 29. As a result, the structure cannot be removed by etching. In such a case, the relative dielectric constant of the sidewall layer 28 is relatively low so that the inter-wiring capacitance does not increase even if the sidewall layer 28 remains, and adverse effects such as degassing occur due to heat treatment or the like. Select a material that does not exist.

Subsequently, as shown in FIG. 6, the antioxidant film 3 is formed.
In the state where the wiring 27 covered with 0 is covered, the third insulating film 2
An intermediate insulating film 31 is formed on the surface 2. The intermediate insulating film 31 is
For example, it is made of silicon nitride and is formed under the same film forming conditions as the intermediate insulating film 19 described with reference to FIG. Further, in the case of forming an upper layer copper wiring, the above process (from the step of forming the second insulating film 20) is repeated.

In such a semiconductor device manufacturing method, in order to prevent the transistor characteristics from being affected, it is preferable that the substrate heating temperature during film formation or etching during the process is low, and in particular, the metal film 16 is preferable. When copper is used as the material, the temperature during the process is preferably 400 ° C. or lower in order to prevent copper diffusion and disconnection due to stress migration.

According to the method of manufacturing a semiconductor device as described above, the sidewall of the wiring groove 13 formed in the first insulating film 12 is covered with the sidewall layer 14, and the wiring 17 is formed via the diffusion barrier film 15. After the formation, the sidewall layer 14 is removed. As a result, a constant width w (here, 100 nm) corresponding to the film thickness of the sidewall layer 14 is provided between the sidewall of the wiring groove 13 and the wiring 17 formed therein and covered with the diffusion barrier film 15. Is provided in a self-aligned manner. This space a is formed over the entire circumference of the wiring 17.

In such a manufacturing method and the semiconductor device obtained thereby, a space a having a constant width w is provided between the side wall of the wiring groove 13 and the wiring 17 without increasing the number of steps such as patterning. Because it is possible,
Even if the insulating film 12 is formed of silicon oxide having a relatively high relative permittivity, the substantial relative permittivity of the first insulating film 12 can be reduced, and the inter-wiring capacitance can be reduced. . Furthermore, in the present embodiment, since silicon oxide is used for the first insulating film 12, the adhesion with the diffusion barrier film 15 that covers the wiring material and the workability of the first insulating film 12 are excellent. , CM in the manufacturing process
It is possible to obtain a semiconductor device having sufficient mechanical strength against stress such as P.

Since the space a having a constant width w is provided between the side wall of the wiring groove 13 and the wiring 17 in a self-aligned manner, the wiring 17 is sparsely and densely arranged on the first insulating film 12. In such a case, the first insulating film 12 is formed widely between the sparse portions of the wiring 17.
Since it contributes as a pillar between wiring layers, mechanical strength can be maintained without increasing the patterning process. When the wirings 17 in the same layer are uniformly arranged, it is possible to make the inter-wiring capacitance uniform and prevent the inter-wiring capacitance from becoming uneven.

Further, in this embodiment, the space c can be provided between the side wall of the connection hole 23 formed in the second insulating film 20 and the via 26 formed therein, The relative permittivity of the second insulating film 20 can be reduced, and the inter-wiring capacitance can be further reduced. Here, the operation of the first embodiment is the same as that of the wiring groove 13 and the wiring 1 formed in the first insulating film 12.
7 has been described as an example, the same effect can be obtained also in the wiring groove 24 and the wiring 27 formed in the third insulating film 22.

Here, in the semiconductor device, two-thirds of the wirings have the structure (air gap structure) in which a space having a constant width is provided between the side wall of the wiring groove and the wiring as described above, and insulation is performed. A simulation of the inter-wiring capacitance when silicon oxide with a relative dielectric constant of about 4.1 was used showed that the relative dielectric constant of this space was about 1.
The substantial relative permittivity of the insulating film was 1.4, which was confirmed to be significantly lower than that of silicon oxide.

As described above, in the first embodiment, an example in which silicon oxide having a relatively high relative dielectric constant is used for the insulating film has been described. However, as the insulating film, TEOS (tet
raethoxy silane) oxide film, silicon oxyfluoride film, CVD
Oxycarbide film, organic SOG (slip on glass)
If a low dielectric constant insulating film such as s) film is used, the relative dielectric constant of the insulating film can be further reduced, and the inter-wiring capacitance can be reduced.

(Second Embodiment) FIG. 7 shows a sectional view of a semiconductor device according to a second embodiment of the present invention. In the first embodiment, the wiring groove 24 formed in the third insulating film 22.
The wiring 27 and the via 26 are formed by embedding a metal film in the same step in the connection hole 23 communicating with the bottom of the wiring groove 24. However, in the second embodiment, the wiring 27 and the via 26 are formed. A method of forming in another step will be described. However, the steps up to the formation of the second insulating film 20 on the intermediate insulating film 19 are performed by the same method as in the first embodiment, and will be omitted. The film forming conditions and the like in the subsequent steps are the same as those in the first embodiment, and therefore will be omitted.

First, the second insulating film 20 and the intermediate insulating film 19 are removed by reactive etching using a resist pattern (not shown), and a connection hole reaching the wiring 17 covered with the antioxidant film 18 is formed. 23 is formed. Next, a diffusion barrier film 32 and a plating seed layer (not shown) are sequentially formed in a state of covering the inside of the connection hole 23, and a metal film made of copper is deposited on the surface by, for example, an electrolytic plating method. The contact hole 23 with copper and a metal film (not shown).
Is formed, and the excess metal film is removed by CMP to planarize. In this way, the via 26 is formed. Here, although the space c provided in the first embodiment is not provided between the sidewall of the connection hole 23 and the via 26, the space c may be formed. However, when the manufacturing process is simplified, the space c does not have to be formed.

After that, the intermediate insulating film 21 is deposited on the second insulating film 20 so as to cover the vias 26, and the third insulating film 22 is formed thereon. Then, the third upper layer of the via 26
A wiring groove 24 is formed in the insulating film 22 and the inside of the wiring groove 24 is covered with a sidewall layer 33, and only the side wall of the wiring groove 24 is covered with a sidewall layer (not shown). The part is etched back and removed.

Next, the intermediate insulating film 21 on the bottom of the wiring groove 24.
Is also removed by etching, and a diffusion barrier film 33 is formed inside the wiring groove 24 whose side wall is covered with the side wall layer 28. Since the diffusion barrier film 33 also functions as an antioxidant film for the via 26, it is not necessary to form an antioxidant film on the via 26. Subsequent steps are the same as the formation of the wiring 17 described with reference to FIG. 1D in the first embodiment, and will be omitted.

In the semiconductor device obtained by the manufacturing method as described above, the wiring 17 is provided between the sidewall of the wiring groove 13 and the wiring 17 formed therein, as in the first embodiment.
Since a space a having a constant width (here, 100 nm) corresponding to the film thickness of the sidewall layer (14) is provided in a self-aligned manner over the entire circumference of, the capacitance between wirings in the same layer as in the first embodiment is different. Has the same effect.

[0057]

As described above, according to the first aspect of the present invention.
According to the method of manufacturing a semiconductor device described above, a space having a constant width can be provided in a self-aligned manner between the sidewall of the wiring groove and the wiring. With such a method, it is possible to provide a space of a certain width in the insulating film without increasing the number of steps such as patterning, which lowers the relative dielectric constant of the insulating film and reduces the inter-wiring capacitance. can do. This allows
Since the inter-wiring capacitance can be reduced without using a low-dielectric-constant insulating film, various problems that occur when a low-dielectric-constant insulating film is used can be avoided, and silicon oxide having a high relative dielectric constant can be used as the insulating film. It is possible to obtain a semiconductor device having excellent mechanical strength as well as excellent adhesion to the diffusion barrier film and workability of the insulating film by using the above materials.

Further, according to the method of manufacturing a semiconductor device according to the second aspect of the present invention, not only the wiring groove but also a space can be provided between the sidewall of the connection hole and the via, so that the insulating film is substantially formed. It is possible to further reduce the relative dielectric constant and further reduce the inter-wiring capacitance.

According to the semiconductor device of the third aspect of the present invention, since the space having a constant width is provided between the side wall of the wiring groove and the wiring, the first insulating film has a relatively high dielectric constant. Even when a film made of a high-quality material is used, the inter-wiring capacitance can be reduced. Therefore, the wiring delay can be suppressed and the device speed can be increased. Further, since the space is provided with a constant width, it is possible to make the capacitance between wirings uniform in the same layer when the wirings are evenly provided.

[Brief description of drawings]

FIG. 1 is a manufacturing process sectional view (1) for explaining a method for manufacturing a semiconductor device according to a first embodiment;

FIG. 2 is a manufacturing process sectional view (2) for explaining the method for manufacturing the semiconductor device according to the first embodiment;

FIG. 3 is a sectional view in a step of the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a manufacturing process sectional view (3) for explaining the method for manufacturing the semiconductor device according to the first embodiment;

FIG. 5 is a manufacturing process sectional view (4) for explaining the method for manufacturing the semiconductor device according to the first embodiment;

FIG. 6 is a manufacturing step cross-sectional view (No. 5) for explaining the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a modified example of the present invention.

[Explanation of symbols]

11 ... Substrate, 12 ... First insulating film, 13, 24 ... Wiring trench, 14, 28 ... Sidewall layer, 17, 27 ... Wiring, 20 ... Second insulating film, 22 ... Third insulating film, 23 …
Connection hole, 26 ... via

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH11 HH27 HH28 HH30 HH32                       HH33 HH34 HH35 JJ01 JJ11                       JJ27 JJ28 JJ30 JJ32 JJ33                       JJ34 JJ35 KK11 KK27 KK28                       KK30 KK32 KK33 KK34 KK35                       MM01 MM02 MM05 MM12 MM13                       NN06 NN07 PP06 PP11 PP15                       PP27 PP28 PP33 QQ08 QQ09                       QQ10 QQ13 QQ19 QQ25 QQ31                       QQ37 QQ48 QQ73 QQ75 RR01                       RR02 RR04 RR06 RR08 RR11                       RR30 SS02 SS08 SS11 TT02                       TT08 XX01 XX03 XX06 XX20                       XX25 XX27 XX28

Claims (4)

[Claims] 1. A step of forming a wiring groove in an insulating film on a substrate, a step of forming a sidewall layer on a side wall of the wiring groove, and a step of forming conductivity inside the wiring groove in which the sidewall layer is formed. And a step of forming a wiring by embedding a material, and a step of selectively removing the sidewall layer to provide a space of a constant width between the sidewall of the wiring groove and the wiring. Of manufacturing a semiconductor device. 2. A step of forming a wiring groove and a connection hole communicating with the bottom of the wiring groove in an insulating film on a substrate, and a step of forming a sidewall layer on the side wall of the wiring groove and the connection hole. A step of burying a conductive material inside the wiring groove and the connection hole in which the sidewall layer is formed, forming a wiring inside the wiring groove, and forming a via inside the connection hole; By selectively removing the sidewall layer, a space having a constant width is provided between the sidewall of the wiring groove and the wiring, and a space is provided between the sidewall of the connection hole and the via. A method of manufacturing a semiconductor device, comprising: 3. A semiconductor device comprising an insulating film formed on a substrate, a wiring groove formed in the insulating film, and a wiring formed inside the wiring groove, wherein the wiring is the wiring groove. A semiconductor device provided with a space having a constant width with respect to a side wall of the semiconductor device. 4. The semiconductor device according to claim 3, further comprising a connection hole communicating with a bottom portion of the wiring groove and a via formed inside the connection hole, wherein a sidewall of the connection hole and the via. A semiconductor device characterized in that a space is provided between the semiconductor device and the semiconductor device.