JP2008172056A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To take a countermeasure against the inhibition of hydrogen treatment without increasing a hydrogen supplier for exclusive use and the number of processes. <P>SOLUTION: A semiconductor device (solid imaging device 10) in which wiring layers 29, 34 to connect circuits on a substrate 11 are formed by lamination on the substrate 11 is composed so that the wring layers 29, 34 have laminated structures (29a-29d) of main wiring metal and high melting point metal or high melting metal compound, and that the surface of the wiring layers 29, 34 are covered by insulating films 30, 35 composed of SiO<SB>2</SB>or SiN or SiON formed by a chemical vapor deposition method in which monosilane gas is used as the main reaction gas. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, in particular, a solid-state imaging device used as an image input device and a manufacturing method thereof.

  Semiconductor devices are being improved in performance and miniaturization of various devices. And in the manufacturing method, in order to achieve both speeding up and miniaturization of the wiring process, the wiring structure to be multilayered and the insulating film forming method are improved.

  Among such semiconductor devices, solid-state imaging devices such as CCD (Charge Coupled Device) image sensors and non-CCD CMOS (Complementary Metal Oxide Semiconductor) image sensors used as image input devices are improved in performance. For this purpose, the S / N ratio is improved by increasing the light collection efficiency and photoelectric effect efficiency of each pixel to improve the sensitivity, and keeping dark current, random noise, and fixed pattern noise low. It is necessary to make it.

  In particular, a CMOS image sensor is manufactured by diverting CMOS technology such as memory and logic, and therefore, a wiring structure using aluminum or copper as a wiring material is used.

  In multilayer wiring used in CMOS technology, when aluminum is used as a wiring material, it is important to control crystallinity in order to improve reliability such as electromigration resistance and stress migration resistance. For this reason, a structure in which a high melting point metal such as titanium (titanium) or titanium nitride and a compound film thereof are stacked is used.

  In addition, when copper is used as a wiring material, high melting point metals such as tantalum and tantalum nitride are used for the purpose of improving reliability as in the case of using aluminum and suppressing the diffusion of copper into the interlayer insulating layer. And the wiring is formed using together with the compound.

  On the other hand, it has been found that the dark current that greatly affects the sensitivity of the image sensor can be suppressed by reducing the interface state between silicon and silicon oxide. For that purpose, it is an effective technique to terminate dangling bonds at the interface with hydrogen, and heat treatment is performed in a hydrogen atmosphere during or at the end of the manufacturing process.

  However, since titanium and tantalum used in the multilayer wiring process of CMOS image sensors have a hydrogen storage capacity even in the state of a single substance and a compound, they impede hydrogenation treatment for the purpose of reducing interface states. End up. As a result, the dark current of the CMOS image sensor cannot be sufficiently reduced, causing image quality degradation.

  Prior art document information related to the semiconductor device and the manufacturing method of the present invention includes the following.

JP-A-1-245528 Japanese Patent Laid-Open No. 7-94692 JP 2003-204055 A

  In Patent Documents 1 and 2, as a countermeasure against hydrogenation treatment inhibition by titanium hydrogen occlusion used in the wiring of the solid-state imaging device, treatment is performed for 10 minutes or more in a hydrogen plasma atmosphere at 350 ° C. to 500 ° C. before performing the hydrogenation treatment. Thus, a method is described in which titanium is supersaturated with hydrogen. However, this method requires an increase in the number of steps for forming the multilayer wiring and a dedicated hydrogen plasma processing apparatus.

  Patent Document 3 describes a method using a tungsten nitride film without using titanium. However, in this method, the orientation control of aluminum as a wiring material, the stabilization of the interface contact resistance value with tungsten embedded in the connection hole formed in the insulating layer between the wiring layers, and the viewpoint of adhesion to the interlayer insulating layer Therefore, realization is difficult.

  The present invention has been made in view of conventional problems, and it is an object of the present invention to provide a dedicated hydrogen supply device and a semiconductor device capable of realizing a hydrogen treatment inhibition measure without increasing the number of processes and a method for manufacturing the same. To do.

In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device in which a wiring layer for connecting a circuit on a substrate is stacked on the substrate, and the wiring layer includes a main wiring metal and a refractory metal or a high melting point metal. The wiring layer has a laminated structure with a melting point metal compound, and the surface of the wiring layer is coated with an insulating film made of SiO _2, SiN, or SiON formed by chemical vapor deposition using monosilane gas as a main reaction gas.

In this semiconductor device, since the wiring layer is coated with an insulating film formed by a chemical vapor deposition method using monosilane gas (SiH ₄ ) as a main reaction gas, the hydrogen component contained in the monosilane gas is stored in the hydrogen. It can be occluded by a high melting point metal or a high melting point metal compound. Therefore, it is possible to prevent the hydrogenation of the substrate from being hindered when a hydrogenation process is performed in a later process for the purpose of reducing the interface order between silicon and silicon oxide.

  Specifically, this semiconductor device is a solid-state imaging device having a plurality of pixel portions and a control circuit portion as the circuit, and a wiring layer that connects the pixel portions and the control circuit portion.

  In this semiconductor device, the wiring layer preferably uses aluminum or copper as the main wiring metal and has a thickness of 100 nm to 1000 nm. In this way, it is possible to prevent the wiring resistance value from being too high to be used or making it difficult to perform microfabrication.

In the wiring layer, it is preferable that the refractory metal or the refractory metal compound contains titanium as a main component and has a thickness of 10 nm to 100 nm.
Alternatively, in the wiring layer, it is preferable that the refractory metal or the refractory metal compound is mainly composed of tantalum, and the film thickness thereof is 5 nm or more and 50 nm or less.

  Furthermore, the insulating film preferably has a thickness of 30 nm to 1000 nm. In this way, voids can be sufficiently suppressed.

The method for manufacturing a semiconductor device of the present invention includes an insulating layer forming step of forming an insulating layer on a substrate, a conductive path forming step of forming a connection hole having a conductive portion in the insulating layer, and the connection hole. A wiring layer forming step for forming a wiring layer having a laminated structure composed of a main wiring metal and a refractory metal or a refractory metal compound on the surface of the insulating layer, and a chemical using monosilane gas as a main reaction gas on the wiring layer And a film forming step of coating with an insulating film made of SiO _2, SiN, or SiON formed by a vapor deposition method.

In this manufacturing method, after the wiring layer forming step, a film forming step of coating the surface with an insulating film made of SiO _2, SiN, or SiON by a chemical vapor deposition method using monosilane gas as a main reaction gas is performed. A hydrogen component can be occluded in a refractory metal or a refractory metal compound having a hydrogen occlusion capacity constituting the wiring layer. Therefore, when the hydrogenation process is executed in a subsequent process, it is possible to reliably prevent inhibition of hydrogenation of the substrate. Moreover, in order to occlude the hydrogen component into the refractory metal or the refractory metal compound, a large dedicated device is unnecessary and the number of manufacturing steps is not increased.

  In this manufacturing method, the film forming step is preferably performed in a temperature atmosphere of 300 ° C. or higher and 400 ° C. or lower.

  In addition, after the film forming step, an insulating layer forming step of forming an insulating layer on the insulating film is further provided, and after the insulating layer forming step, a hydrogenation step of performing a heat treatment in a gas atmosphere containing hydrogen is further provided. It is preferable to have.

  In the manufacturing method of the present invention, the surface of the wiring layer is coated with an insulating film formed by a chemical vapor deposition method using monosilane gas as a main reaction gas. The melting point metal compound can occlude (contain) a hydrogen component. Therefore, hydrogenation inhibition for the purpose of reducing the substrate interface order can be reliably prevented. In addition, a large dedicated device is not required and the number of manufacturing steps does not increase. Further, since the manufactured semiconductor device can reduce dark current, the S / N ratio can be improved and the image quality can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a solid-state imaging device 10 which is a semiconductor device according to an embodiment of the present invention. The solid-state imaging device 10 includes a pixel unit 12 and a peripheral (control) circuit unit 18, and a MOS transistor included in the pixel unit 12 and a plurality of MOS transistors included in the peripheral circuit unit 18 are formed of a P-type silicon substrate. It is formed on the semiconductor substrate 11. In this embodiment, wiring layers 29 and 34 for connecting circuits are stacked on the semiconductor substrate 11.

  The pixel unit 12 includes a plurality of MOS transistors provided so as to form a two-dimensional matrix with respect to the semiconductor substrate 11. Specifically, the pixel unit 12 includes a P-type well diffusion layer 13 formed on the semiconductor substrate 11, an N-type first source diffusion layer 14 and a first drain diffusion formed on the well diffusion layer 13. A layer 15 and a first gate electrode 17 mounted via a first gate film 16 so as to be adjacent to the layer 15 are provided. The first source diffusion layer 14 serves as a photosensor that performs photoelectric conversion, and accumulates charges according to the amount of incident light. The first gate electrode 17 serves as a switch that moves charges accumulated in the first source diffusion layer 14 to the first drain diffusion layer 15.

  The peripheral circuit unit 18 includes a reset transistor, an amplification transistor, a MOS transistor constituting a selection transistor, and the like. The peripheral circuit portion 18 is mounted on an N-type second source diffusion layer 19 and second drain diffusion layer 20 formed on the semiconductor substrate 11 and a second gate film 21 so as to be adjacent thereto. 2 gate electrodes 22.

  An oxide insulating layer 23 (Shallow Trench Isolation) for separating the elements 14, 15, 19, and 20 is formed at the boundary between the pixel unit 12 and the peripheral circuit unit 18.

A first insulating film 24 made of silicon oxide (SiO ₂ ) is formed on the surface of the semiconductor substrate 11 so as to cover the gate electrodes 17 and 22, and a contact etching stopper film 25 made of silicon nitride (SiN) is formed on the surface. Is formed. A first interlayer insulating layer 26 made of silicon oxide (SiO ₂ ) is formed on the surface of the contact etching stopper film 25. The first interlayer insulating layer 26 may be formed of a SiO ₂ (BPSG) film containing boron (B) or phosphorus (P) or a SiO ₂ (PSG) film containing phosphorus (P).

  The first insulating film 24, the contact etching stopper film 25, and the first interlayer insulating layer 26 are formed from the surface of the first interlayer insulating layer 26 so as to be positioned on the second drain diffusion layer 20 and the second gate electrode 22. A first connection hole (contact hole) 27 penetrating through one insulating film 24 is provided. Inside the first connection hole 27, a first conductive portion (tungsten plug) 28 made of a titanium nitride film, a titanium laminated film, and a tungsten film is provided.

  The first interlayer insulating layer 26 is provided with a first wiring layer 29 so as to form a predetermined pattern shape in a plan view on the surface including the first conductive portion 28. The first wiring layer 29 is formed by coating the first laminated metal film 29a, the second laminated metal film 29b, the main wiring metal film 29c, and the third laminated metal film 29d in this order from the semiconductor substrate 11 side. .

  Of these, the main wiring metal film 29c is formed of aluminum (Al) or copper (Cu). Here, the film thickness in the case where the main wiring metal film 29c is made of aluminum is 100 nm or more, more preferably 150 nm or more and 1000 nm or less. Moreover, the film thickness in the case of comprising copper is 100 nm or more and 1000 nm or less. If the film thickness is less than 100 nm, the wiring resistance value is too high to be used, and if it exceeds 1000 nm, it is difficult to use from the viewpoint of fine processing.

  The lowermost first laminated metal film 29a is formed of refractory metal titanium (titanium) or tantalum. Here, the first laminated metal film 29a is important for controlling the orientation that determines the reliability of the wiring by the main wiring metal film 29c. Therefore, when titanium is used, it is formed with a film thickness of 10 nm or more, and when tantalum is used, it is formed with a film thickness of 5 nm or more.

  Further, the second laminated metal film 29b and the third laminated metal film 29d located on both surfaces of the main wiring metal film 29c are mainly composed of titanium nitride or titanium which is a high melting point metal compound. It is made of tantalum nitride. And when titanium is the main component, the film thickness is 10 nm or more and 100 nm or less. The film thickness when tantalum is the main component is 5 nm or more and 50 nm or less.

  Here, when aluminum is used as the main wiring metal film 29c and a refractory metal or a refractory metal compound mainly composed of titanium is used as the laminated metal films 29a, 29b, 29d, the orientation of the main wiring metal film 29c is controlled. The minimum film thickness is 10 nm, and the upper limit is 100 nm from the viewpoint of etching time. When copper is used as the main wiring metal film 29c and a refractory metal or a refractory metal compound mainly composed of tantalum is used as the laminated metal films 29a, 29b, and 29d, the minimum film thickness for preventing copper diffusion is 5 nm. This is because the upper limit is 50 nm from the viewpoint of chemical mechanical polishing (CMP). Of course, aluminum may be used as the main wiring metal film 29c, a refractory metal or a refractory metal compound mainly composed of tantalum may be used as the laminated metal films 29a, 29b, and 29d, and copper may be used as the main wiring metal film 29c. Alternatively, a refractory metal or a refractory metal compound mainly composed of titanium may be used as the laminated metal films 29a, 29b, and 29d.

  The surface of the first interlayer insulating layer 26 including the surface of the first wiring layer 29 is coated with a second insulating film 30 made of silicon oxide, and the surface of the second insulating film 30 is made of silicon oxide. A second interlayer insulating layer 31 is formed. In the second insulating film 30 and the second interlayer insulating layer 31, a second connection penetrating from the surface of the second interlayer insulating layer 31 to the second insulating film 30 so as to be located at a predetermined portion of the first wiring layer 29. A hole 32 is provided, and a second conductive portion 33 similar to the first conductive portion 28 is provided therein.

  Further, the second interlayer insulating layer 31 is provided with a second wiring layer 34 so as to form a predetermined pattern shape in a plan view on the surface including the second conductive portion 33. Similar to the first wiring layer 29, the second wiring layer 34 includes a first laminated metal film 34a, a second laminated metal film 34b, a main wiring metal film 34c, and a third laminated metal film 34d from the semiconductor substrate 11 side. It is constituted by coating in order.

  The surface of the second interlayer insulating layer 31 including the surface of the second wiring layer 34 is coated with a third insulating film 35 made of silicon oxide, and the surface of the third insulating film 35 is made of silicon oxide. A third interlayer insulating layer 36 is formed.

  Next, a method for manufacturing the solid-state imaging device 10 will be specifically described.

  First, as shown in FIG. 2A, a first film forming step of covering the entire surface of the semiconductor substrate 11 on which the pixel portion 12 and the peripheral circuit portion 18 are formed with a first insulating film 24 and a contact etching stopper film 25 is performed. Do.

  Next, a first insulating layer forming step for forming a first interlayer insulating layer 26 made of silicon oxide on the surface of the contact etching stopper film 25 is performed. The first insulating layer forming step is performed by a chemical vapor deposition (CVD) method using ethyl silicate (TEOS (tetraethyl orthosilicate)) as a main reaction gas.

Next, in order to electrically connect the first wiring layer 29 formed on the surface of the first interlayer insulating layer 26 to the second drain diffusion layer 20 and the second gate electrode 22 of the semiconductor substrate 11, A first connection hole 27 penetrating from the first interlayer insulating layer 26 to the first insulating film 24 is formed, and a first conductive path forming step of forming a first conductive portion 28 in the first connection hole 27 is performed. In the first conductive path forming step, first, the first connection hole 27 is formed by the photolithography technique and the dry etching technique so that the second drain diffusion layer 20 and the second gate electrode 22 are exposed. Next, after forming titanium nitride and a titanium laminated film in the formed first connection hole 27 by a sputtering method, tungsten is formed in the first connection hole 27 and the substrate surface by a CVD method containing tungsten hexafluoride gas as a main component. A film is formed. Thereafter, the first conductive portion 28 is formed by CMP. The titanium nitride and titanium laminated film may be formed by a CVD method using an organometallic compound as a source gas or a CVD method using titanium tetrachloride (TiCl ₄ ) as a source gas. In addition, the first conductive portion 28 may be formed by using an etch back method in which tungsten is left in the first connection hole 27 by a dry etching method using sulfur hexafluoride (SF ₆ ) gas.

  Next, a first wiring layer 29 is formed on the first interlayer insulating layer 26 including the first connection hole 27 so as to be electrically connected to the first connection hole 27 in which the first conductive portion 28 is formed. One wiring layer forming step is performed. In this first wiring layer forming step, as shown in FIG. 2B, first, titanium is used as the first laminated metal film 29a, titanium nitride is used as the second laminated metal film 29b, and aluminum is used as the main wiring metal film 29c. Then, the third laminated metal film 29d is coated in the order of titanium nitride to form a plate-like first wiring layer 29 ′. Thereafter, as shown in FIG. 2C, unnecessary portions other than the corresponding positions with respect to the first connection holes 27 are removed by photolithography and dry etching techniques, and the insulating layer 26 including the first connection holes 27 is formed. A first wiring layer 29 having a preset pattern shape is formed.

Next, as shown in FIG. 3A, a second insulating film 30 is formed so as to cover the surfaces of the first wiring layer 29 and the first interlayer insulating layer 26 where the first wiring layer 29 is not formed. A second film forming step is performed. In this second film formation step, silicon oxide is deposited with a film thickness of 30 nm or more and 1000 nm or less by a plasma CVD method using monosilane (SiH ₄ ) gas as a main reaction gas at a temperature of 300 ° C. or more and 400 ° C. or less. A second insulating film 30 is formed. Here, the temperature environment in which this plasma CVD method is performed needs to be 400 ° C. or less which is the recrystallization temperature of aluminum. In addition, the second insulating film 30 as the cap film has a high film formation speed and the limit of thinning of the void suppression is 30 nm, and 1000 nm is sufficient when the gap fill is performed. Yes. Note that the second insulating film 30 may be composed of a SiN film or a SiON film with a similar film thickness by plasma CVD using monosilane gas as the main reaction gas instead of silicon oxide.

  Next, as shown in FIG. 3B, a second interlayer insulating layer 31 is formed on the surface of the second insulating film 30 including the space between the first wiring layers 29 in order to fill the unevenness between the first wiring layers 29. A second insulating layer forming step of forming is performed. In the second insulating layer forming step, after silicon oxide is deposited by high-density plasma CVD or plasma CVD using an organic source such as TEOS, the surface is planarized by CMP. In the second insulating layer forming step, a CVD film different from the above may be formed as a single layer or a stacked layer.

Next, as shown in FIG. 3C, in order to electrically connect the second wiring layer 34 formed on the surface of the second interlayer insulating layer 31 and a predetermined portion of the first wiring layer 29, Then, a second connection hole 32 penetrating from the second interlayer insulating layer 31 to the second insulating film 30 is formed, and a second conductive path forming step of forming a second conductive portion 33 in the second connection hole 32 is performed. In the second conductive path forming step, first, the second connection hole 32 is formed by a photolithography technique and a dry etching technique so that a predetermined portion of the first wiring layer 29 is exposed. Next, after forming titanium nitride and a titanium laminated film in the formed second connection hole 32 by a sputtering method, tungsten is formed in the second connection hole 32 and the substrate surface by a CVD method containing tungsten hexafluoride gas as a main component. A film is formed. Thereafter, the second conductive portion 33 is formed by CMP. For forming the titanium nitride and the titanium laminated film, a CVD method using an organometallic compound as a source gas or a CVD method using TiCl ₄ as a source gas may be used. The second conductive portion 33 may be formed by using an etch back method in which tungsten is left in the second connection hole 32 by a dry etching method using SF ₆ gas.

  Next, the second wiring layer 34 is formed on the second interlayer insulating layer 31 including the second connection hole 32 so as to be electrically connected to the second connection hole 32 in which the second conductive portion 33 is formed. A second wiring layer forming step is performed. In this second wiring layer forming step, first, as shown in FIG. 4A, by sputtering, titanium is used as the first laminated metal film 34a, titanium nitride is used as the second laminated metal film 34b, and aluminum is used as the main wiring metal film 34c. The third laminated metal film 34d is coated in the order of titanium nitride to form a plate-like second wiring layer 34 ′. Thereafter, as shown in FIG. 4B, unnecessary portions other than the corresponding positions with respect to the second connection holes 32 are removed by photolithography and dry etching techniques, and the insulating layer 31 including the second connection holes 32 is formed. A second wiring layer 34 having a preset pattern shape is formed.

  Next, as shown in FIG. 4C, a third insulating film 35 is formed so as to cover the surface of the second wiring layer 34 and the second interlayer insulating layer 31 on which the second wiring layer 34 is not formed. A third film forming step is performed. In the third film forming step, silicon oxide is deposited with a film thickness of 30 nm or more and 1000 nm or less by a plasma CVD method using monosilane gas as a main reaction gas at a temperature of 300 ° C. or higher and 400 ° C. or lower to form a third insulating film 35. Form.

  Next, as shown in FIG. 1, in order to fill the irregularities between the second wiring layers 34, a third interlayer insulating layer 36 is formed on the surface of the third insulating film 35 including the space between the second wiring layers 34. A third insulating layer forming step is performed. In this third insulating layer forming step, after silicon oxide is deposited by high-density plasma CVD or plasma CVD using an organic source such as TEOS, the surface is planarized by CMP. In the third insulating layer forming step, a CVD film different from the above may be formed as a single layer or a stacked layer.

  In the present embodiment, the circuits provided on the semiconductor substrate 11 are the two layers 29 and 34. However, the number of layers can be set by repeatedly performing the insulating layer forming process including the conductive path forming process from the film forming process. It can be changed according to

  Finally, a hydrogenation step is performed in which heat treatment is performed at a temperature of 350 to 450 ° C. in an atmosphere of 100% hydrogen or a mixed gas atmosphere of hydrogen and nitrogen in about 30 to 300 minutes.

As described above, in the method for manufacturing the solid-state imaging device 10 of the present invention, the wiring layers 29 and 34 having the laminated metal films 29a, 29b, 29d, 34a, 34b, and 34d made of titanium or tantalum having hydrogen storage capability are formed. Later, the surface is coated with insulating films 30 and 35 made of SiO _2, SiN, or SiON by chemical vapor deposition using monosilane gas as the main reaction gas. At this time, in order to form a thin film by decomposing monosilane, which is the main reaction gas, and bonding with oxygen in nitrous oxide, the hydrogen components generated during the film formation are separated from the laminated metal films 29a, 29b, 29d, 34a, 34b, 34d can be occluded.

  Therefore, when the hydrogenation process is executed in the subsequent process, the hydrogenation inhibition of the semiconductor substrate 11 for the purpose of reducing the interface state can be reliably prevented. In addition, since a hydrogen component is occluded in titanium or tantalum, a large dedicated device is not required and the number of manufacturing steps does not increase.

  The solid-state imaging device 10 manufactured by this manufacturing method can sufficiently reduce the dark current as shown in FIG. As a result, the S / N ratio can be improved and the image quality can be improved. In FIG. 5 in which the conventional product and the product of the present invention are compared, the film formation conditions when the second and third insulating films 30 and 35 of the solid-state imaging device 10 of the present invention are formed are monosilane / nitrogen / suboxide. Nitrogen oxide = 30/2200/720 sccm, stage temperature: 400 ° C., pressure: 733 Pa, Power: 100 W.

  Note that the solid-state imaging device (semiconductor device) and the manufacturing method thereof according to the present invention are not limited to the configuration of the above-described embodiment, and various modifications are possible.

It is sectional drawing which shows the solid-state imaging device which is a semiconductor device of embodiment of this invention. (A), (B), (C) is sectional drawing which shows the manufacturing process of the semiconductor device of this embodiment. (A), (B), (C) is sectional drawing which shows the manufacturing process following FIG. (A), (B), (C) is sectional drawing which shows the manufacturing process following FIG. It is a graph which shows the comparison state of the dark current value of the semiconductor device of this invention, and the conventional semiconductor device.

Explanation of symbols

10 ... Solid-state imaging device (semiconductor device)
DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Pixel part 18 ... Peripheral (control) circuit part 26 ... 1st interlayer insulation layer 27 ... 1st connection hole 28 ... 1st electroconductive part 29 ... 1st wiring layer 29a ... 1st laminated metal film (high Melting point metal)
29b ... second laminated metal film (refractory metal compound)
29c: Main wiring metal film 29d: Third laminated metal film (refractory metal compound)
DESCRIPTION OF SYMBOLS 30 ... 2nd insulating film 31 ... 2nd interlayer insulating layer 32 ... 2nd connection hole 33 ... 2nd electroconductive part 34 ... 2nd wiring layer 35 ... 3rd insulating film 36 ... 3rd interlayer insulating layer

Claims (9)

In a semiconductor device in which a wiring layer for connecting circuits on a substrate is laminated on the substrate,
Wherein the wiring layer has a main wiring metal and layered structure of a refractory metal or refractory metal compound, the surface of the wiring layer, SiO ₂ or formed by a chemical vapor deposition method using monosilane gas as a main reactive gas A semiconductor device coated with an insulating film made of SiN or SiON.   2. The semiconductor device according to claim 1, wherein the circuit is a solid-state imaging device having a plurality of pixel portions and a control circuit portion, and having a wiring layer that connects the pixel portions and the control circuit portion.   The semiconductor device according to claim 1, wherein the wiring layer uses aluminum or copper as the main wiring metal and has a thickness of 100 nm to 1000 nm.   4. The wiring layer according to claim 1, wherein the refractory metal or the refractory metal compound contains titanium as a main component and has a thickness of 10 nm to 100 nm. 5. The semiconductor device described.   4. The wiring layer according to claim 1, wherein the refractory metal or the refractory metal compound contains tantalum as a main component and has a film thickness of 5 nm to 50 nm. The semiconductor device described.   The semiconductor device according to claim 1, wherein the insulating film has a thickness of 30 nm to 1000 nm. An insulating layer forming step of forming an insulating layer on the substrate;
A conductive path forming step of forming a connection hole having a conductive portion in the insulating layer;
A wiring layer forming step of forming a wiring layer having a laminated structure of a main wiring metal and a refractory metal or a refractory metal compound on the insulating layer including the connection hole;
A film forming step of coating the surface of the wiring layer with an insulating film made of SiO ₂ or SiN or SiON formed by chemical vapor deposition using monosilane gas as a main reaction gas;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 7, wherein the film forming step is performed in a temperature atmosphere of 300 ° C. or higher and 400 ° C. or lower.   An insulating layer forming step of forming an insulating layer on the insulating film after the film forming step; and a hydrogenating step of performing a heat treatment in a gas atmosphere containing hydrogen after the insulating layer forming step. A method for manufacturing a semiconductor device according to claim 7 or 8, wherein:

Images