JP2007019557A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a metal in a wiring layer from being corroded by allowing a trench pattern or hole pattern to reach the wiring layer beneath when the hole pattern and the trench pattern are formed for sealing. <P>SOLUTION: In a method for manufacturing a semiconductor device, a first metal wiring 102 is formed in a wiring formation region R1, and a second metal wiring 103 is formed in a sealing region R2. A recess 110 is formed by allowing upper portions of the wiring 102 and the wiring 103 to be recessed by chemical mechanical polishing process or etching. A second insulating film 104 for embedding the recess 110 is formed on a substrate and its upper surface is flattened. The hole pattern 106 and the trench pattern 107 are formed up to a halfway depth of the film 104, and ashing is performed and a polymer is removed. Then, the pattern 106 and the pattern 107 are allowed to reach the wiring 102 and the wiring 103. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device having a contact conductor portion on a wiring layer and a manufacturing method thereof.

  In recent years, miniaturization and high integration of semiconductor integrated circuits have remarkably advanced. As the miniaturization progresses, the delay time due to the operation of the transistor can be shortened. However, since the wiring resistance and the parasitic capacitance increase, it becomes difficult to shorten the wiring delay time. As a measure for shortening the wiring delay time, copper having a lower resistivity is employed as a wiring material in place of conventional aluminum in order to reduce the wiring resistance. In order to reduce parasitic capacitance, a low dielectric constant insulating film is employed as a material for an interlayer insulating film or the like.

  It is difficult to etch copper. Therefore, when wiring is formed using copper, a method of embedding copper after forming a hole pattern or a trench pattern in an insulating film by an inlay method is used.

  By the way, a trench pattern called a seal ring is formed in a chip of a semiconductor device in order to protect transistors and wirings provided in the chip from external moisture. The seal ring is formed so as to surround the periphery of the transistor and the wiring. The seal ring is formed simultaneously with the etching for forming the hole pattern (via).

  The hole pattern and the trench pattern for the seal ring are formed by the following method.

First, in order to form a hole pattern and a trench pattern, the interlayer insulating film is removed to an intermediate depth using a photoresist as a mask. Here, the process is stopped halfway, if the wiring layer located under the hole pattern and the trench pattern is exposed at this time, then when performing ashing or polymer removal to remove the photoresist, This is because the wiring layer corrodes. Therefore, ashing or polymer removal is performed with the interlayer insulating film remaining in a part of the thickness, and then the hole pattern and the trench pattern are made to reach the wiring layer using the interlayer insulating film itself as a mask.
JP 2002-118078 A

  However, the conventional semiconductor device has the following problems.

  Generally, the etching rate when performing etching increases as the opening area increases. Here, the opening area of the trench pattern is larger than the opening area of the hole pattern. Therefore, if the trench pattern and the hole pattern are formed simultaneously by etching, the trench pattern is formed deeper. Therefore, the depth of the trench pattern cannot be stopped halfway through the interlayer insulating film, and the metal of the underlying wiring layer may be exposed. If the metal is exposed at this stage, there is a problem in that the metal is corroded through the steps of resist removal by ashing and polymer washing later.

  Such a problem also occurs when a plurality of hole patterns are formed in the interlayer insulating film. That is, since the pattern density of each hole pattern is different, the insulating film cannot be removed at a uniform depth when forming the hole pattern. For this reason, the problem that the wiring layer located under the hole pattern is exposed occurs.

  An object of the present invention is to provide a method of manufacturing a semiconductor device in which corrosion of a metal in a wiring layer is unlikely to occur by taking measures for preventing the wiring layer from being exposed when forming a hole pattern or a trench pattern. .

  A first semiconductor device of the present invention includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a wiring layer provided at least above the first insulating film, and the first A second insulating film provided on the insulating layer and the wiring layer; a third insulating film provided on the second insulating film; the third insulating film and the second insulating film; A semiconductor device including at least one contact conductor portion that penetrates the insulating film and reaches the wiring layer, wherein a concave portion is provided on the wiring layer; The thickness of the portion located on the wiring layer is larger than the thickness of the portion located on the first insulating film in the second insulating film.

  As described above, since the portion of the second insulating film located above the wiring layer is formed thick, the third insulating film and the second insulating film are removed in order to form the contact conductor portion. In the process, it becomes easy to leave a part of the second insulating film on the wiring layer, and the wiring layer is hardly exposed. In this state, treatment that may corrode the metal such as ashing or polymer removal is performed, and then the third insulating film and the second insulating film are further removed to expose the wiring layer, and the contact conductor portion Can be filled with conductors. In other words, since it is possible to perform a process that may corrode the metal without exposing the wiring layer, the corrosion of the wiring layer can be prevented.

  On the other hand, since the thickness of the second insulating film other than the portion located on the wiring layer does not increase, the dielectric constant between the layers can be kept constant.

  The wiring layer is a first wiring layer, and the contact conductor portion is a first contact conductor portion, and a second wiring layer provided at least on the first insulating film; A second contact conductor portion that penetrates the third insulating film and the second insulating film and reaches the second wiring layer, and the first wiring of the second insulating film The thickness of the portion located on the layer may be thicker than the thickness of the portion located on the second wiring layer in the second insulating film. In this case, even if the third insulating film and the second insulating film are removed in order to form the contact conductor portion, the region where the first contact conductor portion is formed in the second insulating film is thick. Since it is formed, it is possible to make it difficult to expose the first wiring layer. Accordingly, when the third insulating film and the second insulating film are removed in order to form the contact conductor portion, such as when the area where the first contact conductor portion is formed is larger than that of the second contact conductor portion. Even when the region where the first contact conductor portion is formed is deeply removed, the first wiring layer can be hardly exposed.

  The width of the first wiring layer may be formed larger than the width of the second wiring layer. In this case, the proportion of the conductor (metal) is larger in the region where the first wiring layer is formed than in the region where the second wiring layer is formed. Therefore, when a process such as chemical mechanical polishing is performed from above the first wiring layer and the second wiring layer, the depth of the recess formed on the first wiring layer due to the metal occupancy dependency of dishing. You can deepen the depth.

  A dummy wiring layer may be formed on the side of the first wiring layer. In this case, the proportion of the conductor (metal) is larger in the periphery of the region where the first wiring layer is formed than in the periphery of the region where the second wiring layer is formed. Therefore, when a process such as chemical mechanical polishing is performed from above the first wiring layer and the second wiring layer, the depth of the recess formed on the first wiring layer due to the metal occupancy dependency of dishing. You can deepen the depth.

  The first contact conductor portion may have a rectangular or belt-like planar shape, and the second contact conductor portion may have a circular or square planar shape.

  The first wiring layer and the first contact conductor may be a seal ring provided in a ring shape. In this case, the first contact conductor portion and the second contact conductor portion, which are seal rings, have greatly different areas, but the above-described structure prevents the first wiring layer from being exposed. can do.

  An element is provided in the semiconductor substrate, and the wiring layer may be electrically connected to the element. In this case, when the third insulating film and the second insulating film are removed when forming the wiring layer, the wiring layer can be hardly exposed even if an error occurs in the depth of removal. .

  The second insulating film is preferably a silicon insulating film containing carbon.

  A second semiconductor device of the present invention includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a wiring layer provided at least above the first insulating film, and the wiring layer An oxidation resistant conductor film overlying the first insulation film, a second insulation film provided on the oxidation resistance conductor film, and a second insulation film provided on the second insulation film. 3 insulating films, and at least one contact conductor portion that penetrates the third insulating film and the second insulating film and reaches the oxidation-resistant conductor film.

  Thus, in the step of removing the third insulating film and the second insulating film to form the contact conductor portion, the metal such as ashing or polymer removal is corroded with the oxidation-resistant conductor film exposed. Corrosion of the wiring layer can be prevented even when there is a fear of treatment. On the other hand, since the thickness of the second insulating film other than the portion located on the wiring layer does not increase, the dielectric constant between the layers can be kept constant.

  The oxidation-resistant conductive film may be a nitrogen-introduced layer in which nitrogen is introduced into the upper region of the wiring layer.

  The oxidation resistant conductor film may be titanium nitride.

    The wiring layer is a first wiring layer, and the oxidation-resistant conductor film is a first oxidation-resistant conductor film provided on the first wiring layer, and the contact conductor portion Is a first contact conductor portion, a second wiring layer provided at least above the first insulating film, and a second oxidation-resistant conductor film covering the second wiring layer And a second contact conductor that penetrates the third insulating film and the second insulating film and reaches the second oxidation-resistant conductor film, and the first contact conductor The upper surface area is larger than that of the second contact conductor portion. In this case, if the third insulating film and the second insulating film are removed when these contact conductor portions are formed, the region where the first contact conductor portions are formed is deeply removed. However, since the top of the first wiring layer is covered with the oxidation resistant film, even if the oxidation resistant film is exposed, the corrosion of the first wiring layer can be prevented.

  The first contact conductor portion may have a rectangular or belt-like planar shape, and the second contact conductor portion may have a circular or square planar shape.

  The first wiring layer and the first contact conductor may be a seal ring provided in a ring shape. In this case, the first contact conductor portion and the second contact conductor portion, which are seal rings, have greatly different areas, but the above-described structure prevents the first wiring layer from being exposed. can do.

  An element is provided in the semiconductor substrate, and the wiring layer may be electrically connected to the element. In this case, when removing the third insulating film and the second insulating film when forming the wiring layer, even if an error occurs in the depth of removal, the wiring layer can be made difficult to corrode. .

  The second insulating film is preferably a silicon insulating film containing carbon.

  The first semiconductor device manufacturing method of the present invention includes a step (a) of forming a first insulating film above a semiconductor substrate and a step of forming a wiring layer on at least the upper portion of the first insulating film. (B), a step (c) of forming a recess in the upper portion of the wiring layer, and a step of forming a second insulating film filling the recess on the first insulating film and the wiring layer (d) ), A step (e) of planarizing the upper surface of the second insulating film, and a step (f) of forming a third insulating film on the second insulating film after the step (e). And removing a portion of the third insulating film and the second insulating film located above the wiring layer to a depth not reaching the wiring layer using a photoresist as a mask. A step (g) of leaving a part of the second insulating film, and a step of removing the photoresist ( ) And a.

  As a result, the portion of the second insulating film located on the wiring layer can be formed thick, so that in the step (g), the wiring layer can be more reliably kept in an unexposed state. Therefore, even if the process which may corrode metals, such as ashing, is performed after process process (g), it can prevent that a wiring layer corrodes. On the other hand, since the film thickness of the second insulating film other than the portion located on the wiring layer does not increase, the dielectric constant between the layers can be kept constant in the semiconductor device manufactured by this method.

In the step (c), the recess may be formed by recessing the upper portion of the wiring layer by chemical mechanical polishing, dry etching, or wet etching.
In this case, in addition to the above-described effect, an effect that the adhesion between the first insulating film and the second insulating film can be improved can be obtained.

  In the step (b), as the wiring layer, a first wiring layer for seal ring and a second wiring layer located in a region surrounded by the first wiring layer are formed, and the step (b) In c), the concave portion is formed at least above the first wiring layer. In the step (g), the third insulating film and the second insulating film above the first wiring layer are formed. A portion of the third insulating film and the second insulating film that are located above the second wiring layer is formed by removing a part of the second insulating film. A hole pattern may be formed by removing a part of the hole pattern. In this case, since the opening area of the trench pattern is larger than the opening area of the hole pattern, in the step (g), the trench pattern is formed deeper than the hole pattern. However, since the region where the trench pattern is formed in the second insulating film is formed thick, it is possible to make it difficult to expose the first wiring layer.

  In the step (b), the width of the first wiring layer may be formed larger than the width of the second wiring layer. In this case, the proportion of the conductor (metal) is larger in the region where the first wiring layer is formed than in the region where the second wiring layer is formed. Accordingly, when a process such as chemical mechanical polishing is performed from above the first wiring layer and the second wiring layer in the step (c), the upper portion of the first wiring layer is formed due to the metal occupancy dependency of dishing. The depth of the formed recess can be increased.

  In the step (b), a dummy wiring layer may be formed on the side of the first wiring layer. In this case, the proportion of the conductor (metal) is larger in the periphery of the region where the first wiring layer is formed than in the periphery of the region where the second wiring layer is formed. Accordingly, when a process such as chemical mechanical polishing is performed from above the first wiring layer and the second wiring layer in the step (c), the upper portion of the first wiring layer is formed due to the metal occupancy dependency of dishing. The depth of the formed recess can be increased.

  Before the step (a), the method further includes a step (h) of forming an element in the semiconductor substrate. In the step (b), the wiring layer electrically connected to the element may be formed. Good. In this case, in the step (g), even if an error occurs in the depth to be removed, the wiring layer can be hardly exposed.

  The second method for manufacturing a semiconductor device of the present invention includes a step (a) of forming a first insulating film above a semiconductor substrate and a step of forming a wiring layer on at least the upper portion of the first insulating film. (B), a step (c) of forming an oxidation-resistant conductive film covering the wiring layer, and a second insulating film formed on the first insulating film and the oxidation-resistant conductive film. A step (d), a step (e) of forming a third insulating film on the second insulating film, and the wiring layer of the third insulating film and the second insulating film. A step (f) of removing a portion located above using a photoresist as a mask and a step (g) of removing the photoresist are provided.

  As a result, the upper part of the wiring layer can be covered with the oxidation-resistant conductor film. Therefore, in the step (f), after the oxidation-resistant conductor film is exposed, a treatment that may corrode the metal such as ashing is performed. However, corrosion of the wiring layer can be prevented. On the other hand, since the film thickness of the second insulating film other than the portion located on the wiring layer does not increase, the dielectric constant between the layers can be kept constant in the semiconductor device manufactured by this method.

  In the step (c), the oxidation-resistant conductor film may be formed by introducing nitrogen into the upper portion of the wiring layer by plasma treatment, wet treatment or ion implantation.

  In the step (c), a film containing nitrogen may be deposited on the wiring layer as the oxidation-resistant conductor film.

  In the step (b), as the wiring layer, a first wiring layer for seal ring and a second wiring layer located in a region surrounded by the first wiring layer are formed, and the step (b) In c), an oxidation-resistant conductor film is formed on the first wiring layer and the second wiring layer, and in the step (f), the third insulating film and the second insulating film are formed. A part of the portion located above the first wiring layer is removed to form a seal ring trench pattern, and the second insulating film out of the third insulating film and the second insulating film. The hole pattern may be formed by removing a part of the portion located above the wiring layer. In this case, since the opening area of the trench pattern is larger than the opening area of the hole pattern, in the step (f), the trench pattern is formed deeper than the hole pattern. However, since the region where the trench pattern is formed in the second insulating film is formed thick, it is possible to make it difficult to expose the first wiring layer.

Before the step (a), the method further includes a step (g) of forming an element in the semiconductor substrate,
In the step (b), the wiring layer electrically connected to the element may be formed. In this case, even if an error occurs in the depth to be removed in the step (f), the wiring layer can be hardly exposed.

  In the semiconductor device and the manufacturing method thereof according to the present invention, corrosion of the wiring layer can be prevented.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. 1A to 1F are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. 1A to 1F show a wiring formation region R1 and a seal ring region R2 for protecting the wiring formation region R1 from external moisture. The seal ring region R2 surrounds the side of the wiring formation region R1.

  First, in the step shown in FIG. 1A, a first insulating film 101 having a thickness of 500 nm made of a silicon oxide film is formed on a silicon substrate (not shown). Then, a photoresist (not shown) having an opening at a wiring pattern formation position is formed on the first insulating film 101 by photolithography. By performing dry etching using the photoresist as a mask, a part of the first insulating film 101 is removed to form wiring grooves 108 and 109 having a depth of 250 nm. Then, after removing the photoresist, a 30 nm thick laminated film (not shown) made of tantalum nitride and tantalum and a 1000 nm thick copper film (not shown) are formed on the substrate. Thereafter, the copper film and the laminated film are polished using a chemical mechanical polishing method, whereby a surface conductor film 102a covering the inner surface of the wiring groove 108 and a wiring via the surface conductor film 102a are formed in the wiring formation region R1. A first metal wiring 102 made of a metal wiring film 102b filling the trench 108 is formed. At this time, the second metal wiring 103 composed of the surface conductor film 103a and the metal wiring film 103b is formed in the seal ring region R2.

  Next, in the step shown in FIG. 1B, the upper portions of the first metal wiring 102 and the second metal wiring 103 are formed by chemical mechanical polishing or selective etching of metal using nitric acid or the like. By recessing, a recess shape (concave portion 110) having a depth of about 20 nm to 40 nm is formed.

  Next, in the step shown in FIG. 1C, a second insulating film 104 made of a silicon nitride carbonized film having a thickness of 100 nm to 150 nm is deposited on the substrate while filling the recess 110. At this time, as a material of the second insulating film 104, a silicon nitride film, a silicon carbide film, a silicon oxycarbide film, or the like may be used. Further, a laminate of these films may be formed.

  At this time, a step is formed on the upper surface of the second insulating film 104 reflecting the recess shape of the first metal wiring 102 and the second metal wiring 103.

  Next, in the step illustrated in FIG. 1D, the upper surface of the second insulating film 104 is planarized by performing chemical mechanical polishing, wet etching using sulfuric acid, nitric acid, or the like, or etch back. As a result, the thickness of the portion of the second insulating film 104 located on the first metal wiring 102 and the second metal wiring 103 is about 70 nm to 90 nm, and the thickness of the other portions is 50 nm. become.

  Next, in the step shown in FIG. 1E, a third insulating film 105 made of a carbon-containing silicon oxide film is deposited on the substrate. At this time, as the third insulating film 105, an FSG (Fluorinated Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or a porous film may be used. Further, a stacked film of these films may be used.

  Thereafter, a photoresist (not shown) having openings in the hole pattern formation region and the trench pattern formation region is formed on the third insulating film 105 by photolithography. Thereafter, by performing dry etching using a photoresist as a mask, a hole pattern (through hole) 106 is formed in the wiring formation region R1, and a trench pattern 107 is formed in the seal ring region R2. This dry etching is performed until the hole pattern 106 and the trench pattern 107 reach a depth in the middle of the second insulating film 104. At this time, since the opening area of the trench pattern 107 is larger than the opening area of the hole pattern 106, the trench pattern 107 is removed deeper. Thereafter, the photoresist is removed by ashing, and the polymer at the time of wet etching and dry etching is removed.

  Next, in the step shown in FIG. 1F, the second insulating film 104 remaining in the pattern is etched to form the hole pattern 106 and the trench pattern 107 into the first metal wiring 102 and the second metal wiring 103. The hole contact conductor portion 106 ′ having a circular or square planar shape and the ring-shaped trench contact conductor portion 107 ′ are formed. Note that this step is performed after completion of processing that may corrode metals such as ashing and polymer removal.

  Next, the structure of the wiring and the seal ring in the semiconductor device of this embodiment will be described with reference to FIG.

  As shown in FIG. 1F, the semiconductor device of this embodiment has a wiring formation region R1 and a seal ring region R2 surrounding the side of the wiring formation region R1. A first metal wiring 102 is provided in the wiring formation region R1, and a second metal wiring 103 is provided in the seal ring region R2. The first metal wiring 102 has a surface conductor film 102a that covers the surface of the wiring groove 108 and a metal wiring film 102b that covers the surface conductor film 102a. The second metal wiring 103 also has a surface conductor film 103a covering the surface of the wiring groove 109 and a metal wiring film 103b provided thereon. The upper portions of the first metal wiring 102 and the second metal wiring 103 are recessed, and a recess 110 is formed.

  A second insulating film 104 is provided on the first insulating film 101, the first metal wiring 102, and the second metal wiring 103. Since the second insulating film 104 fills the recess 110, the second insulating film 104 is formed such that the portion located on the first metal wiring 102 and the second metal wiring 103 is thicker than the other portions. Has been. The upper surface of the second insulating film 104 is planarized.

  A third insulating film 105 is provided on the second insulating film 104. In the wiring formation region R1, a hole contact conductor portion 106 ′ penetrating the third insulating film 105 and the second insulating film 104 is provided. Similarly, a trench contact conductor portion 107 ′ is formed in the seal ring region R2. Accordingly, the seal ring region R2 includes a ring-shaped ring composed of the second metal wiring 103 and the trench contact conductor 107 ′ so as to surround the first metal wiring 102 and the hole contact conductor 106 ′ in the wiring formation region R1. A seal ring is provided.

  Hereinafter, effects obtained in the present embodiment will be described in comparison with the prior art.

  Conventionally, the upper surfaces of the first metal wiring and the second metal wiring remain flat, and a second insulating film having a uniform thickness is formed on the first metal wiring and the second metal wiring. Was formed. For this reason, when the hole pattern and the trench pattern are formed, the trench pattern penetrates the second insulating film, and the second metal wiring may be exposed.

  On the other hand, in the present embodiment, only the portion of the second insulating film 104 located on the first metal wiring 102 and the second metal wiring 103 can be formed thick. Therefore, it is possible to prevent the trench pattern 107 from reaching the second metal wiring 103. Therefore, even if ashing or polymer cleaning is performed, the first metal wiring 102 does not corrode. Here, since the portion of the second insulating film 104 located on the first insulating film 101 does not become thick, the dielectric constant between layers can be kept constant.

  Further, a chemical mechanical polishing method or selective etching is performed to recess the upper portions of the first metal wiring 102 and the second metal wiring 103, thereby forming the first insulating film 101 and the second insulating film 104. Adhesion can be improved.

  In the present embodiment, the recess shape is formed on the first metal wiring 102 and the second metal wiring 103 by a chemical mechanical polishing method or the like. However, in the present invention, the recess shape may be formed by utilizing the property of copper that compresses when heat is applied. Specifically, after forming the first metal wiring 102 and the second metal wiring 103 in the step shown in FIG. 1A, heat treatment is performed at 200 degrees to 500 degrees. As a result, the metal wiring films 102 b and 103 b made of copper are compressed, and a recess is formed above the first metal wiring 102 and the second metal wiring 103. Also by this method, the same effect as described above can be obtained.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 2A to 2F are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. 2A to 2F show a wiring formation region R1 and a seal ring region R2 for protecting the wiring formation region R1 from external moisture. The seal ring region R2 surrounds the side of the wiring formation region R1.

  First, in the step shown in FIG. 2A, a first insulating film 111 having a thickness of 500 nm made of a silicon oxide film is formed on a silicon substrate (not shown). Then, a photoresist (not shown) having an opening in the metal wiring pattern formation region is formed on the first insulating film 111 by photolithography. By performing dry etching using the photoresist as a mask, a wiring groove 118 is formed in the wiring formation region R1, and a wiring groove 119 is formed in the seal ring formation region R2. At this time, the width of the wiring groove 119 is made wider than the width of the wiring groove 118. Specifically, when the width of the wiring groove 118 is smaller than 2 μm, the width of the wiring groove 119 is set to 2 μm or more.

  Then, after removing the photoresist, a 30 nm thick laminated film (not shown) made of tantalum nitride and tantalum and a 1000 nm thick copper film (not shown) are formed on the substrate. Thereafter, by polishing the copper and the laminated film using a chemical mechanical polishing method, a surface conductor film 112a covering the inner surface of the wiring groove 118 and a wiring groove via the surface conductor film 112a are formed in the wiring formation region R1. A first metal wiring 112 having a width of 2 μm or more, which is formed of the metal wiring film 112b filling the 118, is formed. At this time, in the seal ring region R2, the second metal wiring 113 having a width of 2 μm or more and formed of the surface conductor film 113a and the metal wiring film 113b is formed.

  Next, a chemical mechanical polishing method is performed in the step shown in FIG. At this time, the upper portion of the second metal wiring 113 is recessed using the metal occupancy dependency of dishing. This will be described in detail below. When a chemical mechanical polishing method is performed on a substrate in which metal is embedded, the depth at which the metal is removed tends to increase as the proportion of the metal in the region increases. In the present embodiment, the width of the second metal wiring 113 is formed wider than the width of the first metal wiring 112. In other words, the ratio of the metal per unit area is higher in the region where the second metal wiring 113 is formed. Therefore, the upper part of the second metal wiring 133 is recessed deeper than the other regions.

  Note that, instead of a method of making the width of the second metal wiring 113 wider than that of the first metal wiring 112, a metal pattern per unit area is formed by forming a dummy pattern around the second metal wiring 113. May be raised.

Next, in the step shown in FIG. 2C, a second insulating film 114 made of a silicon nitride carbide film is deposited on the first insulating film 111, the first metal wiring 112, and the second metal wiring 113. To do.
At this time, as a material of the second insulating film 114, a silicon nitride film, a silicon oxide film, a silicon oxycarbide film, or the like may be used. Further, a laminate of these films may be formed.

  At this time, a step is formed on the second insulating film 114 reflecting the recess shape of the second metal wiring 113.

  Next, in the step shown in FIG. 2D, the second insulating film 114 is planarized by performing chemical mechanical polishing, wet etching, or etch back.

  Next, in the step shown in FIG. 2E, a third insulating film 115 made of a carbon-containing silicon oxide film is deposited on the substrate. At this time, as the third insulating film 115, an FSG (Fluorinated Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or a porous film may be used. Further, a stacked film of these films may be used.

  Thereafter, a photoresist (not shown) having openings in the hole pattern formation region and the trench pattern formation region is formed on the third insulating film 115 by photolithography. Thereafter, by performing dry etching using a photoresist as a mask, a hole pattern 116 is formed in the wiring formation region R1, and a trench pattern 117 is formed in the seal ring region R2. This dry etching is performed until the trench pattern 117 reaches a depth in the middle of the second insulating film 114. At this time, since the opening area of the trench pattern 117 is larger than the opening area of the hole pattern 116, the trench pattern 117 is removed deeper. Thereafter, the photoresist is removed by ashing, and the polymer at the time of wet etching and dry etching is removed.

  Next, in the step shown in FIG. 2F, the second insulating film 114 remaining in the pattern is removed, and the hole pattern 116 and the trench pattern 117 are replaced with the first metal wiring 112 and the second metal wiring 113. The hole contact conductor portion 116 ′ having a circular or square planar shape and the trench contact conductor portion 117 ′ having a ring shape are formed. Note that this step is performed after completion of processing that may corrode metals such as ashing and polymer removal.

  Next, the structure of the wiring and the seal ring in the semiconductor device of the present embodiment will be described with reference to FIG. 2 (f) again.

  As shown in FIG. 2F, the semiconductor device of this embodiment has a wiring formation region R1 and a seal ring region R2 surrounding the side of the wiring formation region R1. A first metal wiring 112 is provided in the wiring formation region R1, and a second metal wiring 113 is provided in the seal ring region R2. Here, the width of the second metal wiring 113 is larger than the width of the first metal wiring 112.

  The first metal wiring 112 has a surface conductor film 112a that covers the surface of the wiring groove 118, and a metal wiring film 112b that covers the surface conductor film 112a. The second metal wiring 113 also has a surface conductor film 113a that covers the surface of the wiring groove 119 and a metal wiring film 113b provided thereon. The upper part of the second metal wiring 113 is recessed, and a recess 120 is formed.

  A second insulating film 114 is provided on the first insulating film 111, the first metal wiring 112, and the second metal wiring 113. Since the second insulating film 114 fills the recess 120, the second insulating film 114 is formed such that the portion located on the second metal wiring 113 is thicker than the other portions. The upper surface of the second insulating film 114 is planarized.

  A third insulating film 115 is provided on the second insulating film 114. In the wiring formation region R1, a hole contact conductor portion 116 ′ penetrating the third insulating film 115 and the second insulating film 114 is provided. Similarly, a trench contact conductor portion 117 'is formed in the seal ring region R2. Accordingly, the seal ring region R2 includes a ring-shaped ring composed of the second metal wiring 113 and the trench contact conductor 117 ′ so as to surround the first metal wiring 112 and the hole contact conductor 116 ′ in the wiring formation region R1. A seal ring is provided.

  Hereinafter, effects obtained in the present embodiment will be described in comparison with the prior art.

  Conventionally, the upper surface of the second metal wiring remains flat, and a second insulating film having a uniform thickness is formed on the second metal wiring. For this reason, when the hole pattern and the trench pattern are formed, the trench pattern penetrates the second insulating film, and the second metal wiring may be exposed.

  On the other hand, in the present embodiment, only the portion of the second insulating film 114 positioned on the second metal wiring 113 can be formed thick without increasing the number of steps. Therefore, it is possible to prevent the trench pattern 117 from reaching the second metal wiring 113. Therefore, even if ashing or polymer cleaning is performed, corrosion of the first metal wiring does not occur. Here, since the portion of the second insulating film 114 located on the first insulating film 111 does not become thick, the dielectric constant between the layers can be kept constant.

  Further, by performing chemical mechanical polishing or etching in order to recess the upper portion of the second metal wiring 113, the adhesion between the first insulating film 111 and the second insulating film 114 can be improved. .

  In this embodiment, the recess shape is formed using the metal occupancy dependency of dishing. However, the recess shape may be formed using the pattern density dependency. Alternatively, in the step shown in FIG. 2B of the present invention, etching is performed in a state where the region excluding the second metal wiring 113 is covered with a photoresist or the like, so that the upper portion of the second metal wiring 113 is formed. A recess shape may be formed. In this case, the same effect as described above can be obtained except that the number of steps increases.

  In the present embodiment, when chemical mechanical polishing is performed in the step shown in FIG. 2B, a highly soluble slurry such as hydrogen peroxide may be used. As a result, the metal polishing rate increases, so that the second metal wiring 113 can be recessed deeper.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 3A to 3E are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the third embodiment. 3A to 3E show a wiring formation region R1 and a seal ring region R2 for protecting the wiring formation region R1 from external moisture. The seal ring region R2 surrounds the side of the wiring formation region R1.

  First, in the step shown in FIG. 3A, a first insulating film 121 having a thickness of 500 nm made of a silicon oxide film is formed on a silicon substrate (not shown). Then, a photoresist (not shown) having an opening in the metal wiring pattern formation region is formed on the first insulating film 121 by photolithography. By performing dry etching using the photoresist as a mask, a part of the first insulating film 121 is removed to form wiring grooves 128 and 129 having a depth of 250 nm. Then, after removing the photoresist, a 30 nm thick laminated film (not shown) made of tantalum nitride and tantalum and a 1000 nm thick copper film (not shown) are formed on the substrate. Thereafter, the copper film and the laminated film are polished using a chemical mechanical polishing method, so that a wiring is formed in the wiring formation region R1 via the surface conductor film 122a covering the inner surface of the wiring groove 128 and the surface conductor film 122a. A first metal wiring 122 made of a metal wiring film 122b filling the trench 128 is formed. At this time, the second metal wiring 123 composed of the surface conductor film 123a and the metal wiring film 123b is formed in the seal ring region R2.

  Next, in the step shown in FIG. 3B, a plasma treatment using a nitrogen-containing gas, a wet treatment using ammonia, benzotriazole (BTA) or quinaldic acid, or ion implantation is performed to perform the first treatment. Nitrogen is supplied to the upper part of the metal wiring 122 and the second metal wiring 123. As a result, the upper portions of the first metal wiring 122 and the second metal wiring 123 are transformed into the oxidation resistant film 130. At the same time, the adhesion between the first insulating film 121 and the second insulating film 124 formed in a later step can be improved.

  Next, in the step shown in FIG. 3C, a second insulating film 124 made of a silicon nitride carbide film is deposited on the first insulating film 121 and the oxidation resistant film 130. At this time, as a material of the second insulating film 124, a silicon nitride film, a silicon carbide film, a silicon oxycarbide film, or the like may be used. Further, a laminate of these films may be formed.

  Next, in the step shown in FIG. 3D, a third insulating film 125 made of a carbon-containing silicon oxide film is deposited on the substrate. At this time, as the third insulating film 125, an FSG (Fluorinated Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or a porous film may be used. Further, a stacked film of these films may be used.

  Thereafter, a photoresist (not shown) having openings in the hole pattern formation region and the trench pattern formation region is formed on the third insulating film 125 by photolithography. Thereafter, by performing dry etching using a photoresist as a mask, a hole pattern 126 is formed in the wiring formation region R1, and a trench pattern 127 is formed in the seal ring region R2. In this dry etching, the trench pattern 127 may stop in the middle of the second insulating film 124, or may penetrate the second insulating film 124 and reach the oxidation resistant film 130. Thereafter, the photoresist is removed by ashing, and the polymer at the time of wet etching and dry etching is removed.

  Next, in the step shown in FIG. 3E, the second insulating film 124 remaining in the pattern is removed, and the hole pattern 126 and the trench pattern 127 are made to reach the oxidation resistant film 130 to form the trench. Are filled with a conductor to form a hole contact conductor portion 126 ′ having a circular or square planar shape and a ring-shaped trench contact conductor portion 127 ′.

  Next, the structure of the wiring and the seal ring in the semiconductor device of this embodiment will be described with reference to FIG.

  As shown in FIG. 3E, the semiconductor device of this embodiment has a wiring formation region R1 and a seal ring region R2 surrounding the side of the wiring formation region R1. A first metal wiring 122 is provided in the wiring formation region R1, and a second metal wiring 123 is provided in the seal ring region R2. The first metal wiring 122 has a surface conductor film 122a that covers the surface of the wiring groove 128 and a metal wiring film 122b that covers the surface conductor film 122a. The second metal wiring 123 also has a surface conductor film 123a that covers the surface of the wiring groove 129, and a metal wiring film 123b provided thereon. Nitrogen is contained in the upper portions of the metal wiring films 122b and 123b, and an oxidation resistant film 130 is formed.

  A second insulating film 124 is provided on the first insulating film 121, the first metal wiring 122, and the second metal wiring 123. A third insulating film 125 is provided on the second insulating film 124. In the wiring formation region R1, a hole contact conductor portion 126 'penetrating the third insulating film 125 and the second insulating film 124 is provided. Similarly, a trench contact conductor portion 127 'is formed in the seal ring region R2. Accordingly, the seal ring region R2 includes a ring-shaped ring composed of the second metal wiring 123 and the trench contact conductor portion 127 ′ so as to surround the first metal wiring 122 and the hole contact conductor portion 126 ′ in the wiring formation region R1. A seal ring is provided.

  Hereinafter, effects obtained in the present embodiment will be described in comparison with the prior art.

  Conventionally, when the trench pattern reaches the second metal wiring when forming the hole pattern and the trench pattern, the second metal wiring is corroded in the subsequent ashing and polymer removal steps.

  On the other hand, in this embodiment, the upper part of the second metal wiring 123 is changed to the oxidation resistant film 130. Therefore, even if the ashing or polymer removal step is performed in a state where the trench pattern 127 reaches the second metal wiring 123, the upper portion of the second metal wiring 123 is not corroded. Here, since the portion of the second insulating film 124 located on the first insulating film 121 does not become thick, the dielectric constant between the layers can be kept constant.

  Further, by containing nitrogen in the upper part of the first metal wiring 122 and the second metal wiring 123, there is an advantage that the etching resistance when the hole pattern 126 and the trench pattern 127 are formed is improved.

  3D, when the hole pattern 126 and the trench pattern 127 reach the oxidation resistant film 130, the hole pattern 126, the trench pattern 127, and the oxidation resistant film 130 are later formed. There is also an advantage that the step of removing the second insulating film 124 remaining therebetween can be omitted.

(Fourth embodiment)
A method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. 4A to 4E are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the fourth embodiment. 4A to 4E show a wiring formation region R1 and a seal ring region R2 for protecting the wiring formation region R1 from external moisture. The seal ring region R2 surrounds the side of the wiring formation region R1.

  First, in the step shown in FIG. 4A, a first insulating film 131 having a thickness of 500 nm made of a silicon oxide film is formed on a silicon substrate (not shown). Then, a photoresist (not shown) having an opening in the metal wiring pattern formation region is formed on the first insulating film 131 by photolithography. By performing dry etching using the photoresist as a mask, a part of the first insulating film 131 is removed to form wiring grooves 138 and 139 having a depth of 250 nm. Then, after removing the photoresist, a 30 nm thick laminated film (not shown) made of tantalum nitride and tantalum and a 1000 nm thick copper film (not shown) are formed on the substrate. Thereafter, the copper film and the laminated film are polished using a chemical mechanical polishing method, whereby a wiring is formed in the wiring forming region R1 through the surface conductor film 132a covering the inner surface of the wiring groove 138 and the surface conductor film 132a. A first metal wiring 132 made of a metal wiring film 132b filling the groove 138 is formed. At this time, the second metal wiring 133 composed of the surface conductor film 133a and the metal wiring film 133b is formed in the seal ring region R2.

  Next, in the step shown in FIG. 4B, an oxidation-resistant metal film 140 is selectively deposited on the first metal wiring 132 and the second metal wiring 133. An example of the material of the metal film 140 is titanium nitride (TiN).

  4C, a second insulating film 134 made of a silicon nitride carbide film is deposited on the first insulating film 131 and the metal film 140. At this time, as a material of the second insulating film 134, a silicon nitride film, a silicon carbide film, a silicon oxycarbide film, or the like may be used. Further, a laminate of these films may be formed. After that, the second insulating film 134 is planarized by performing chemical mechanical polishing, wet etching, or etch back.

  Next, in the step shown in FIG. 4D, a third insulating film 135 made of a carbon-containing silicon oxide film is deposited on the substrate. At this time, as the third insulating film 135, an FSG (Fluorinated Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or a porous film may be used. Further, a stacked film of these films may be used.

  Thereafter, a photoresist (not shown) having openings in the hole pattern formation region and the trench pattern formation region is formed on the third insulating film 135 by photolithography. Thereafter, by performing dry etching using a photoresist as a mask, a hole pattern 136 is formed in the wiring formation region R1, and a trench pattern 137 is formed in the seal ring region R2. In this dry etching, the trench pattern 137 may be formed to a depth halfway through the second insulating film 134, or may penetrate the second insulating film 134 and reach the metal film 140. Thereafter, the photoresist is removed by ashing, and the polymer at the time of wet etching and dry etching is removed.

  Next, in the step shown in FIG. 4E, the second insulating film 134 remaining in the pattern is removed, and the hole pattern 136 and the trench pattern 137 are replaced with the first metal wiring 132 and the second metal wiring 133. Then, the hole contact conductor portion 136 ′ having a circular or square planar shape and the trench contact conductor portion 137 ′ having a ring shape are formed.

  Next, the structure of the wiring and the seal ring in the semiconductor device of this embodiment will be described with reference to FIG.

  As shown in FIG. 4E, the semiconductor device of this embodiment has a wiring formation region R1 and a seal ring region R2 surrounding the side of the wiring formation region R1. A first metal wiring 132 is provided in the wiring formation region R1, and a second metal wiring 133 is provided in the seal ring region R2. The first metal wiring 132 has a surface conductor film 132a that covers the surface of the wiring groove 138 and a metal wiring film 132b that covers the surface conductor film 132a. The second metal wiring 133 also has a surface conductor film 133a that covers the surface of the wiring groove 139 and a metal wiring film 133b provided thereon.

  An oxidation-resistant metal film 140 such as titanium nitride is provided on the first metal wiring 132 and the second metal wiring 133. A second insulating film 134 is provided on the first insulating film 131 and the metal film 140. A third insulating film 135 is provided on the second insulating film 134. In the wiring formation region R1, a hole contact conductor portion 136 'that penetrates the third insulating film 135 and the second insulating film 134 is provided. Similarly, a trench contact conductor portion 137 'is formed in the seal ring region R2. Accordingly, the seal ring region R2 includes a ring-shaped ring composed of the second metal wiring 133 and the trench contact conductor portion 137 ′ so as to surround the first metal wiring 132 and the hole contact conductor portion 136 ′ in the wiring formation region R1. A seal ring is provided.

  In the present embodiment, the second metal wiring 133 is covered with the oxidation-resistant metal film 140. Therefore, even if the ashing or polymer removal process is performed while the trench pattern 137 reaches the metal film 140, the upper portion of the second metal wiring 133 is not corroded. Here, since the portion of the second insulating film 134 located on the first insulating film 131 is not thickened, the dielectric constant between the layers can be kept constant.

  Further, by forming the oxidation resistant metal film 140 on the first metal wiring 132 and the second metal wiring 133, the etching resistance when forming the hole pattern 136 and the trench pattern 137 is improved. There is also.

(Fifth embodiment)
A method for manufacturing a semiconductor device according to the fifth embodiment of the present invention will be described below with reference to FIGS. 5A to 5F are cross-sectional views illustrating a method for manufacturing a wiring region in a semiconductor device according to the fifth embodiment. In the first to fourth embodiments, the case where the depth difference between the hole pattern and the trench pattern occurs in the wiring region and the seal ring region has been described. On the other hand, this embodiment shows a case where a depth difference occurs for each hole pattern when a large number of hole patterns are formed in the wiring region.

  First, in the step shown in FIG. 5A, a first insulating film 141 having a thickness of 500 nm made of a silicon oxide film is formed on a silicon substrate (not shown). Then, a photoresist (not shown) having an opening in the metal wiring pattern formation region is formed on the first insulating film 141 by photolithography. By performing dry etching using the photoresist as a mask, a part of the first insulating film 141 is removed, and a wiring groove 148 having a depth of 250 nm is formed. Then, after removing the photoresist, a 30 nm thick laminated film (not shown) made of tantalum nitride and tantalum and a 1000 nm thick copper film (not shown) are formed on the substrate. Thereafter, the copper film and the laminated film are polished using a chemical mechanical polishing method, whereby a surface conductor film 142a covering the inner surface of the wiring groove 148 and a metal wiring filling the wiring groove 148 via the surface conductor film 142a A metal wiring 142 made of the film 142b is formed.

  Next, in the step shown in FIG. 5B, a depth of 20 nm to 40 nm is obtained by recessing the upper portion of the metal wiring 142 by chemical mechanical polishing or selective etching of metal using nitric acid or the like. A recess shape (concave portion 150) is formed.

  Next, in the step shown in FIG. 5C, a second insulating film 144 made of a silicon nitride carbonized film having a thickness of 100 nm to 150 nm is deposited on the substrate while filling the recess 150. At this time, as a material of the second insulating film 144, a silicon nitride film, a silicon carbide film, a silicon oxycarbide film, or the like may be used. Further, a laminate of these films may be formed.

  At this point, a step is formed on the second insulating film 144 reflecting the recess shape of the metal wiring 142.

  Next, in the step shown in FIG. 5D, the upper surface of the second insulating film 144 is planarized by performing chemical mechanical polishing, wet etching, or etch back. As a result, the thickness of the portion of the second insulating film 144 located on the metal wiring 142 is about 70 nm to 90 nm, and the thickness of the other portion is 50 nm.

  Next, in the step shown in FIG. 5E, a third insulating film 145 made of a carbon-containing silicon oxide film is deposited on the substrate. At this time, as the third insulating film 145, an FSG (Fluorinated Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or a porous film may be used. Further, a stacked film of these films may be used.

  Thereafter, a photoresist (not shown) having an opening in the hole pattern formation region is formed on the third insulating film 145 by photolithography. Thereafter, the hole pattern 146 is formed by performing dry etching using the photoresist as a mask. This dry etching is performed until the hole pattern 146 reaches a depth in the middle of the second insulating film 144. At this time, the depths of the plurality of hole patterns 146 are different due to the influence of pattern density. Thereafter, the photoresist is removed by ashing, and the polymer at the time of wet etching and dry etching is removed.

  Next, in the step shown in FIG. 5 (f), the second insulating film 144 remaining in the pattern is removed, the hole pattern 146 reaches the metal wiring 142, and the planar shape is filled with a conductor. A circular or square hole contact conductor portion 146 ′ is formed. Note that this step is performed after completion of processing that may corrode metals such as ashing and polymer removal.

  Next, the structure of the wiring and the hole contact conductor portion in the semiconductor device of the present embodiment will be described with reference to FIG.

  As shown in FIG. 5F, in the semiconductor device of this embodiment, a metal wiring 142 having a surface conductor film 142a and a metal wiring film 142b covering the surface conductor film 142a is provided in the first insulating film 141. ing. The upper part of the metal wiring 142 is recessed, and a recess 150 is provided.

  A second insulating film 144 is provided on the first insulating film 141 and the metal wiring 142. Since the second insulating film 144 fills the recess 150, the second insulating film 144 is formed so that the portion located on the metal wiring 142 is thicker than the other portions. The upper surface of the second insulating film 144 is planarized.

  A third insulating film 145 is provided on the second insulating film 144. A hole contact conductor portion 146 ′ that penetrates the third insulating film 145 and the second insulating film 144 is provided.

  Hereinafter, effects obtained in the present embodiment will be described in comparison with the prior art.

  Conventionally, the upper surface of the metal wiring remains flat, and the second insulating film and the third insulating film are formed on the metal wiring. When a plurality of hole patterns are formed in this state, the depth differs for each hole pattern due to pattern density and process variations. Therefore, some of the hole patterns may reach the metal wiring through the second insulating film. In particular, when a large number of hole patterns are formed, this fear has been increased.

  On the other hand, in the present embodiment, only the portion of the second insulating film 144 located on the metal wiring 142 can be formed thick. Therefore, the hole pattern 146 can be prevented from reaching the metal wiring 142. Therefore, even if ashing or polymer cleaning is performed, the metal wiring 142 does not corrode. Here, the portion of the second insulating film 144 located on the first insulating film 141 does not become thick, so that the dielectric constant between the layers can be kept constant.

  In addition, the adhesion between the first insulating film 141 and the second insulating film 144 can be improved by performing chemical mechanical polishing or selective etching to recess the upper portion of the metal wiring 142.

  In the present embodiment, the method of the first embodiment is applied when a plurality of hole patterns are formed in the wiring region. However, in the present invention, the methods of the third and fourth embodiments can be applied to the case where a plurality of hole patterns are formed in the wiring region.

  In the first to fourth embodiments, the case where the trench contact conductor portion is formed in a ring shape and used for a seal ring has been described. However, the trench contact conductor portion may be formed in a rectangular shape or a belt shape and used as a part of an electrode.

  As described above, the industrial applicability is high in that it can prevent the metal of the wiring located under the hole pattern or the trench pattern from corroding while keeping the dielectric constant in the interlayer insulating film constant. .

(A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device of 2nd Embodiment. (A)-(e) is sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment. (A)-(e) is sectional drawing which shows the manufacturing process of the semiconductor device of 4th Embodiment. (A)-(f) is sectional drawing which shows the manufacturing method of a wiring area | region among semiconductor devices in 5th Embodiment.

Explanation of symbols

101 first insulating film
102 1st metal wiring
102a Surface conductor film
102b Metal wiring film
103 Second metal wiring
103a Surface conductor film
103b Metal wiring film
104 Second insulating film
105 Third insulating film
106 hole pattern 106 'hole contact conductor
107 trench pattern 107 'trench contact conductor 108 wiring trench
109 Wiring groove
110 recess
111 First insulating film
112 First metal wiring
112a Surface conductor film
112b Metal wiring film
113 Second metal wiring
113a Surface conductor film
113b Metal wiring film
114 Second insulating film
115 third insulating film
116 hole pattern 116 'hole contact conductor
117 trench pattern
117 'trench contact conductor
118 Wiring groove
119 Wiring groove
120 recess
121 first insulating film
122 First metal wiring
122a Surface conductor film
122b Metal wiring film
123 Second metal wiring
123a Surface conductor film
123b Metal wiring film
124 Second insulating film
125 third insulating film
126 'hole contact conductor 126 hole pattern
127 trench pattern
127 'trench contact conductor
128 Wiring groove
129 Wiring groove 130 Oxidation resistant film
131 first insulating film
132 First metal wiring
132a Surface conductor film
132b Metal wiring film
133 Second metal wiring
133a Surface conductor film
133b Metal wiring film
134 Second insulating film
135 Third insulating film
136 hole pattern
136 'hole contact conductor
137 trench pattern
137 'trench contact conductor
138 Wiring groove
139 Wiring groove
140 Metal film
141 First insulating film
142 metal wiring
142a Surface conductor film
142b Metal wiring film
143 Metal wiring
144 Second insulating film
145 Third insulating film
146 hole pattern
146 'hole contact conductor
148 Wiring groove
150 recess

Claims (13)

A semiconductor substrate;
A first insulating film provided above the semiconductor substrate;
A wiring layer provided on at least an upper portion of the first insulating film;
An oxidation-resistant conductive film covering the wiring layer;
A second insulating film provided on the first insulating film and the oxidation-resistant conductor film;
A third insulating film provided on the second insulating film;
A semiconductor device comprising: at least one contact conductor portion that penetrates the third insulating film and the second insulating film and reaches the oxidation-resistant conductor film. The semiconductor device according to claim 1,
The semiconductor device, wherein the oxidation-resistant conductor film is a nitrogen-introduced layer in which nitrogen is introduced into an upper region of the wiring layer. The semiconductor device according to claim 1,
The semiconductor device, wherein the oxidation-resistant conductive film is titanium nitride. It is a semiconductor device given in any 1 paragraph among Claims 1-3,
The wiring layer is a first wiring layer,
The oxidation-resistant conductor film is a first oxidation-resistant conductor film provided on the first wiring layer,
The contact conductor portion is a first contact conductor portion,
A second wiring layer provided at least on the first insulating film;
A second oxidation-resistant conductor film covering the second wiring layer;
A second contact conductor that penetrates the third insulating film and the second insulating film and reaches the second oxidation-resistant conductive film,
The first contact conductor portion is a semiconductor device having an upper surface area larger than that of the second contact conductor portion. The semiconductor device according to claim 4,
The first contact conductor portion has a rectangular or belt-like planar shape,
The semiconductor device, wherein the second contact conductor portion has a circular or square planar shape. A semiconductor device according to claim 4 or 5, wherein
The semiconductor device, wherein the first wiring layer and the first contact conductor are seal rings provided in a ring shape. It is a semiconductor device given in any 1 paragraph among Claims 1-3,
An element is provided in the semiconductor substrate,
The semiconductor device, wherein the wiring layer is electrically connected to the element. A semiconductor device according to any one of claims 1 to 7,
The semiconductor device, wherein the second insulating film is a silicon insulating film containing carbon. A step (a) of forming a first insulating film above the semiconductor substrate;
A step (b) of forming a wiring layer on at least an upper portion of the first insulating film;
A step (c) of forming an oxidation-resistant conductor film covering the wiring layer;
Forming a second insulating film on the first insulating film and the oxidation-resistant conductor film (d);
A step (e) of forming a third insulating film on the second insulating film;
A step (f) of removing a portion of the third insulating film and the second insulating film located above the wiring layer using a photoresist as a mask;
And a step (g) of removing the photoresist. A method of manufacturing a semiconductor device according to claim 9,
In the step (c), a method of manufacturing a semiconductor device, wherein the oxidation-resistant conductive film is formed by introducing nitrogen into the upper portion of the wiring layer by plasma treatment, wet treatment or ion implantation. A method of manufacturing a semiconductor device according to claim 9,
In the step (c), a method for manufacturing a semiconductor device, wherein a film containing nitrogen is deposited on the wiring layer as the oxidation-resistant conductor film. It is a manufacturing method of a semiconductor device given in any 1 paragraph among Claims 9-11,
In the step (b), a first wiring layer and a second wiring layer are formed as the wiring layer,
In the step (c), an oxidation resistant conductor film is formed on the first wiring layer and the second wiring layer,
In the step (f), a trench pattern is formed by removing a portion of the third insulating film and the second insulating film located above the first wiring layer, thereby forming the third pattern. A method of manufacturing a semiconductor device, wherein a hole pattern is formed by removing a portion of the insulating film and the second insulating film located above the second wiring layer. It is a manufacturing method of a semiconductor device given in any 1 paragraph among Claims 9-11,
Before the step (a), the method further includes a step (g) of forming an element in the semiconductor substrate,
In the step (b), a method of manufacturing a semiconductor device, wherein the wiring layer electrically connected to the element is formed.

Images