JP2003306399A5 - - Google Patents

Download PDF

Info

Publication number
JP2003306399A5
JP2003306399A5 JP2003045552A JP2003045552A JP2003306399A5 JP 2003306399 A5 JP2003306399 A5 JP 2003306399A5 JP 2003045552 A JP2003045552 A JP 2003045552A JP 2003045552 A JP2003045552 A JP 2003045552A JP 2003306399 A5 JP2003306399 A5 JP 2003306399A5
Authority
JP
Japan
Prior art keywords
buffer
layer
indium phosphide
lead
based perovskite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2003045552A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003306399A (ja
Filing date
Publication date
Priority claimed from US10/093,342 external-priority patent/US6872252B2/en
Application filed filed Critical
Publication of JP2003306399A publication Critical patent/JP2003306399A/ja
Publication of JP2003306399A5 publication Critical patent/JP2003306399A5/ja
Withdrawn legal-status Critical Current

Links

JP2003045552A 2002-03-06 2003-02-24 シリコン基板上にリン化インジウム層を形成する方法 Withdrawn JP2003306399A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/093,342 US6872252B2 (en) 2002-03-06 2002-03-06 Lead-based perovskite buffer for forming indium phosphide on silicon
US10/093,342 2002-03-06

Publications (2)

Publication Number Publication Date
JP2003306399A JP2003306399A (ja) 2003-10-28
JP2003306399A5 true JP2003306399A5 (enExample) 2006-02-23

Family

ID=27787965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003045552A Withdrawn JP2003306399A (ja) 2002-03-06 2003-02-24 シリコン基板上にリン化インジウム層を形成する方法

Country Status (3)

Country Link
US (1) US6872252B2 (enExample)
EP (1) EP1347502A3 (enExample)
JP (1) JP2003306399A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4663216B2 (ja) * 2003-06-10 2011-04-06 ルネサスエレクトロニクス株式会社 半導体記憶装置およびその製造方法
FR2921200B1 (fr) * 2007-09-18 2009-12-18 Centre Nat Rech Scient Heterostructures semi-conductrices monolithiques epitaxiees et leur procede de fabrication

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4707216A (en) 1986-01-24 1987-11-17 University Of Illinois Semiconductor deposition method and device
US4865659A (en) 1986-11-27 1989-09-12 Sharp Kabushiki Kaisha Heteroepitaxial growth of SiC on Si
JPH01207920A (ja) 1988-02-16 1989-08-21 Oki Electric Ind Co Ltd ＩｎＰ半導体薄膜の製造方法
JP3263964B2 (ja) 1992-01-31 2002-03-11 富士通株式会社 半導体装置形成用結晶とその製造方法
US5981980A (en) 1996-04-22 1999-11-09 Sony Corporation Semiconductor laminating structure
JP3699823B2 (ja) * 1998-05-19 2005-09-28 株式会社東芝 半導体装置
JP2000305117A (ja) * 1999-02-19 2000-11-02 Fuji Xerox Co Ltd 光デバイス、光デバイスの駆動方法、及び光デバイスの製造方法
US6392257B1 (en) * 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
JP2001313429A (ja) 2000-04-27 2001-11-09 Tdk Corp 積層薄膜その製造方法および電子デバイス
US6558517B2 (en) * 2000-05-26 2003-05-06 Micron Technology, Inc. Physical vapor deposition methods
WO2002001648A1 (en) * 2000-06-28 2002-01-03 Motorola, Inc. Semiconductor structure, device, circuit, and process
WO2002003114A1 (en) * 2000-06-30 2002-01-10 Motorola, Inc. Integrated circuits with optical interconnect
US6590236B1 (en) * 2000-07-24 2003-07-08 Motorola, Inc. Semiconductor structure for use with high-frequency signals
US6583034B2 (en) * 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6563118B2 (en) * 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US6559471B2 (en) * 2000-12-08 2003-05-06 Motorola, Inc. Quantum well infrared photodetector and method for fabricating same
US6594414B2 (en) * 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch

Similar Documents

Publication Publication Date Title
WO2004051707A3 (en) Gallium nitride-based devices and manufacturing process
WO2005095679A3 (en) Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
CN100364052C (zh) 晶格调谐半导体衬底的形成
WO2002050345A3 (en) Semiconductor compliant substrate having a graded monocrystalline layer
CN100444323C (zh) 形成晶格调制半导体基片
WO2004006311A3 (en) Transfer of a thin layer from a wafer comprising a buffer layer
JP2008505834A5 (enExample)
EP1054442A3 (en) Method for growing epitaxial group III nitride compound semiconductors on silicon
EP1396877A3 (en) Substrate for electronic devices, manufacturing method therefor, and electronic device
JP2008538658A5 (enExample)
WO2006099171A3 (en) NOVEL GeSiSn-BASED COMPOUNDS, TEMPLATES, AND SEMICONDUCTOR STRUCTURES
WO2004060792A3 (en) Method of forming semiconductor devices through epitaxy
WO2005010964A3 (en) Silicon crystallization using self-assembled monolayers
WO2003096385A3 (en) Silicon-on-insulator structures and methods
WO2006060466A3 (en) Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate
WO2003094218A3 (en) Method of growing monocrystalline oxide having a semiconductor device thereon
WO2005013326A3 (en) Epitaxial growth of relaxed silicon germanium layers
JP2012516555A5 (enExample)
JP2003243302A5 (enExample)
JP2006210555A5 (enExample)
JP2010523458A5 (enExample)
TW200603211A (en) Lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
JPH11329971A5 (enExample)
WO2005043604A3 (en) Growth and integration of epitaxial gallium nitride films with silicon-based devices
WO2003009357A3 (en) Epitaxial semiconductor on insulator (soi) structures and devices