JP2003306399A - シリコン基板上にリン化インジウム層を形成する方法 - Google Patents

シリコン基板上にリン化インジウム層を形成する方法

Info

Publication number
JP2003306399A
JP2003306399A JP2003045552A JP2003045552A JP2003306399A JP 2003306399 A JP2003306399 A JP 2003306399A JP 2003045552 A JP2003045552 A JP 2003045552A JP 2003045552 A JP2003045552 A JP 2003045552A JP 2003306399 A JP2003306399 A JP 2003306399A
Authority
JP
Japan
Prior art keywords
layer
indium phosphide
buffer
silicon substrate
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2003045552A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003306399A5 (enExample
Inventor
Jun Amano
ジュン・アマノ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2003306399A publication Critical patent/JP2003306399A/ja
Publication of JP2003306399A5 publication Critical patent/JP2003306399A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3418—Phosphides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12687—Pb- and Sn-base components: alternative to or next to each other

Landscapes

  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2003045552A 2002-03-06 2003-02-24 シリコン基板上にリン化インジウム層を形成する方法 Withdrawn JP2003306399A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/093,342 US6872252B2 (en) 2002-03-06 2002-03-06 Lead-based perovskite buffer for forming indium phosphide on silicon
US10/093,342 2002-03-06

Publications (2)

Publication Number Publication Date
JP2003306399A true JP2003306399A (ja) 2003-10-28
JP2003306399A5 JP2003306399A5 (enExample) 2006-02-23

Family

ID=27787965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003045552A Withdrawn JP2003306399A (ja) 2002-03-06 2003-02-24 シリコン基板上にリン化インジウム層を形成する方法

Country Status (3)

Country Link
US (1) US6872252B2 (enExample)
EP (1) EP1347502A3 (enExample)
JP (1) JP2003306399A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010539723A (ja) * 2007-09-18 2010-12-16 サントル ナシオナル ドゥ ラ ルシェルシェサイアンティフィク（セエヌエールエス） エピタキシャル固体半導体ヘテロ構造及びその製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4663216B2 (ja) * 2003-06-10 2011-04-06 ルネサスエレクトロニクス株式会社 半導体記憶装置およびその製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4707216A (en) 1986-01-24 1987-11-17 University Of Illinois Semiconductor deposition method and device
US4865659A (en) 1986-11-27 1989-09-12 Sharp Kabushiki Kaisha Heteroepitaxial growth of SiC on Si
JPH01207920A (ja) 1988-02-16 1989-08-21 Oki Electric Ind Co Ltd ＩｎＰ半導体薄膜の製造方法
JP3263964B2 (ja) 1992-01-31 2002-03-11 富士通株式会社 半導体装置形成用結晶とその製造方法
US5981980A (en) 1996-04-22 1999-11-09 Sony Corporation Semiconductor laminating structure
JP3699823B2 (ja) * 1998-05-19 2005-09-28 株式会社東芝 半導体装置
JP2000305117A (ja) * 1999-02-19 2000-11-02 Fuji Xerox Co Ltd 光デバイス、光デバイスの駆動方法、及び光デバイスの製造方法
US6392257B1 (en) * 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
JP2001313429A (ja) 2000-04-27 2001-11-09 Tdk Corp 積層薄膜その製造方法および電子デバイス
US6558517B2 (en) * 2000-05-26 2003-05-06 Micron Technology, Inc. Physical vapor deposition methods
WO2002001648A1 (en) * 2000-06-28 2002-01-03 Motorola, Inc. Semiconductor structure, device, circuit, and process
WO2002003114A1 (en) * 2000-06-30 2002-01-10 Motorola, Inc. Integrated circuits with optical interconnect
US6590236B1 (en) * 2000-07-24 2003-07-08 Motorola, Inc. Semiconductor structure for use with high-frequency signals
US6583034B2 (en) * 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6563118B2 (en) * 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US6559471B2 (en) * 2000-12-08 2003-05-06 Motorola, Inc. Quantum well infrared photodetector and method for fabricating same
US6594414B2 (en) * 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010539723A (ja) * 2007-09-18 2010-12-16 サントル ナシオナル ドゥ ラ ルシェルシェサイアンティフィク（セエヌエールエス） エピタキシャル固体半導体ヘテロ構造及びその製造方法
JP2015008293A (ja) * 2007-09-18 2015-01-15 サントル ナシオナル ドゥ ラ ルシェルシェサイアンティフィク（セエヌエールエス） エピタキシャル固体半導体ヘテロ構造及びその製造方法
JP2017028318A (ja) * 2007-09-18 2017-02-02 サントル ナシオナル ドゥ ラ ルシェルシェサイアンティフィク（セエヌエールエス） エピタキシャル固体半導体ヘテロ構造及びその製造方法

Also Published As

Publication number Publication date
US6872252B2 (en) 2005-03-29
US20030168000A1 (en) 2003-09-11
EP1347502A2 (en) 2003-09-24
EP1347502A3 (en) 2005-07-27

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