JP2003224228A - 半導体装置用パッケージ並びに半導体装置及びその製造方法 - Google Patents

半導体装置用パッケージ並びに半導体装置及びその製造方法

Info

Publication number
JP2003224228A
JP2003224228A JP2002023106A JP2002023106A JP2003224228A JP 2003224228 A JP2003224228 A JP 2003224228A JP 2002023106 A JP2002023106 A JP 2002023106A JP 2002023106 A JP2002023106 A JP 2002023106A JP 2003224228 A JP2003224228 A JP 2003224228A
Authority
JP
Japan
Prior art keywords
conductor pattern
semiconductor element
forming layer
semiconductor device
pattern forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002023106A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003224228A5 (https=
Inventor
Seiki Shimada
清貴 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2002023106A priority Critical patent/JP2003224228A/ja
Publication of JP2003224228A publication Critical patent/JP2003224228A/ja
Publication of JP2003224228A5 publication Critical patent/JP2003224228A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2002023106A 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法 Pending JP2003224228A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002023106A JP2003224228A (ja) 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002023106A JP2003224228A (ja) 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2003224228A true JP2003224228A (ja) 2003-08-08
JP2003224228A5 JP2003224228A5 (https=) 2005-06-16

Family

ID=27745908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002023106A Pending JP2003224228A (ja) 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JP2003224228A (https=)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870249B2 (en) 2002-12-24 2005-03-22 Oki Electric Industry Co., Ltd. Semiconductor device and manufacturing method thereof
JP2005340578A (ja) * 2004-05-28 2005-12-08 Sanyo Electric Co Ltd 回路装置
JP2008103615A (ja) * 2006-10-20 2008-05-01 Shinko Electric Ind Co Ltd 電子部品搭載多層配線基板及びその製造方法
CN100472776C (zh) * 2005-05-27 2009-03-25 环隆电气股份有限公司 小型化无线通讯模块及其制造方法
KR100907639B1 (ko) * 2007-12-20 2009-07-14 삼성전기주식회사 다층 인쇄회로기판의 제조방법 및 그것을 이용한 반도체플라스틱 패키지
JP2011187919A (ja) * 2010-03-05 2011-09-22 Samsung Electro-Mechanics Co Ltd 電子素子内蔵型印刷回路基板及びその製造方法
JP2015026777A (ja) * 2013-07-29 2015-02-05 富士通株式会社 電子部品
KR101517541B1 (ko) * 2006-12-07 2015-05-04 스태츠 칩팩 아이엔씨. 다층 반도체 패키지

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870249B2 (en) 2002-12-24 2005-03-22 Oki Electric Industry Co., Ltd. Semiconductor device and manufacturing method thereof
JP2005340578A (ja) * 2004-05-28 2005-12-08 Sanyo Electric Co Ltd 回路装置
CN100472776C (zh) * 2005-05-27 2009-03-25 环隆电气股份有限公司 小型化无线通讯模块及其制造方法
JP2008103615A (ja) * 2006-10-20 2008-05-01 Shinko Electric Ind Co Ltd 電子部品搭載多層配線基板及びその製造方法
US8222747B2 (en) 2006-10-20 2012-07-17 Shinko Electric Industries Co., Ltd. Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
KR101517541B1 (ko) * 2006-12-07 2015-05-04 스태츠 칩팩 아이엔씨. 다층 반도체 패키지
KR100907639B1 (ko) * 2007-12-20 2009-07-14 삼성전기주식회사 다층 인쇄회로기판의 제조방법 및 그것을 이용한 반도체플라스틱 패키지
JP2011187919A (ja) * 2010-03-05 2011-09-22 Samsung Electro-Mechanics Co Ltd 電子素子内蔵型印刷回路基板及びその製造方法
JP2015026777A (ja) * 2013-07-29 2015-02-05 富士通株式会社 電子部品

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