JP2003173165A - Display device - Google Patents

Display device

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Publication number
JP2003173165A
JP2003173165A JP2002268656A JP2002268656A JP2003173165A JP 2003173165 A JP2003173165 A JP 2003173165A JP 2002268656 A JP2002268656 A JP 2002268656A JP 2002268656 A JP2002268656 A JP 2002268656A JP 2003173165 A JP2003173165 A JP 2003173165A
Authority
JP
Japan
Prior art keywords
reset
signal
switch
display
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002268656A
Other languages
Japanese (ja)
Other versions
JP4230744B2 (en
Inventor
Yoshiaki Aoki
良朗 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002268656A priority Critical patent/JP4230744B2/en
Publication of JP2003173165A publication Critical patent/JP2003173165A/en
Application granted granted Critical
Publication of JP4230744B2 publication Critical patent/JP4230744B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To surely prevent display unevenness. <P>SOLUTION: The display device is provided with a plurality of display pixels PX, driving circuits 14, 15 for supplying video signals to drive these display pixels PX, a plurality of pixel switches 13 for fetching the video signals from the driving circuits 14, 15, and a plurality of reset switches SW3 for fetching reset signals from reset signal terminals RESET prior to a plurality of the pixel switches. Each display pixel includes a self-luminous element 16, a driving control element 17 connected in series with the self-luminous element 16 between power supply terminals VEL, VSS, a capacitance element 18 for holding the video signal fetched by the corresponding pixel switch 13 as a control voltage of the driving control element 17, a threshold value cancelling circuit 20 for initializing the control voltage of the driving control element 17 at the level equivalent to a threshold voltage peculiar to the driving control element 17 by using the reset signal fetched by the corresponding reset switch SW3, SW1, and SW2. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、複数の表示画素が
表示画面を構成するように配置される表示装置に関し、
特に各表示画素が例えば有機ＥＬ(Electro Luminescenc
e)素子のような自己発光素子を含む表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device in which a plurality of display pixels are arranged so as to form a display screen,
In particular, each display pixel is, for example, an organic EL (Electro Luminescenc
e) A display device including a self-luminous element such as an element.

【０００２】[0002]

【従来の技術】近年では、有機ＥＬ表示装置が軽量、薄
型、高輝度という特徴を持つことから携帯電話のような
携帯用情報機器のモニタディスプレイとして注目されて
いる。典型的な有機ＥＬ表示装置は、表示画面を構成す
るためにマトリクス状に配列される複数の表示画素を備
える。この有機ＥＬ表示装置では、複数の走査線がこれ
ら表示画素の行に沿って配置され、複数の信号線がこれ
ら表示画素の列に沿って配置され、複数の画素スイッチ
がこれら走査線および信号線の交差位置近傍に配置され
る。各表示画素は自己発光素子である有機ＥＬ素子、一
対の電源端子間でこの有機ＥＬ素子に直列に接続される
薄膜トランジスタで構成される駆動制御素子、および駆
動制御素子の制御電圧を保持する容量素子を有する。各
画素スイッチは対応走査線から供給される走査信号に応
答して導通し、対応信号線から供給される映像信号を制
御電圧として駆動制御素子に印加する。駆動制御素子は
この制御電圧に応じた駆動電流を有機ＥＬ素子に供給す
る。2. Description of the Related Art In recent years, an organic EL display device has been noted as a monitor display for portable information equipment such as a mobile phone because of its features of light weight, thinness and high brightness. A typical organic EL display device includes a plurality of display pixels arranged in a matrix to form a display screen. In this organic EL display device, a plurality of scanning lines are arranged along the rows of these display pixels, a plurality of signal lines are arranged along the columns of these display pixels, and a plurality of pixel switches are arranged for these scanning lines and signal lines. It is placed near the intersection position of. Each display pixel is an organic EL element which is a self-luminous element, a drive control element composed of a thin film transistor connected in series to the organic EL element between a pair of power supply terminals, and a capacitive element which holds a control voltage of the drive control element. Have. Each pixel switch becomes conductive in response to the scanning signal supplied from the corresponding scanning line, and applies the video signal supplied from the corresponding signal line to the drive control element as a control voltage. The drive control element supplies a drive current according to the control voltage to the organic EL element.

【０００３】有機ＥＬ素子は赤、緑、または青の蛍光性
有機化合物を含む薄膜である発光層をカソード電極およ
びアノード電極間に挟持した構造を有し、発光層に電子
および正孔を注入しこれらを再結合させることにより励
起子を生成させ、この励起子の失活時に生じる光放出に
より発光する。アノード電極はＩＴＯ等で構成される透
明電極であり、カソード電極はアルミニウム等の金属で
構成される反射電極である。この構成により、有機ＥＬ
素子は１０Ｖ以下の印加電圧でも１００〜１０００００
ｃd／ｍ２程度の輝度を得ることができる。An organic EL element has a structure in which a light emitting layer, which is a thin film containing a red, green, or blue fluorescent organic compound, is sandwiched between a cathode electrode and an anode electrode, and electrons and holes are injected into the light emitting layer. Excitons are generated by recombining these, and light is emitted by light emission generated when the excitons are deactivated. The anode electrode is a transparent electrode made of ITO or the like, and the cathode electrode is a reflective electrode made of metal such as aluminum. With this configuration, organic EL
The device is 100 to 100,000 even with applied voltage of 10 V or less.
A brightness of about cd / m 2 can be obtained.

【０００４】ところで、この有機ＥＬ表示装置では、表
示ムラが駆動制御素子のスレッショルド電圧Ｖthのバラ
ツキによって生じ易い。従来、このようなスレッショル
ド電圧Ｖthの影響を回避するため、例えば閾値キャンセ
ル回路が全表示画素に設けられる。各閾値キャンセル回
路は信号線駆動回路から映像信号に先だって供給される
リセット信号を用いて駆動制御素子の制御電圧を初期化
するように構成される。By the way, in this organic EL display device, display unevenness is likely to occur due to variations in the threshold voltage Vth of the drive control element. Conventionally, in order to avoid such an influence of the threshold voltage Vth, for example, a threshold cancel circuit is provided in all display pixels. Each threshold cancellation circuit is configured to initialize the control voltage of the drive control element using the reset signal supplied from the signal line drive circuit prior to the video signal.

【０００５】[0005]

【発明が解決しようとする課題】しかし、上述の信号線
駆動回路は各行の表示画素に供給される映像信号を更新
する毎に全信号線にリセット信号を供給する必要があ
る。さらに、有機ＥＬ表示装置の画素数が大型化および
高精細化のために増大した場合には、信号線駆動回路が
信号線電位を短時間にリセット電位に遷移させることが
困難となる。駆動制御素子の制御電圧がこの結果として
完全に初期化されないと、これが表示ムラの原因となる
ことがあった。However, the above-described signal line drive circuit needs to supply a reset signal to all signal lines every time the video signal supplied to the display pixels in each row is updated. Further, when the number of pixels of the organic EL display device increases due to the increase in size and definition, it becomes difficult for the signal line drive circuit to shift the signal line potential to the reset potential in a short time. As a result, if the control voltage of the drive control element is not completely initialized, this may cause display unevenness.

【０００６】本発明の目的は、表示ムラを確実に防止で
きる表示装置を提供することにある。An object of the present invention is to provide a display device which can surely prevent display unevenness.

【０００７】[0007]

【課題を解決するための手段】本発明によれば、表示画
面を構成する複数の表示画素と、前記複数の表示画素を
駆動する映像信号を供給する駆動回路と、前記駆動回路
からの映像信号をそれぞれ取り込む複数の画素スイッチ
と、前記複数の画素スイッチにそれぞれ先行してリセッ
ト信号端子からのリセット信号を取り込む複数のリセッ
トスイッチとを備え、前記複数の表示画素の各々は自己
発光素子、一対の電源端子間において前記自己発光素子
に直列に接続される駆動制御素子、対応画素スイッチに
よって取り込まれた映像信号を前記駆動制御素子の制御
電圧として保持する容量素子、および対応リセットスイ
ッチによって取り込まれたリセット信号を用いて前記駆
動制御素子の制御電圧をこの駆動制御素子固有のスレッ
ショルド電圧に等しいレベルに初期化する閾値キャンセ
ル回路を含む表示装置が提供される。According to the present invention, a plurality of display pixels forming a display screen, a drive circuit for supplying a video signal for driving the plurality of display pixels, and a video signal from the drive circuit. Each of the plurality of display pixels includes a self-luminous element, and a plurality of pixel switches that capture the reset signal from the reset signal terminal prior to the plurality of pixel switches. A drive control element serially connected to the self-luminous element between power supply terminals, a capacitive element that holds a video signal captured by a corresponding pixel switch as a control voltage of the drive control element, and a reset captured by a corresponding reset switch. A signal is used to change the control voltage of the drive control element to a threshold voltage specific to the drive control element. A display device including a threshold canceling circuit for initializing the level There are provided.

【０００８】この表示装置では、リセット信号はリセッ
ト信号端子からリセットスイッチに供給され、このリセ
ットスイッチにより取り込まれる。リセット信号端子は
リセット信号の電位から変化する必要がなく、このリセ
ット信号端子とリセットスイッチとを結ぶ配線について
も同様である。このため、リセットスイッチがリセット
信号端子およびリセットスイッチ間の配線に寄生する配
線容量の影響を受けずに短時間でリセット信号を取り込
むことが可能である。すなわち、リセット信号の供給に
映像信号用配線を用いた場合に生じる信号遷移時間の不
足によって駆動制御素子の制御電圧を完全に初期化でき
ないような状況になりにくい。従って、配線容量が増大
した場合でも駆動制御素子のスレッショルド電圧に依存
した表示ムラを確実に防止できる。また、リセット信号
端子および各リセットスイッチ間の配線パターンには自
由度があるため、リセットスイッチ相互の配置に依存し
た電圧降下の影響を考慮した配線パターンを用いること
が可能である。In this display device, the reset signal is supplied from the reset signal terminal to the reset switch and fetched by the reset switch. The reset signal terminal does not need to change from the potential of the reset signal, and the same applies to the wiring connecting the reset signal terminal and the reset switch. Therefore, it is possible to capture the reset signal in a short time without the reset switch being affected by the wiring capacitance parasitic on the wiring between the reset signal terminal and the reset switch. That is, it is unlikely that the control voltage of the drive control element cannot be completely initialized due to the shortage of signal transition time that occurs when the video signal wiring is used to supply the reset signal. Therefore, it is possible to reliably prevent display unevenness depending on the threshold voltage of the drive control element even when the wiring capacitance increases. Further, since there is a degree of freedom in the wiring pattern between the reset signal terminal and each reset switch, it is possible to use a wiring pattern that considers the influence of voltage drop depending on the arrangement of the reset switches.

【０００９】[0009]

【発明の実施の形態】以下、本発明の第１実施形態に係
る有機ＥＬ表示装置について添付図面を参照して説明す
る。BEST MODE FOR CARRYING OUT THE INVENTION An organic EL display device according to a first embodiment of the present invention will be described below with reference to the accompanying drawings.

【００１０】図１はこの有機ＥＬ表示装置の構成を示
す。有機ＥＬ表示装置は有機ＥＬパネル１０および有機
ＥＬパネル１０を制御するコントローラＣＮＴにより構
成される。FIG. 1 shows the structure of this organic EL display device. The organic EL display device includes an organic EL panel 10 and a controller CNT that controls the organic EL panel 10.

【００１１】有機ＥＬパネル１０は、ガラス板等の光透
過性絶縁基板上にマトリクス状に配置される複数の表示
画素ＰＸ、これら表示画素ＰＸの行に沿って配置される
複数の走査線１１、これら表示画素ＰＸの行に直交する
方向に配置される複数の信号線１２、これら走査線１１
および信号線１２の交差位置近傍に配置される複数の画
素スイッチ１３、複数の走査線１１を順次駆動する制御
信号出力回路１４、および複数の信号線１２を駆動する
信号線駆動回路１５を備える。また、走査線１１と平行
に信号線１２とは独立に配線されるリセット信号用配線
ＲＳが配置される。各表示画素ＰＸは自己発光素子であ
る有機ＥＬ素子１６、一対の電源端子ＶＥＬ，ＶＳＳ間
でこの有機ＥＬ素子１６に直列に接続され例えばＰチャ
ネル薄膜トランジスタで構成される駆動制御素子１７、
および画素スイッチ１３により取込まれた映像信号を駆
動制御素子１７の制御電圧として保持する容量素子１８
を有する。電源端子ＶＥＬおよびＶＳＳは例えば＋１０
Ｖの電位および０Ｖの電位にそれぞれ設定される。The organic EL panel 10 includes a plurality of display pixels PX arranged in a matrix on a light-transmissive insulating substrate such as a glass plate, a plurality of scanning lines 11 arranged along the rows of the display pixels PX. A plurality of signal lines 12 arranged in a direction orthogonal to the rows of these display pixels PX, and these scanning lines 11
And a plurality of pixel switches 13 arranged near the intersection of the signal lines 12, a control signal output circuit 14 for sequentially driving the plurality of scanning lines 11, and a signal line drive circuit 15 for driving the plurality of signal lines 12. Further, a reset signal wiring RS that is wired independently of the signal line 12 is arranged in parallel with the scanning line 11. Each display pixel PX is an organic EL element 16 which is a self-luminous element, a drive control element 17 which is connected in series to the organic EL element 16 between a pair of power supply terminals VEL and VSS, and is composed of, for example, a P-channel thin film transistor,
And a capacitive element 18 for holding the video signal taken in by the pixel switch 13 as a control voltage for the drive control element 17.
Have. The power supply terminals VEL and VSS are, for example, +10.
The potential of V and the potential of 0V are set respectively.

【００１２】画素スイッチ１３は例えばＮチャネル薄膜
トランジスタにより構成され、走査線１１から供給され
る走査信号により駆動されたときに信号線１２から供給
される映像信号Ｖsig(＝０〜４Ｖ)を出力する。駆動制
御素子１７は画素スイッチ１３によって取り込まれ制御
電圧として印加される映像信号Ｖsigに応じた駆動電流
Ｉdを有機ＥＬ素子１６に供給する。有機ＥＬ素子１６
は赤、緑、または青の蛍光性有機化合物を含む薄膜であ
る発光層をカソード電極およびアノード電極間に挟持し
た構造を有し、発光層に電子および正孔を注入しこれら
を再結合させることにより励起子を生成させ、この励起
子の失活時に生じる光放出により発光する。The pixel switch 13 is composed of, for example, an N-channel thin film transistor, and outputs a video signal Vsig (= 0 to 4V) supplied from the signal line 12 when driven by the scanning signal supplied from the scanning line 11. The drive control element 17 supplies the organic EL element 16 with a drive current Id corresponding to the video signal Vsig captured by the pixel switch 13 and applied as a control voltage. Organic EL element 16
Has a structure in which a light emitting layer, which is a thin film containing a red, green, or blue fluorescent organic compound, is sandwiched between a cathode electrode and an anode electrode, and injects electrons and holes into the light emitting layer to recombine them. To generate excitons, which emit light by light emission generated when the excitons are deactivated.

【００１３】コントローラＣＮＴは有機ＥＬパネル１０
の外部に配置されるプリント基板上に形成され、制御信
号出力回路１４および信号線駆動回路１５を制御する。
コントローラＣＮＴは外部から供給されるデジタル映像
信号および同期信号を受け取り、垂直走査タイミングを
制御する垂直走査制御信号、および水平走査タイミング
を制御する水平走査制御信号を同期信号に基づいて発生
し、これら垂直走査制御信号および水平走査制御信号を
それぞれ制御信号出力回路１４および信号線駆動回路１
５に供給すると共に、水平および垂直走査タイミングに
同期してデジタル映像信号を信号線駆動回路１５に供給
する。The controller CNT is an organic EL panel 10.
It is formed on a printed circuit board arranged outside the device and controls the control signal output circuit 14 and the signal line drive circuit 15.
The controller CNT receives a digital video signal and a synchronization signal supplied from the outside, generates a vertical scanning control signal for controlling a vertical scanning timing and a horizontal scanning control signal for controlling a horizontal scanning timing based on the synchronization signal, and outputs these vertical signals. The scanning control signal and the horizontal scanning control signal are supplied to the control signal output circuit 14 and the signal line drive circuit 1, respectively.
5, and a digital video signal is supplied to the signal line drive circuit 15 in synchronization with the horizontal and vertical scanning timings.

【００１４】信号線駆動回路１５は水平走査制御信号の
制御により各水平走査期間において順次得られる映像信
号をアナログ形式に変換し複数の信号線１２に並列的に
供給する。制御信号出力回路１４は垂直走査制御信号の
制御により各フレーム期間において順次複数の走査線１
１に走査信号を供給する。すなわち、各走査線は互いに
異なる１水平走査期間（１Ｈ）において走査信号により
駆動される。各行の画素スイッチ１３は対応走査線１１
から供給される走査信号により１水平走査期間のうちの
所定期間（映像書込期間）だけ導通し、走査信号が再び
１フレーム期間後に供給されるまで非導通となる。１行
分の駆動制御素子１７はこれら画素スイッチ１３の導通
により複数の信号線１２から供給される映像信号Ｖsig
に対応した駆動電流Ｉdを有機ＥＬ素子１６にそれぞれ
供給する。この映像信号Ｖsigは映像信号の更新周期で
ある１フレーム期間（１Ｆ）毎に更新される。The signal line driving circuit 15 converts the video signal sequentially obtained in each horizontal scanning period into an analog format by the control of the horizontal scanning control signal, and supplies it to the plurality of signal lines 12 in parallel. The control signal output circuit 14 sequentially controls the plurality of scanning lines 1 in each frame period under the control of the vertical scanning control signal.
The scan signal is supplied to 1. That is, each scanning line is driven by the scanning signal in one horizontal scanning period (1H) different from each other. The pixel switch 13 of each row corresponds to the corresponding scanning line 11
The scanning signal supplied from the device makes the circuit conductive for a predetermined period (video writing period) of one horizontal scanning period, and becomes non-conductive until the scanning signal is supplied again after one frame period. The drive control elements 17 for one row are supplied with video signals Vsig supplied from a plurality of signal lines 12 by the conduction of the pixel switches 13.
The drive current Id corresponding to is supplied to the organic EL element 16, respectively. The video signal Vsig is updated every one frame period (1F) which is the update cycle of the video signal.

【００１５】図２は表示画素ＰＸの等価回路を示す。各
表示画素ＰＸは、有機ＥＬ素子１６、駆動制御素子１
７、容量素子１８に加えて閾値キャンセル回路を備え
る。この閾値キャンセル回路は、駆動制御素子１７のゲ
ート−ソース間に接続されるキャパシタ２０、駆動制御
素子１７のドレイン電流を駆動電流Idとして有機ＥＬ素
子１６に出力する第1スイッチＳＷ１と、駆動制御素子
１７のゲート・ドレイン間の電位差をゼロにリセットす
る第２スイッチＳＷ２と、リセット信号端子ＲＥＳＥＴ
からのリセット信号Ｖrst（＝８Ｖ）を取り込むリセッ
トスイッチＳＷ３とから構成される。FIG. 2 shows an equivalent circuit of the display pixel PX. Each display pixel PX includes an organic EL element 16 and a drive control element 1.
7. A threshold cancel circuit is provided in addition to the capacitor 18. The threshold cancel circuit includes a capacitor 20 connected between the gate and the source of the drive control element 17, a first switch SW1 for outputting the drain current of the drive control element 17 to the organic EL element 16 as a drive current Id, and a drive control element. A second switch SW2 for resetting the potential difference between the gate and drain of 17 to zero, and a reset signal terminal RESET
And a reset switch SW3 that takes in the reset signal Vrst (= 8V) from the.

【００１６】これらスイッチＳＷ１〜ＳＷ３は駆動制御
素子１７の制御電圧をこの駆動制御素子１７のスレッシ
ョルド電圧Ｖthに等しいレベルに初期化するためにリセ
ット制御信号ＲＣ１およびＲＣ２の制御により図３に示
す関係でオンオフされる。These switches SW1 to SW3 have the relationship shown in FIG. 3 under the control of reset control signals RC1 and RC2 in order to initialize the control voltage of the drive control element 17 to a level equal to the threshold voltage Vth of the drive control element 17. Turned on and off.

【００１７】これらスイッチＳＷ１〜ＳＷ３について詳
しく説明すると、第２スイッチＳＷ２は駆動制御素子１
７のゲートおよびドレイン間に接続され、例えばＰチャ
ネル薄膜トランジスタで構成される。第1スイッチＳＷ
１は駆動制御素子１７のドレインと有機ＥＬ素子１６と
の間に接続され、例えばＰチャネル薄膜トランジスタで
構成される。リセットスイッチＳＷ３は画素スイッチ１
３およびキャパシタ２０間のノードとリセット信号端子
ＲＥＳＥＴとの間に接続され、例えばＰチャネル薄膜ト
ランジスタにより構成される。リセットスイッチＳＷ３
の薄膜トランジスタは、リセット信号用配線ＲＳに接続
されるソースおよび画素スイッチ１３のドレインに接続
されるドレインを含む。第1スイッチＳＷ１は制御信号
出力回路１４で発生されるリセット制御信号ＲＣ１によ
り制御され、第２スイッチＳＷ２およびリセットスイッ
チＳＷ３は制御信号出力回路１４で発生されるリセット
制御信号ＲＣ２により制御される。Explaining these switches SW1 to SW3 in detail, the second switch SW2 is the drive control element 1
7 is connected between the gate and the drain, and is composed of, for example, a P-channel thin film transistor. First switch SW
Reference numeral 1 is connected between the drain of the drive control element 17 and the organic EL element 16, and is composed of, for example, a P-channel thin film transistor. The reset switch SW3 is the pixel switch 1
3 and a node between the capacitor 20 and the reset signal terminal RESET, and is composed of, for example, a P-channel thin film transistor. Reset switch SW3
The thin film transistor of includes a source connected to the reset signal line RS and a drain connected to the drain of the pixel switch 13. The first switch SW1 is controlled by the reset control signal RC1 generated by the control signal output circuit 14, and the second switch SW2 and the reset switch SW3 are controlled by the reset control signal RC2 generated by the control signal output circuit 14.

【００１８】そしてこのような構成により、行毎にリセ
ット信号を各表示画素に供給することが可能となる。With such a configuration, it becomes possible to supply a reset signal to each display pixel for each row.

【００１９】リセット期間は、各水平走査期間の最初に
駆動制御素子１７のゲート-ソース間電圧を閾値電圧Ｖt
hより大きくなるよう設定するもので、画素スイッチ１
３がOFFの状態で、第1スイッチＳＷ１，第２スイッチＳ
Ｗ２，およびリセットスイッチＳＷ３をオン状態とす
る。ノードＡの電位はリセットスイッチＳＷ３からのリ
セット信号Ｖrstにより上昇し、ノードＢおよびＣの電
位は第２スイッチＳＷ２を介して流れる放電電流により
低下する。In the reset period, the gate-source voltage of the drive control element 17 is set to the threshold voltage Vt at the beginning of each horizontal scanning period.
It is set to be larger than h. Pixel switch 1
When 3 is OFF, the first switch SW1 and the second switch S
W2 and the reset switch SW3 are turned on. The potential of the node A rises due to the reset signal Vrst from the reset switch SW3, and the potentials of the nodes B and C fall due to the discharge current flowing through the second switch SW2.

【００２０】続く閾値Ｖthバラツキキャンセル期間で
は、画素スイッチ１３がオフ状態を維持した状態で、さ
らに第1スイッチＳＷ１をオフ状態に設定する。これに
より、ノードＢの電位が第２スイッチＳＷ２を介して流
れる充電電流により駆動制御素子１７のスレッショルド
電圧Ｖthに等しいレベルに上昇する。一方、キャパシタ
のノードＡ側には、リセット電圧が保持される。During the subsequent threshold Vth variation cancel period, the first switch SW1 is further set to the OFF state while the pixel switch 13 is kept in the OFF state. As a result, the potential of the node B rises to a level equal to the threshold voltage Vth of the drive control element 17 due to the charging current flowing through the second switch SW2. On the other hand, the reset voltage is held on the node A side of the capacitor.

【００２１】映像信号書込期間では、画素スイッチ１３
がオン状態にされ、第１スイッチＳＷ１、第２スイッチ
ＳＷ２およびリセットスイッチＳＷ３がオフ状態にされ
る。これにより、映像信号ＶsigがリセットスイッチＳ
Ｗ３からのリセット信号Ｖrstに代わって画素スイッチ
１３から供給されると、ノードＢの電位がスレッショル
ド電圧Ｖthを映像信号Ｖsigに加えたレベルとなる。In the video signal writing period, the pixel switch 13
Is turned on, and the first switch SW1, the second switch SW2, and the reset switch SW3 are turned off. As a result, the video signal Vsig is reset to the reset switch S.
When supplied from the pixel switch 13 instead of the reset signal Vrst from W3, the potential of the node B becomes a level obtained by adding the threshold voltage Vth to the video signal Vsig.

【００２２】映像信号表示期間では、第１スイッチＳＷ
１がオン状態にされ、画素スイッチ１３、第２スイッチ
ＳＷ２およびリセットスイッチＳＷ３がオフ状態にされ
る。これにより、駆動電流Ｉdが第1スイッチＳＷ１を介
して有機ＥＬ素子１６に供給される。駆動電流Ｉdはリ
セット信号Ｖrstと映像信号Ｖsigとの電位差により決定
されることになり、駆動制御素子１７のスレッショルド
電圧Ｖthにバラツキがあっても、駆動電流Ｉdの変動を
抑制できる。尚、本実施形態においては、駆動制御素子
１７の特性補正としてスレッショルド電圧のバラツキ補
正を行うものについて説明したが、これに限定されな
い。また、閾値キャンセル回路の構成も適宜選択でき
る。In the video signal display period, the first switch SW
1 is turned on, and the pixel switch 13, the second switch SW2, and the reset switch SW3 are turned off. As a result, the drive current Id is supplied to the organic EL element 16 via the first switch SW1. Since the drive current Id is determined by the potential difference between the reset signal Vrst and the video signal Vsig, even if the threshold voltage Vth of the drive control element 17 varies, fluctuations in the drive current Id can be suppressed. In addition, in the present embodiment, the case where the variation correction of the threshold voltage is performed as the characteristic correction of the drive control element 17 has been described, but the present invention is not limited to this. Also, the configuration of the threshold cancel circuit can be appropriately selected.

【００２３】本実施形態の有機ＥＬ表示装置では、複数
のリセットスイッチＳＷ３が複数の表示画素ＰＸの行に
沿って配置される複数のリセット信号用配線ＲＳを介し
てリセット信号端子ＲＥＳＥＴに接続される。リセット
信号Ｖrstはリセット信号端子ＲＥＳＥＴからリセット
スイッチＳＷ３に供給され、このリセットスイッチＳＷ
３により取り込まれる。リセット信号Ｖrstが映像信号
Ｖsig用配線である信号線１２とは別の専用配線である
リセット信号用配線ＲＳにより供給されるため、リセッ
トスイッチＳＷ３がリセット信号用配線ＲＳに寄生する
配線容量の影響を受けずに短時間でリセット信号を取り
込むことが可能である。すなわち、リセット信号Ｖrst
の供給に映像信号Ｖsigを供給する信号線１２を用いた
場合に生じる信号遷移時間の不足によって駆動制御素子
１７の制御電圧を完全に初期化できないような状況にな
りにくく、駆動制御素子１７の特性補正期間を十分に確
保することができる。従って、配線容量が増大した場合
でも駆動制御素子１７のスレッショルド電圧Ｖthに依存
した表示ムラを確実に防止できる。In the organic EL display device of the present embodiment, the plurality of reset switches SW3 are connected to the reset signal terminal RESET via the plurality of reset signal wirings RS arranged along the rows of the plurality of display pixels PX. . The reset signal Vrst is supplied from the reset signal terminal RESET to the reset switch SW3.
Incorporated by 3. Since the reset signal Vrst is supplied by the reset signal wiring RS that is a dedicated wiring different from the signal line 12 that is the wiring for the video signal Vsig, the reset switch SW3 affects the parasitic wiring capacitance of the reset signal wiring RS. It is possible to capture the reset signal in a short time without receiving the reset signal. That is, the reset signal Vrst
The characteristics of the drive control element 17 are unlikely to occur because the control voltage of the drive control element 17 cannot be completely initialized due to a shortage of signal transition time that occurs when the signal line 12 that supplies the video signal Vsig is used to supply It is possible to secure a sufficient correction period. Therefore, even if the wiring capacitance increases, it is possible to reliably prevent display unevenness depending on the threshold voltage Vth of the drive control element 17.

【００２４】図４は本発明の第２実施形態に係る有機Ｅ
Ｌ表示装置の構成を示す。この有機ＥＬ表示装置はリセ
ット信号Ｖrst並びにリセット制御信号ＲＣ１およびＲ
Ｃ２用の配線を複数行の表示画素ＰＸについて共通化し
たことを除いて図１に示す有機ＥＬ表示装置と同様であ
る。このため、同様部分を同一参照符号で表しその説明
を省略する。FIG. 4 shows an organic E according to a second embodiment of the present invention.
The structure of an L display device is shown. This organic EL display device has a reset signal Vrst and reset control signals RC1 and R1.
It is the same as the organic EL display device shown in FIG. 1 except that the wiring for C2 is shared by the display pixels PX of a plurality of rows. Therefore, the same parts are denoted by the same reference numerals and the description thereof is omitted.

【００２５】具体的には、図４に示すようにリセット信
号Ｖrst並びにリセット制御信号ＲＣ１およびＲＣ２が
奇数および偶数行の表示画素ＰＸ間において走査線１１
と平行するようにそれぞれ配置される配線を介して供給
される。この場合、リセット信号Ｖrstおよびリセット
制御信号ＲＣ１およびＲＣ２を供給するために必要とさ
れる配線領域を低減することができるため、表示装置の
大型化および高精細化が容易になる。Specifically, as shown in FIG. 4, the scanning line 11 is provided between the display pixels PX of the reset signal Vrst and the reset control signals RC1 and RC2 in the odd and even rows.
Are supplied via wirings arranged so as to be parallel to In this case, it is possible to reduce the wiring area required to supply the reset signal Vrst and the reset control signals RC1 and RC2, and thus it is easy to increase the size and definition of the display device.

【００２６】図５は本発明の第３実施形態に係る有機Ｅ
Ｌ表示装置の構成を示す。この有機ＥＬ表示装置はリセ
ット信号用配線ＲＳを簡略化したことを除いて図１に示
す有機ＥＬ表示装置と同様である。このため、同様部分
を同一参照符号で表しその説明を省略する。FIG. 5 shows the organic E according to the third embodiment of the present invention.
The structure of an L display device is shown. This organic EL display device is the same as the organic EL display device shown in FIG. 1 except that the reset signal wiring RS is simplified. Therefore, the same parts are denoted by the same reference numerals and the description thereof is omitted.

【００２７】具体的には、図５に示すようにリセットス
イッチＳＷ３のソースがリセット信号用配線ＲＳを介し
て電源配線ＶＥＬに接続され、この配線ＲＳからの電源
電圧ＶＥＬをリセット信号Ｖrstとして取込む。この構
成は映像信号Ｖsigの最大値が電源電圧ＶＥＬにほぼ等
しい必要があるが、リセット信号用配線ＲＳのための配
線領域を低減することが可能である。Specifically, as shown in FIG. 5, the source of the reset switch SW3 is connected to the power supply wiring VEL via the reset signal wiring RS, and the power supply voltage VEL from this wiring RS is taken in as the reset signal Vrst. . In this configuration, the maximum value of the video signal Vsig needs to be substantially equal to the power supply voltage VEL, but the wiring area for the reset signal wiring RS can be reduced.

【００２８】図６は本発明の第４実施形態に係る有機Ｅ
Ｌ表示装置の構成を示す。この有機ＥＬ表示装置は、複
数のリセット信号用配線ＲＳが図６に示すように各信号
線１２に平行に配置されることを除いて図１に示す有機
ＥＬ表示装置と同様である。このため、同様部分を同一
参照符号で表しその説明を省略する。FIG. 6 shows an organic E according to the fourth embodiment of the present invention.
The structure of an L display device is shown. This organic EL display device is the same as the organic EL display device shown in FIG. 1 except that a plurality of reset signal wirings RS are arranged in parallel with each signal line 12 as shown in FIG. Therefore, the same parts are denoted by the same reference numerals and the description thereof is omitted.

【００２９】具体的には、複数のリセットスイッチＳＷ
３が複数の表示画素ＰＸの列方向に平行に配置される複
数のリセット信号用配線ＲＳを介してリセット信号端子
ＲＥＳＥＴに接続される。このような構成では、補正動
作時におけるリセット信号Ｖrstの供給に複数本のリセ
ット信号用配線ＲＳを用いることができ、リセット信号
Ｖrstの供給を一リセット配線に集中することなく、そ
の配線数分で分割することができる。そして、リセット
信号用配線内での電圧降下の発生を抑制することがで
き、画面の均一表示が可能となる。詳しく説明すると、
これらリセット信号用配線ＲＳによる電圧降下をリセッ
ト信号線数分で分割でき、この電圧降下に依存して１行
分の表示画素ＰＸ間で発生するクロストークを図１に示
す有機ＥＬ表示装置の場合よりも改善して均一な画像を
表示画面に表示させることができる。Specifically, a plurality of reset switches SW
3 is connected to the reset signal terminal RESET via a plurality of reset signal wirings RS arranged in parallel to the column direction of the plurality of display pixels PX. With such a configuration, a plurality of reset signal wirings RS can be used to supply the reset signal Vrst during the correction operation, and the supply of the reset signal Vrst is not concentrated on one reset wiring, but can be performed by the number of wirings. It can be divided. Then, it is possible to suppress the occurrence of a voltage drop in the reset signal wiring, and it is possible to uniformly display the screen. In detail,
In the case of the organic EL display device shown in FIG. 1, the voltage drop due to the reset signal wiring RS can be divided by the number of reset signal lines, and the crosstalk generated between the display pixels PX for one row depending on the voltage drop. It is possible to improve and display a uniform image on the display screen.

【００３０】図７は本発明の第５実施形態に係る有機Ｅ
Ｌ表示装置の構成を示す。この有機ＥＬ表示装置は、複
数のリセット信号用配線ＲＳが図７に示すように格子状
に配置されることを除いて図１に示す有機ＥＬ表示装置
と同様である。このため、同様部分を同一参照符号で表
しその説明を省略する。FIG. 7 shows an organic E according to the fifth embodiment of the present invention.
The structure of an L display device is shown. This organic EL display device is the same as the organic EL display device shown in FIG. 1 except that a plurality of reset signal wirings RS are arranged in a grid pattern as shown in FIG. Therefore, the same parts are denoted by the same reference numerals and the description thereof is omitted.

【００３１】具体的には、複数のリセットスイッチＳＷ
３が複数の表示画素ＰＸの行および列に沿って配置され
交差位置において互いに接続される複数のリセット信号
用配線ＲＳを介してリセット信号端子ＲＥＳＥＴに接続
される。このような構成では、第４実施形態と同様の効
果に加え、リセット信号Ｖrst供給を表示面内に格子状
に配置した配線により行うので、電圧降下を最小に抑え
ることができる。そのため、これらリセット信号用配線
ＲＳ間で生じる電圧降下のバラツキが一層低減され、ま
た電圧降下が発生したとしても、クロストークとして視
認されるのを抑制でき、さらに均一な画像を表示画面に
表示させることができる。Specifically, a plurality of reset switches SW
3 are arranged along the rows and columns of the plurality of display pixels PX, and are connected to the reset signal terminal RESET via the plurality of reset signal wirings RS that are connected to each other at the intersection positions. In such a configuration, in addition to the effect similar to that of the fourth embodiment, the reset signal Vrst is supplied by the wiring arranged in a grid pattern in the display surface, so that the voltage drop can be minimized. Therefore, the variation in the voltage drop that occurs between the reset signal wirings RS is further reduced, and even if the voltage drop occurs, it is possible to suppress the visual recognition as crosstalk and display a more uniform image on the display screen. be able to.

【００３２】以上説明したように、表示画素への映像信
号供給とリセット信号供給をそれぞれ独立した別の配線
で行うことにより、例えば大型化による負荷増大、ある
いは高精細化による水平走査期間の短縮に際しても、十
分な補正期間を確保することが可能となる。また、さら
に同時に補正動作を行う複数の表示画素に複数本の配線
からリセット信号を供給することで電圧降下を抑制で
き、画面の均一表示が可能となる。As described above, by supplying the video signal and the reset signal to the display pixels by independent wirings, for example, when the load is increased due to an increase in size or the horizontal scanning period is shortened due to high definition. Also, it becomes possible to secure a sufficient correction period. Further, by supplying a reset signal from a plurality of wirings to a plurality of display pixels that perform a correction operation at the same time, a voltage drop can be suppressed, and uniform display on the screen becomes possible.

【００３３】尚、本発明は上述の実施形態に限定され
ず、その要旨を逸脱しない範囲で様々に変形可能であ
る。The present invention is not limited to the above-mentioned embodiment, and can be variously modified without departing from the gist thereof.

【００３４】例えばリセットスイッチＳＷ３はＰチャネ
ル薄膜トランジスタで構成されたが、例えばＮチャネル
薄膜トランジスタ、あるいはトランスファゲート等のス
イッチ素子に変更し、リセット制御信号ＲＣ２とは逆極
性のリセット制御信号によりこのスイッチ素子を制御す
ることもできる。For example, although the reset switch SW3 is composed of a P-channel thin film transistor, it is changed to a switch element such as an N-channel thin film transistor or a transfer gate, and this switch element is switched by a reset control signal having a polarity opposite to that of the reset control signal RC2. It can also be controlled.

【００３５】また、リセット信号用配線ＲＳは各実施形
態において２行の表示画素ＰＸ毎に設けられたが３行以
上の表示画素ＰＸに対して１本の割合で設けられてもよ
く、所望の期間発光されるよう適宜設定される。Further, although the reset signal wiring RS is provided for each of the two rows of display pixels PX in each embodiment, one reset signal wiring RS may be provided for three or more rows of display pixels PX. It is appropriately set to emit light for a period.

【００３６】また、上述の実施形態では、第２スイッチ
ＳＷ２およびリセットスイッチＳＷ３は共通のリセット
制御信号ＲＣ２で制御する場合について説明したが、そ
れぞれ別出力のリセット制御信号を用いて制御してもよ
い。このように制御することにより、さらに動作を安定
させ、表示品位を向上させることが可能となる。Further, in the above-described embodiment, the case where the second switch SW2 and the reset switch SW3 are controlled by the common reset control signal RC2 has been described, but they may be controlled by using the reset control signals of different outputs. . By controlling in this way, it becomes possible to further stabilize the operation and improve the display quality.

【００３７】また、上述の実施形態では、映像信号のデ
ジタル−アナログ変換をガラス基板上に形成された信号
線駆動回路にて行う場合について説明したが、このアナ
ログ変換をガラス基板外部で行い、信号線駆動回路はア
ナログ映像信号を時分割で対応する信号線に供給するも
のであってもよい。Further, in the above-described embodiment, the case where the digital-analog conversion of the video signal is performed by the signal line drive circuit formed on the glass substrate has been described, but this analog conversion is performed outside the glass substrate and the signal is converted. The line drive circuit may supply the analog video signal to the corresponding signal line in a time division manner.

【００３８】さらに、上述の実施形態で有機ＥＬ素子１
６が用いられたが、本発明はこれに限定されず自己発光
可能な様々な発光素子にも適用できる。Furthermore, in the above-described embodiment, the organic EL device 1
Although No. 6 is used, the present invention is not limited to this, and can be applied to various light emitting devices capable of self-luminous.

【００３９】[0039]

【発明の効果】本発明によれば、表示ムラを確実に防止
できる表示装置を提供することができる。According to the present invention, it is possible to provide a display device capable of surely preventing display unevenness.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施形態に係る有機ＥＬ表示装置の
構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of an organic EL display device according to an embodiment of the present invention.

【図２】図１に示す表示画素の等価回路を示す図であ
る。FIG. 2 is a diagram showing an equivalent circuit of the display pixel shown in FIG.

【図３】図２に示す表示画素の動作を説明するための図
である。FIG. 3 is a diagram for explaining the operation of the display pixel shown in FIG.

【図４】本発明の第２実施形態に係る有機ＥＬ表示装置
の構成を示す回路図である。FIG. 4 is a circuit diagram showing a configuration of an organic EL display device according to a second embodiment of the present invention.

【図５】本発明の第３実施形態に係る有機ＥＬ表示装置
の構成を示す回路図である。FIG. 5 is a circuit diagram showing a configuration of an organic EL display device according to a third embodiment of the present invention.

【図６】本発明の第４実施形態に係る有機ＥＬ表示装置
の構成を示す回路図である。FIG. 6 is a circuit diagram showing a configuration of an organic EL display device according to a fourth embodiment of the present invention.

【図７】本発明の第５実施形態に係る有機ＥＬ表示装置
の構成を示す回路図である。FIG. 7 is a circuit diagram showing a configuration of an organic EL display device according to a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１３…画素スイッチ １４…制御信号出力回路 １５…信号線駆動回路 １６…有機ＥＬ素子 １７…駆動制御素子 １８…キャパシタ ＳＷ１…第１スイッチ ＳＷ２…第２スイッチ ＳＷ３…リセットスイッチ ＣＮＴ…コントローラ ＰＸ…表示画素 ＲＳ…リセット信号用配線 ＶＥＬ，ＶＳＳ…電源端子 ＲＥＳＥＴ…リセット信号端子 13 ... Pixel switch 14 ... Control signal output circuit 15 ... Signal line drive circuit 16 ... Organic EL element 17 ... Drive control element 18 ... Capacitor SW1 ... First switch SW2 ... Second switch SW3 ... Reset switch CNT ... controller PX ... Display pixel RS: Wiring for reset signal VEL, VSS ... Power supply terminal RESET ... Reset signal terminal

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｇ０９Ｇ 3/20 ６４２ Ｇ０９Ｇ 3/20 ６４２Ａ Ｈ０５Ｂ 33/14 Ｈ０５Ｂ 33/14 Ａ ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642A H05B 33/14 H05B 33/14 A

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 表示画面を構成する複数の表示画素と、
前記複数の表示画素を駆動する映像信号を供給する駆動
回路と、前記駆動回路からの映像信号をそれぞれ取り込
む複数の画素スイッチと、前記複数の画素スイッチにそ
れぞれ先行してリセット信号端子からのリセット信号を
取り込む複数のリセットスイッチとを備え、前記複数の
表示画素の各々は自己発光素子、一対の電源端子間にお
いて前記自己発光素子に直列に接続される駆動制御素
子、対応画素スイッチによって取り込まれた映像信号を
前記駆動制御素子の制御電圧として保持する容量素子、
および対応リセットスイッチによって取り込まれたリセ
ット信号を用いて前記駆動制御素子の制御電圧をこの駆
動制御素子固有のスレッショルド電圧に等しいレベルに
初期化する閾値キャンセル回路を含むことを特徴とする
表示装置。1. A plurality of display pixels constituting a display screen,
A drive circuit that supplies a video signal that drives the plurality of display pixels, a plurality of pixel switches that respectively capture the video signals from the drive circuit, and a reset signal from a reset signal terminal prior to each of the plurality of pixel switches. Each of the plurality of display pixels, each self-luminous element, a drive control element serially connected to the self-luminous element between a pair of power supply terminals, and an image captured by a corresponding pixel switch. A capacitive element that holds a signal as a control voltage of the drive control element,
And a threshold cancel circuit that initializes the control voltage of the drive control element to a level equal to a threshold voltage specific to the drive control element by using a reset signal fetched by a corresponding reset switch. 【請求項２】 前記リセットスイッチは複数の表示画素
に１本の割合で設けられるリセット信号用配線を介して
前記リセット信号端子に接続されることを特徴とする請
求項１に記載の表示装置。2. The display device according to claim 1, wherein the reset switch is connected to the reset signal terminal through a reset signal wiring provided at a ratio of one for a plurality of display pixels. 【請求項３】 前記リセットスイッチは前記リセット信
号として前記一対の電源端子の一方の電位を受け取るよ
うに接続されることを特徴とする請求項１に記載の表示
装置。3. The display device according to claim 1, wherein the reset switch is connected so as to receive the potential of one of the pair of power supply terminals as the reset signal. 【請求項４】 前記駆動制御素子は駆動用薄膜トランジ
スタを含み、前記閾値キャンセル回路は前記駆動用薄膜
トランジスタのドレインと前記自己発光素子間に接続さ
れる第1スイッチ、前記駆動用薄膜トランジスタのドレ
インと前記駆動用薄膜トランジスタのゲート間に接続さ
れる第２スイッチ、および前記リセットスイッチおよび
前記駆動用薄膜トランジスタのゲート間に接続されるキ
ャパシタを含むことを特徴とする請求項１に記載の表示
装置。4. The drive control element includes a drive thin film transistor, and the threshold cancel circuit includes a first switch connected between the drain of the drive thin film transistor and the self-luminous element, the drain of the drive thin film transistor and the drive. The display device according to claim 1, further comprising a second switch connected between the gates of the thin film transistors, and a capacitor connected between the reset switch and the gates of the driving thin film transistors. 【請求項５】 前記リセットスイッチおよび前記第２ス
イッチは共通な制御信号により制御される薄膜トランジ
スタであることを特徴とする請求項４に記載の表示装
置。5. The display device according to claim 4, wherein the reset switch and the second switch are thin film transistors controlled by a common control signal. 【請求項６】 前記第1スイッチは前記リセットスイッ
チおよび前記第２スイッチの制御信号とは独立な制御信
号により制御される薄膜トランジスタであることを特徴
とする請求項５に記載の表示装置。6. The display device according to claim 5, wherein the first switch is a thin film transistor controlled by a control signal independent of control signals of the reset switch and the second switch. 【請求項７】 映像信号を供給する前記複数信号線と、
前記複数の信号線と略直交して配置され走査信号を供給
する複数の走査線と、各々対応走査線からの走査信号に
応答して対応信号線から映像信号を取り込む複数の画素
スイッチと、前記複数の画素スイッチにそれぞれ接続さ
れ各々表示素子およびこの表示素子を駆動する駆動制御
素子とを含む複数の表示画素と、前記複数の信号線から
独立してリセット信号を供給するリセット信号用配線
と、各々前記リセット信号用配線および対応表示画素の
駆動制御素子間に配置され前記駆動制御素子への前記リ
セット信号の供給を制御する複数のリセットスイッチと
を備えることを特徴とする表示装置。7. The plurality of signal lines for supplying a video signal,
A plurality of scanning lines that are arranged substantially orthogonal to the plurality of signal lines and supply a scanning signal; a plurality of pixel switches that take in a video signal from the corresponding signal line in response to a scanning signal from the corresponding scanning line; A plurality of display pixels each including a display element and a drive control element for driving the display element, each of which is respectively connected to the plurality of pixel switches; and a reset signal wiring that supplies a reset signal independently from the plurality of signal lines, A display device, comprising: a plurality of reset switches, each of which is arranged between the reset signal wiring and the drive control element of the corresponding display pixel and controls supply of the reset signal to the drive control element. 【請求項８】 前記リセット信号用配線は格子状に配置
されることを特徴とする請求項７に記載の表示装置。8. The display device according to claim 7, wherein the reset signal wirings are arranged in a grid pattern. 【請求項９】 前記表示素子は自己発光素子であること
を特徴とする請求項７に記載の表示装置。9. The display device according to claim 7, wherein the display element is a self-luminous element. 【請求項１０】 前記表示画素は前記表示素子に対応し
て、前記駆動制御素子の制御電圧を保持する容量素子、
前記駆動制御素子の制御電圧をこの駆動制御素子固有の
スレッショルド電圧に等しくなるよう設定する閾値キャ
ンセル回路を含むことを特徴とする請求項９に記載の表
示装置。10. The display pixel corresponds to the display element, and a capacitive element that holds a control voltage of the drive control element,
10. The display device according to claim 9, further comprising a threshold cancel circuit that sets a control voltage of the drive control element to be equal to a threshold voltage specific to the drive control element. 【請求項１１】 前記閾値キャンセル回路およびリセッ
トスイッチの制御は同一配線を用いてなされることを特
徴とする請求項１０に記載の表示装置。11. The display device according to claim 10, wherein the threshold cancel circuit and the reset switch are controlled using the same wiring. 【請求項１２】 基板上に配置される複数の信号線と、
前記信号線と略直交して配置される複数の走査線と、ゲ
ートが前記走査線、ソースが前記信号線に接続される薄
膜トランジスタでなる画素スイッチと、前記画素スイッ
チのドレインに接続される表示画素と、前記信号線とは
別に配線されるリセット信号用配線と、ソースが前記リ
セット信号用配線、ドレインが前記画素スイッチのドレ
インに接続される薄膜トランジスタでなるリセットスイ
ッチとを備えることを特徴とする表示装置。12. A plurality of signal lines arranged on a substrate,
A plurality of scanning lines arranged substantially orthogonal to the signal lines, a pixel switch formed of a thin film transistor having a gate connected to the scanning line and a source connected to the signal line, and a display pixel connected to the drain of the pixel switch. And a reset signal wiring that is wired separately from the signal line, a reset signal wiring whose source is the reset signal wiring, and a drain which is a thin film transistor connected to the drain of the pixel switch. apparatus.
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