JP2009069571A - Electro-optical device, method of controlling electro-optical device, and electronic apparatus - Google Patents

Electro-optical device, method of controlling electro-optical device, and electronic apparatus Download PDF

Info

Publication number
JP2009069571A
JP2009069571A JP2007238887A JP2007238887A JP2009069571A JP 2009069571 A JP2009069571 A JP 2009069571A JP 2007238887 A JP2007238887 A JP 2007238887A JP 2007238887 A JP2007238887 A JP 2007238887A JP 2009069571 A JP2009069571 A JP 2009069571A
Authority
JP
Japan
Prior art keywords
potential
control
electro
gate
optical device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007238887A
Other languages
Japanese (ja)
Other versions
JP5045323B2 (en
Inventor
Hitoshi Ota
人嗣 太田
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP2007238887A priority Critical patent/JP5045323B2/en
Publication of JP2009069571A publication Critical patent/JP2009069571A/en
Application granted granted Critical
Publication of JP5045323B2 publication Critical patent/JP5045323B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To control a drive current of each electro-optical element while suppressing enlargement and complication of a circuit. <P>SOLUTION: Each of a plurality of unit circuits includes a drive transistor TDR and an electro-optical element W. The drive transistor TDR includes a gate D having a potential VG set in accordance with a data signal D[j] and a back gate B for controlling a channel formed in accordance with the potential VG of the gate G. The electro-optical element E has gradation changed in accordance with a drive current IDR flowing to the drive transistor TDR. A potential control circuit 38 variably controls a control potential VCTL in accordance with an operation mode. The control potential VCTL is commonly supplied to back gates B of respective drive transistors TDR in the plurality of unit circuits U. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for controlling an electro-optical element such as a light-emitting element.

Conventionally, a technique for uniformly controlling the amount of drive current supplied to each electro-optic element for a plurality of electro-optic elements has been proposed. For example, in Patent Document 1, in a display device in which a plurality of light-emitting elements are interposed between a power supply line and a ground line, each drive current is obtained by changing a voltage between the power supply line and the ground line by a power supply circuit. Techniques for controlling are disclosed.
JP 2002-341828 A

  In the configuration of Patent Document 1, the drive current supplied to each light emitting element flows through the power supply line and the ground line. However, in order to change the potential of the power supply line and ground line through which a large amount of current flows, a large-scale and complicated power supply circuit is required. In view of the above circumstances, an object of the present invention is to control the drive current of each electro-optic element while suppressing the increase in size and complexity of the circuit.

  In order to solve the above problems, an electro-optical device according to the invention includes a gate whose potential is set according to a data signal and a characteristic control electrode that controls a channel formed according to the potential of the gate. A plurality of unit circuits each including a drive transistor and an electro-optic element driven by a drive current flowing in the drive transistor, and a characteristic of each drive transistor in which the control potential is variably set and the control potential is set in the plurality of unit circuits And a potential control circuit to be supplied to the control electrode. Note that an electro-optical element is an element whose gradation (brightness and transmittance) changes with the supply of electric energy (application of voltage or supply of current).

  In the above configuration, since the drive current of each electro-optic element is uniformly controlled by changing the control potential supplied to the characteristic control electrode of the drive transistor, it is necessary to change the voltage across the electro-optic element. There is no. Therefore, compared to the configuration of Patent Document 1 that controls the voltage between both ends of the light emitting element, an increase in the size and complexity of the circuit of the electro-optical device is suppressed. In addition, since the current hardly flows through the wiring for supplying the control potential to the characteristic control electrode (for example, the potential supply line 18 in FIG. 2), the potential control circuit is realized by a small and simple circuit. Therefore, according to the present invention, it is possible to control the drive current of each electro-optic element while suppressing the increase in size and complexity of the circuit. The characteristic control electrode is a back gate (eg, back gate B in FIG. 3) facing the gate across the semiconductor layer, or a channel electrode (eg, channel electrode 26 in FIG. 9) conducting to the channel contact region of the semiconductor layer. is there.

  In a preferred aspect of the present invention, the potential control circuit sets the control potential to a reference potential equal to the source potential of the driving transistor in the standard mode, and controls in the first mode (for example, the power saving mode in the configuration of FIG. 2). The potential is set higher than the reference potential, and the control potential is set lower than the reference potential in the second mode (for example, the high luminance mode in the configuration of FIG. 2). According to the above aspect, it is possible to switch between a mode that prioritizes reduction of power consumption and a mode that prioritizes the amount of light emitted from the electro-optic element as necessary.

  In a preferred embodiment of the present invention, each of the plurality of unit circuits includes a first switching element (for example, switching element SW5 in FIG. 6) for controlling electrical connection between the characteristic control electrode and the potential control circuit, and a drive transistor. A second switching element that is diode-connected in the first period (for example, the switching element SW4 in FIG. 6), a first electrode to which a data signal is supplied in the second period after the elapse of the first period, and a gate of the driving transistor The first switching element is controlled to be in an off state in the first period and controlled to be in an on state in the second period, including a capacitor element (for example, the capacitor element C3 in FIG. 6) having the connected second electrode. Is done. According to the above aspect, it is possible to control the drive current of each electro-optical element while effectively compensating for the error in the threshold voltage of the drive transistor in each unit circuit.

  The electro-optical device according to the invention is used in various electronic apparatuses. A typical example of an electronic device is a device that uses an electro-optical device as a display device. Examples of the electronic apparatus according to the present invention include a personal computer and a mobile phone. However, the use of the electro-optical device according to the present invention is not limited to image display. For example, the electro-optical device of the present invention can also be applied as an exposure device (exposure head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

  The present invention is also specified as a method for controlling an electro-optical device including a plurality of unit circuits according to each of the above aspects. A driving method of an electro-optical device according to one aspect is characterized in that a control potential is variably set and the control potential is supplied to a characteristic control electrode of each driving transistor in a plurality of unit circuits. According to the above method, the same operation and effect as the electro-optical device of the present invention are exhibited. Further, assuming that each of the plurality of unit circuits includes a capacitor element having a first electrode and a second electrode connected to the gate of the driving transistor, the driving transistor is diode-connected in the first period. In addition, it is preferable to stop the supply of the control potential to the characteristic control electrode and supply the data signal to the first electrode and the control potential to the characteristic control electrode in the second period after the first period.

<A: First Embodiment>
FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention. The electro-optical device 100 is mounted on various electronic devices as a display device that displays an image. As shown in the figure, the electro-optical device 100 includes an element array unit 10 in which a plurality of unit circuits (pixel circuits) U are arranged, and peripheral circuits (control line drive circuits 32, 32) for driving each unit circuit U. A signal supply circuit 34, a power supply circuit 36, a potential control circuit 38, and a control circuit 42).

  The power supply circuit 36 generates a power supply potential VEL and a ground potential GND (VEL> GND). The power supply potential VEL is commonly supplied to each unit circuit U via the power supply line 161, and the ground potential GND is commonly supplied to each unit circuit U via the ground line 162. The potential control circuit 38 generates a control potential VCTL. The control potential VCTL is commonly supplied to the unit circuits U through the potential supply line 18. The control potential VCTL will be described later.

  In the element array section 10, m sets of control line groups 12 extending in the X direction and n signal lines 14 extending in the Y direction intersecting the X direction are formed (each of m and n). Is a natural number of 2 or more). Each unit circuit U is arranged corresponding to each intersection of the control line group 12 and the signal line 14. Therefore, in the entire element array unit 10, the unit circuits U are arranged in a matrix of m rows × n columns across the X direction and the Y direction.

  FIG. 2 is a circuit diagram showing a specific configuration of each unit circuit U. In the drawing, only one unit circuit U in the j-th column (j = 1 to n) belonging to the i-th row (i = 1 to m) is representatively shown. As shown in FIG. 2, each control line group 12 in FIG. 1 includes two control lines 12A and 12B.

  The unit circuit U includes an electro-optic element E. The electro-optical element E is interposed between the power supply line 161 and the ground line 162. The electro-optic element E of this embodiment is an organic EL element in which a light emitting layer of an organic EL (Electroluminescence) material is formed between an anode and a cathode facing each other. The electro-optical element E is driven at a gradation (luminance) corresponding to the amount of drive current IDR supplied to the light emitting layer.

  A P-channel type drive transistor TDR is disposed on the path of the drive current IDR (between the power supply line 161 and the anode of the electro-optic element E). The drive transistor TDR controls the amount of drive current IDR according to the potential VG (gate-source voltage) of its gate G. A capacitive element C1 is interposed between the gate G of the driving transistor TDR and the power supply line 161. Note that the capacitive element C1 may be interposed between a gate having a constant potential other than the power supply line 161 and the gate G.

  The drive transistor TDR is a four-terminal transistor having a back gate B in addition to a gate G, a source S, and a drain D. The back gate B of the drive transistor TDR in each unit circuit U is connected in common to the potential supply line 18. A capacitive element (bypass capacitor) C 2 is interposed between the back gate B and the ground line 162. The capacitive element C2 may be interposed between a constant potential wiring other than the ground line 162 and the back gate B.

  FIG. 3 is a cross-sectional view illustrating a specific structure of the drive transistor TDR. As shown in FIG. 3, the driving transistor TDR is a thin film transistor formed together with each electro-optic element E on the surface of the insulating substrate 20.

  The back gate B is formed on the surface of the substrate 20. The back gate B is covered with a gate insulating film 21, and a semiconductor layer (for example, a polysilicon film body) 22 is formed on the surface of the gate insulating film 21. A gate G is formed so as to face the channel region of the semiconductor layer 22 with the gate insulating film 23 on the surface of the semiconductor layer 22 interposed therebetween. That is, the back gate B is formed on the side opposite to the gate G with the semiconductor layer 22 interposed therebetween. A source S is connected to the source region of the semiconductor layer 22 through a through hole in the interlayer insulating layer 24, and a drain D is connected to the drain region of the semiconductor layer 22 through a through hole in the interlayer insulating layer 24.

  FIG. 4 is a graph showing the relationship between the potential VG (gate-source voltage) of the gate G of the drive transistor TDR and the drive current IDR flowing between the source and drain. In FIG. 4, the relationship between the potential VG and the drive current IDR when the potential VB of the back gate B is set to the reference potential VC is shown by a solid line. The reference potential VC is substantially equal to the potential of the source S (power supply potential VEL) of the drive transistor TDR. That is, the reference potential VC is set so that the voltage between the back gate and the source becomes zero.

  The thickness of the channel formed in the semiconductor layer 22 according to the potential VG of the gate G changes according to the potential VB (voltage between the back gate and the source) of the back gate B. Therefore, the amount of drive current IDR increases or decreases according to the potential VB of the back gate B. For example, the channel shrinks (the depletion layer expands) as the potential VB of the back gate B rises with respect to the potential of the source S (power supply potential VEL). Therefore, when the potential VB of the back gate B is set to a potential VH (VH> VEL) higher than the reference potential VC as shown by a chain line in FIG. 4, the amount of drive current IDR with respect to the potential VG of the gate G decreases. To do. In other words, the threshold voltage VTH of the drive transistor TDR decreases. On the other hand, the channel expands as the potential VB of the back gate B decreases with respect to the potential of the source S. Therefore, when the potential VB is set to a potential VL (VL <VEL) lower than the reference potential VC as shown by a broken line in FIG. 4, the current of the drive current IDR with respect to the potential VG of the gate G increases (drive transistor TDR). Threshold voltage VTH increases). As described above, the back gate B functions as an electrode (characteristic control electrode) for controlling the electrical characteristics of the drive transistor TDR.

  As shown in FIG. 2, the unit circuit U includes two switching elements SW (SW1, SW2). Each switching element SW is an N-channel thin film transistor formed on the surface of the substrate 20 together with the driving transistor TDR.

  The switching element SW1 is interposed between the gate G of the driving transistor TDR and the signal line 14 in the j-th column, and controls the electrical connection (conduction / non-conduction) between them. The gate of the switching element SW1 in each of the n unit circuits U belonging to the i-th row is commonly connected to the control line 12A of the i-th row.

  The switching element SW2 is interposed between the drain D of the driving transistor TDR and the anode of the electro-optical element E (that is, on the path of the driving current IDR) and controls the electrical connection between them. The gate of the switching element SW2 in each of the n unit circuits U belonging to the i-th row is commonly connected to the control line 12B of the i-th row. Since the path of the drive current IDR is established when the switching element SW2 becomes conductive, the switching element SW2 functions as a means for controlling whether or not the drive current IDR can be supplied to the electro-optical element E.

  The control line drive circuit 32 in FIG. 1 is a circuit that supplies a signal to each of the m sets of control line groups 12. First, the control line driving circuit 32 generates selection signals GSL [1] to GSL [m] for sequentially selecting the unit circuits U in units of rows, and outputs them to the control lines 12A. As shown in FIG. 5, the selection signals GSL [1] to GSL [m] are sequentially set to the high level every writing period (horizontal scanning period) PWR.

  Second, the control line drive circuit 32 generates control signals GDR [1] to GDR [m] and outputs them to the control lines 12B. As shown in FIG. 5, the control signal GDR [i] supplied to the control line 12B of the i-th row is the selection signal GSL next after the writing period PWR in which the selection signal GSL [i] becomes high level. [i] is set to the high level in the driving period PDR before the start of the writing period PWR in which the high level is set, and the low level is maintained in the period other than the driving period PDR (including the writing period PWR). A configuration in which the selection signals GSL [1] to GSL [m] and the control signals GDR [1] to GDR [m] are generated by separate circuits is also employed.

  The signal supply circuit 34 in FIG. 1 generates data signals D [1] to D [n] that specify the gradation of each unit circuit U and outputs the data signals to each signal line 14. The data signal D [j] supplied to the signal line 14 in the j-th column in the writing period PWR in which the selection signal GSL [i] is high level is the unit circuit U in the j-th column belonging to the i-th row. Is set to the potential VDATA corresponding to the gradation specified in.

  The control circuit 42 controls each circuit (control line drive circuit 32, signal supply circuit 34, power supply circuit 36, potential control circuit 38) by outputting various signals such as a synchronization signal and an image signal. As shown in FIG. 1, an operation unit 44 is connected to the control circuit 42. The operation unit 44 is a device that detects an operation by a user. The control circuit 42 selects an operation mode of the electro-optical device 100 according to the content of the operation detected by the operation unit 44.

  The operation modes in this embodiment include a standard mode, a power saving mode, and a high luminance mode. The power saving mode is an operation mode in which the power consumed by the electro-optical device 100 is reduced as compared with the standard mode and the high luminance mode. The high brightness mode is an operation mode in which the overall brightness (image brightness) of the element array unit 10 is increased as compared with the standard mode and the power saving mode.

  The potential control circuit 38 variably controls the control potential VCTL according to the operation mode selected by the control circuit 42. When the standard mode is selected, the potential control circuit 38 sets the control potential VCTL to the reference potential VC (VC = VEL). The potential control circuit 38 sets the control potential VCTL to the potential VH (VH> VC) when the power saving mode is selected, and sets the control potential VCTL to the potential VL (when the high luminance mode is selected. Set to VL <VC.

  Next, the operation of the unit circuit U in the j-th column belonging to the i-th row will be described. When the selection signal GSL [i] transits to a high level in the writing period PWR (that is, when the i-th row is selected), the switching element SW1 transits to the ON state. Therefore, the potential VDATA of the data signal D [j] is supplied from the signal line 14 in the j-th column to the gate G of the driving transistor TDR via the switching element SW1, and the charge corresponding to the potential VDATA is supplied to the capacitive element C1. Accumulated. That is, the potential VG of the gate G of the drive transistor TDR is set and held at the potential VDATA of the data signal D [j].

  When the control signal GDR [i] changes to a high level in the driving period PDR after the writing period PWR has elapsed, the switching element SW2 is turned on. Accordingly, a drive current IDR having a current amount corresponding to the potential VG of the gate G of the drive transistor TDR and the potential VB of the back gate B is transferred from the power supply line 161 to the electro-optical element E via the drive transistor TDR and the switching element SW2. Supplied. The electro-optical element E emits light with a luminance corresponding to the amount of drive current IDR. As described above, a desired image is displayed on the element array unit 10 by controlling the gradation of each electro-optical element E.

  The control potential VCTL supplied from the potential control circuit 38 to the back gate B of each drive transistor TDR via the potential supply line 18 is set to the reference potential VC in the standard mode. Therefore, for example, when the potential VG of the gate G is set to the potential V1 (VDATA) in FIG. 4 in the writing period PWR, the driving current IDR having the current amount Ia is supplied to the electro-optical element E in the immediately following driving period PDR. The On the other hand, since the control potential VCTL supplied to the back gate B of each drive transistor TDR is set to the potential VH in the power saving mode, the current amount Ia in the standard mode is set when the gate G is set to the potential V1. A drive current IDR having a smaller current amount Ib is supplied to the electro-optical element E during the drive period PDR. Therefore, the luminance of each electro-optical element E is lower than that in the standard mode, but the power consumed by the electro-optical device 100 is reduced compared to the standard mode.

  Further, since the potential VL is supplied to the back gate B of each drive transistor TDR in the high luminance mode, the drive current IDR when the gate G is set to the potential V1 is larger than the current amount Ia in the standard mode. The quantity is Ic. Therefore, the electric power consumed by the electro-optical device 100 increases as compared with the standard mode, but the luminance of each electro-optical element E increases as compared with the standard mode.

  As described above, in this embodiment, the drive current IDR of each electro-optical element E is uniformly controlled by changing the control potential VCTL supplied to the back gate B of the drive transistor TDR. It is not necessary to change the voltage between 161 and the ground line 162. Therefore, the power supply circuit 36 is reduced in size and simplified as compared with the configuration of Patent Document 1 that controls the voltage between the power supply line 161 and the ground line 162. Further, since the impedance of the back gate B is sufficiently high, almost no current flows through the potential supply line 18. Therefore, the potential control circuit 38 is realized by a small and simple circuit. As described above, according to this embodiment, it is possible to control the drive current IDR of each electro-optical element E while suppressing the increase in size and complexity of the peripheral circuit. In addition, the number of luminance steps (the number of gradations) of each electro-optical element E does not change according to the operation mode.

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described. The unit circuit U of this embodiment has a function of compensating for an error in the threshold voltage VTH of the driving transistor TDR (difference between the driving transistors TDR and a difference from the design value). In addition, about the element which an effect | action and function are the same as that of 1st Embodiment among this form, the same code | symbol as the above is attached | subjected and each detailed description is abbreviate | omitted suitably.

  FIG. 6 is a circuit diagram showing the configuration of the unit circuit U in the j-th column belonging to the i-th row, and FIG. 7 is a timing chart showing the waveforms of the signals supplied to the unit circuit U. As shown in FIG. 6, the control line group 12 includes a control line 12C in addition to the two control lines (12A, 12B) in the first embodiment. The control line drive circuit 32 generates initialization signals GRS [1] to GRS [m] and outputs them to the control lines 12C. As shown in FIG. 7, the initialization signal GRS [i] supplied to the control line 12C in the i-th row is an initialization period before the start of the writing period PWR in which the selection signal GSL [i] is at a high level. It becomes high level at PRS and maintains low level during the period other than the initialization period PRS. The drive period PDR in which the control signal GDR [i] is at the high level is the initialization period in which the initialization signal GRS [i] is at the high level after the writing period PWR in which the selection signal GSL [i] is at the high level. This is the period before the start of PRS.

  The power supply circuit 36 generates a constant potential (hereinafter referred to as “initialization potential”) VRS higher than the maximum value of the potential VDATA of the data signal D [j]. As shown in FIG. 6, the initialization potential VRS is commonly supplied to the unit circuits U through the initialization line 15. The point that the potential control circuit 38 selects the control potential VCTL supplied to each unit circuit U according to the operation mode is the same as in the first embodiment.

  Unit circuit U includes capacitive elements C3 and C4 and switching elements SW3 to SW5 in addition to drive transistor TDR, switching elements SW1 and SW2, electro-optical element E and capacitive element C1. The capacitive element C3 includes an electrode e1 and an electrode e2. The switching element SW1 is interposed between the electrode e1 and the signal line 14 in the j-th column. The electrode e2 is connected to the gate G of the drive transistor TDR.

  The switching elements SW3 to SW5 are N-channel thin film transistors formed on the surface of the substrate 20 together with the electro-optic element E and the driving transistor TDR. The switching element SW3 is interposed between the electrode e1 and the initialization line 15 and controls the electrical connection between them. The switching element SW4 is interposed between the gate G and the drain D of the driving transistor TDR and controls the electrical connection between them. The gates of the switching elements SW3 and SW4 in the unit circuits U belonging to the i-th row are commonly connected to the i-th control line 12C.

  The switching element SW5 is interposed between the back gate B of the driving transistor TDR and the potential supply line 18 to control the electrical connection between them. The gate of the switching element SW5 in each unit circuit U belonging to the i-th row is commonly connected to the control line 12A of the i-th row. The capacitive element C4 is interposed between the back gate B of the driving transistor TDR and the ground line 162 and holds the potential VB of the back gate B. The capacitive element C4 may be interposed between a constant potential wiring other than the ground line 162 and the back gate B.

  Next, the operation of the unit circuit U in the j-th column belonging to the i-th row will be described. In the initialization period PRS, the initialization signal GRS [i] is set to a high level, whereby the switching elements SW3 and SW4 are turned on. Accordingly, the initialization potential VRS is supplied from the initialization line 15 to the electrode e1 of the capacitive element C3 via the switching element SW3. Further, since the drive transistor TDR is diode-connected via the switching element SW4, the potential VG of the gate G of the drive transistor TDR is the difference between the power supply potential VEL supplied to the power supply line 161 and the threshold voltage VTH of the drive transistor TDR. It converges to a value (VG = VEL-VTH).

  When the initialization period PRS elapses, the initialization signal GRS changes to the low level, so that the switching elements SW3 and SW4 transition to the off state. Accordingly, the supply of the initialization potential VRS to the electrode e1 is stopped and the diode connection of the driving transistor TDR is released. When the writing period PWR starts following the initialization period PRS, the selection signal GSL [i] is set to a high level, so that the switching element SW1 is turned on. Therefore, the potential of the electrode e1 drops from the initialization potential VRS set in the initialization period PRS to the potential VDATA of the data signal D [j].

Since the impedance of the gate G of the drive transistor TDR is sufficiently high, if the electrode e1 fluctuates from the potential VRS to the potential VDATA by a change amount ΔV (ΔV = VRS−VDATA), the electrode e2 capacitively coupled to the electrode e1 (drive transistor) The potential VG of the TDR gate G) decreases by a change amount k · ΔV from the set value (VEL−VTH) in the initialization period PRS. That is, at the end point of the writing period PWR, the potential VG of the gate G of the driving transistor TDR is set to the level of the following equation (1).
VG = VEL−VTH−k · ΔV (1)
The coefficient k is a numerical value determined according to the capacitance ratio between the capacitive element C3 and another capacitor (capacitor C1 and gate capacitance of the drive transistor TDR).

  In the writing period PWR, the selection signal GSL [i] is set to the high level, so that the switching element SW5 is also turned on. That is, the back gate B of the driving transistor TDR and the potential supply line 18 are connected. Therefore, the control potential VCTL is supplied to the back gate B of the drive transistor TDR, and the charge corresponding to the control potential VCTL is held in the capacitive element C4.

  In the drive period PDR after the writing period PWR has elapsed, the control signal GDR [i] transitions to a high level, whereby the switching element SW2 transitions to the on state. Accordingly, the drive current IDR is supplied to the electro-optical element E via the drive transistor TDR and the switching element SW2.

Assume that the threshold voltage VTH of the driving transistor TDR is changed to the voltage VTH_BG by supplying the control potential VCTL to the back gate B in the writing period PWR. Even during the driving period PDR in which the switching element SW5 is in the OFF state, the potential VB of the back gate B is maintained at the control potential VCTL by the capacitive element C4. Therefore, if the drive transistor TDR operates in the saturation region, the drive current IDR in the drive period PDR becomes a current amount of the following equation (2). VGS is a gate-source voltage of the driving transistor TDR, and β is a gain coefficient of the driving transistor TDR.
IDR = (β / 2) (VGS−VTH_BG) 2
= (Β / 2) (VEL−VG−VTH_BG) 2
= (Β / 2) (k · ΔV + VTH−VTH_BG) 2 …… (2)

The threshold voltage VTH_BG is a voltage obtained by changing (offset) the initial threshold voltage VTH (threshold voltage in the initialization period PRS) by the change amount α by supplying the control potential VCTL to the back gate B (VTH_BG = VTH + α). . Therefore, equation (2) is transformed into the following equation (3).
IDR = (β / 2) (k · ΔV + α) 2 (3)
That is, the drive current IDR is determined according to the voltage VDATA and the change amount α of the data signal D [j] and does not depend on the threshold voltage VTH of the drive transistor TDR. Therefore, it is possible to suppress gradation unevenness (variation in each drive current IDR) of each electro-optic element E due to an error in the threshold voltage VTH of each drive transistor TDR. Further, the change amount α in the equation (3) changes according to the control potential VCTL. Therefore, also in the present embodiment, as in the first embodiment, the amount of drive current IDR varies for each operation mode in accordance with the control potential VCTL.

  In the configuration in which elements (switching elements SW3 and SW4 and capacitive element C3) for compensating for an error in the threshold voltage VTH of the driving transistor TDR are simply added to the configuration in FIG. As described below, the drive current IDR cannot be controlled in accordance with the control potential VCTL.

In contrast, the switching element SW5 is not installed. That is, the control potential VCTL is constantly supplied to the back gate B of the drive transistor TDR throughout the entire period including the initialization period PRS. Therefore, in the initialization period PRS, the potential VG of the gate G of the drive transistor TDR is a difference value (VG = VEL) between the power supply potential VEL supplied to the power supply line 161 and the threshold voltage VTH_BG after change according to the control potential VCTL. -VTH_BG). In the writing period PWR, the potential VG of the gate G is lowered by the change amount k · ΔV and set to the level of the following equation (1a).
VG = VEL−VTH_BG−k · ΔV (1a)

Therefore, the drive current IDR supplied to the electro-optical element E in the drive period PDR is controlled to the current amount of the following equation (2a).
IDR = (β / 2) (VGS−VTH_BG) 2
= (Β / 2) (VEL−VG−VTH_BG) 2
= (Β / 2) (k · ΔV) 2 …… (2a)
In other words, the control potential VCTL is not reflected in the drive current IDR in contrast. In contrast, in the present embodiment, the supply of the control potential VCTL to the back gate B of the drive transistor TDR is stopped in the initialization period PRS, so that the drive current IDR can be reliably changed according to the control potential VCTL. It is.

<C: Modification>
Various modifications are added to the above embodiments. An example of a specific modification is as follows. Two or more aspects may be arbitrarily selected from the following examples and combined.

(1) Modification 1
In each of the above embodiments, one of the three kinds of potentials (VC, VH, VL) is selected as the control potential VCTL. However, the control mode of the control potential VCTL by the potential control circuit 38 is appropriately changed. For example, any one of two types of potentials or four or more types of potentials may be selected as the control potential VCTL. However, the change in the control potential VCTL need not be discrete. That is, a configuration in which the control potential VCTL continuously changes within a predetermined range is also suitable.

(2) Modification 2
In the above embodiment, the control potential VCTL is controlled according to the operation on the operation unit 44. However, the trigger for changing the control potential VCTL is not limited to an instruction from the user. For example, a configuration in which a measuring device (light meter) that measures the amount of light around the electro-optical device 100 is installed and the control potential VCTL is controlled according to the measured value is also suitable. For example, when the ambient light amount is small, the control circuit 42 selects the power saving mode (VCTL = VH), and when the ambient light amount is large, the control circuit 42 selects the high luminance mode (VCTL = VL). Condition. According to the above configuration, power consumption is reduced by displaying a low-brightness image in an environment where the amount of light is low, and image visibility is ensured by displaying a high-brightness image in an environment where the amount of light is sufficient. There is an advantage of being.

(3) Modification 3
The configuration of the unit circuit U is changed as appropriate. For example, in the electro-optical device 100 in which a plurality of unit circuits U are arranged in only one row (for example, an exposure apparatus employed in an electrophotographic image forming apparatus), an operation of selecting each unit circuit U in units of rows is unnecessary. Therefore, the switching element SW1 is omitted and the gate G of the driving transistor TDR is directly connected to the signal line 14. Further, when the light emission of the electro-optical element E during the writing period PWR is not a particular problem, the switching element SW2 is omitted (the driving current IDR is supplied to the electro-optical element E even during the writing period PWR). ) Is also adopted.

  The conductivity type of each transistor constituting the unit circuit U is arbitrary. For example, an N channel type thin film transistor is employed as the drive transistor TDR. In the N-channel type drive transistor TDR, the amount of drive current IDR with respect to the potential VG of the gate G increases as the potential VB of the back gate B increases. Therefore, in the power saving mode, the potential VL lower than the reference potential VC is supplied to each unit circuit U as the control potential VCTL, and in the high luminance mode, the potential VH higher than the reference potential VC is used as the control potential VCTL. To be supplied.

(4) Modification 4
In the second embodiment, the control potential VCTL is supplied to the back gate B of the drive transistor TDR every write period PWR (every frame), but the timing and cycle of supplying the control potential VCTL to the back gate B are changed as appropriate. Is done. For example, a configuration in which the control potential VCTL is supplied only during a predetermined number of writing periods PWR, a configuration in which the control potential VCTL is supplied immediately after the electro-optical device 100 is turned on, or a setting that is set regardless of the frame. A configuration in which the control potential VCTL is supplied every predetermined time is also suitable. In the configuration in which the control potential VCTL is held in the capacitive element C4 of the unit circuit U as shown in FIG. 6, the control potential VCTL is newly supplied before the voltage of the capacitive element C4 falls below a predetermined value due to charge leakage (capacitance). It is desirable to refresh the voltage of element C4).

(5) Modification 5
In the second embodiment, the switching element SW5 is installed in each unit circuit U. However, as shown in FIG. 8, a configuration in which one switching element SW5 is shared by a plurality of unit circuits U is also employed. The switching element SW5 in FIG. 8 is arranged corresponding to each row of the unit circuit U. The i-th row switching element SW5 is interposed between the back gate B of the driving transistor TDR and the potential supply line 18 in each of the n unit circuits U belonging to the i-th row. When the switching element SW5 in the i-th row is turned on, the control potential VCTL is supplied from the potential control circuit 38 to the back gates B of the n drive transistors TDR belonging to the i-th row. According to the above configuration, the configuration of each unit circuit U can be simplified. There is also an advantage that the potential supply line 18 does not need to be routed over all the unit circuits U.

(6) Modification 6
In each of the above embodiments, the potential VB of the back gate B of the drive transistor TDR is controlled. As a configuration for adjusting (correcting) the electrical characteristics of the drive transistor TDR, for example, a channel contact (body described below) A contact structure is also preferably employed.

  FIG. 9 is a plan view showing a configuration of a P-channel type drive transistor TDR adopting a channel contact structure. The drive transistor TDR has a semiconductor layer 25 formed on the surface of the substrate 20 (not shown in FIG. 9). A gate G is formed so as to face the semiconductor layer 25 with a gate insulating film (not shown) covering the semiconductor layer 25 interposed therebetween. In the semiconductor layer 25, a source region 25s, a drain region 25d, and a channel contact region 25c are formed after the gate G is formed. The source region 25s and the drain region 25d are regions into which P-type impurities are introduced. The channel contact region 25c is a region into which a P-type impurity having the same conductivity type as that of the channel of the driving transistor TDR is introduced.

  An interlayer insulating layer (not shown) is formed so as to cover the semiconductor layer 25 and the gate G. A plurality of through holes (H1, H2, H3) are formed in the interlayer insulating layer. A source S is connected to the source region 25s of the semiconductor layer 25 through a through hole H1, and a drain D is connected to the drain region 25d through a through hole H2. A channel electrode 26 is connected to the channel contact region 25c of the semiconductor layer 25 through a through hole H3.

  The configuration of the unit circuit U is the same as that of the above embodiments. The control potential VCTL is supplied to the channel electrode 26 of the driving transistor TDR directly (first embodiment) or indirectly via the switching element SW5 (second embodiment). The electrical characteristics of the drive transistor TDR (the relationship between the potential VG of the gate G and the amount of current of the drive current IDR) vary depending on the potential of the channel contact region 25c. Accordingly, even in the configuration employing the channel contact structure drive transistor TDR, the drive current IDR (the overall array of the element array section 10) of each electro-optic element E is controlled by appropriately controlling the control potential VCTL according to the operation mode. Brightness and power consumption in the element array section 10) can be changed.

  As described above, the characteristic control electrode (back gate B or channel electrode 26) for controlling the channel formed in the semiconductor layer according to the potential VG of the gate G is formed in the drive transistor TDR, and the variable control potential VCTL is formed. A configuration in which is supplied to the characteristic control electrode is preferably employed.

(7) Modification 7
The organic EL element is only an example of the electro-optical element E. For example, light-emitting elements such as inorganic EL elements and LED (Light Emitting Diode) elements are also used as the electro-optical element E. The electro-optical element E in each of the above embodiments is an element whose optical characteristics (luminance) are changed by supplying the drive current IDR.

<D: Application example>
Next, electronic equipment using the electro-optical device according to the invention will be described. FIGS. 10 to 12 show a form of an electronic apparatus that employs the electro-optical device 100 according to any one of the forms described above as a display device.

  FIG. 10 is a perspective view illustrating a configuration of a mobile personal computer that employs the electro-optical device 100. The personal computer 2000 includes an electro-optical device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed. Since the electro-optical device 100 uses an organic light-emitting diode element as the electro-optical element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 11 is a perspective view illustrating a configuration of a mobile phone to which the electro-optical device 100 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the electro-optical device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled.

  FIG. 12 is a perspective view illustrating a configuration of a personal digital assistant (PDA) to which the electro-optical device 100 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 that displays various images. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the electro-optical device 100.

  The electronic apparatus to which the electro-optical device according to the present invention is applied includes the digital still camera, the television, the video camera, the car navigation device, the pager, the electronic notebook, and the electronic paper in addition to the apparatuses illustrated in FIGS. Calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices with touch panels, and the like. The use of the electro-optical device according to the invention is not limited to image display. For example, the electro-optical device of the present invention is also used as an exposure device that forms a latent image on a photosensitive drum by exposure in an electrophotographic image forming device.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a circuit diagram which shows the structure of a unit circuit. It is sectional drawing which shows the structure of a drive transistor. It is a graph which shows the electrical property of a drive transistor. 6 is a timing chart for explaining the operation of the electro-optical device. It is a circuit diagram which shows the structure of the unit circuit in 2nd Embodiment of this invention. 6 is a timing chart for explaining the operation of the electro-optical device. It is a circuit diagram which shows the structure of the element array part which concerns on a modification. It is a top view which shows the structure of the drive transistor of a channel contact structure. It is a perspective view which shows the form (personal computer) of an electronic device. It is a perspective view which shows the form (cellular phone) of an electronic device. It is a perspective view which shows the form (mobile information terminal) of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Electro-optical apparatus, U ... Unit circuit, 10 ... Element array part, 12 ... Control line group, 12A, 12B, 12C ... Control line, 14 ... Signal line, 161 ... Power supply line, 162 ...... Ground line, 18 ... Potential supply line, 32 ... Control line drive circuit, 34 ... Signal supply circuit, 36 ... Power supply circuit, 38 ... Potential control circuit, 42 ... Control circuit, E ... Electricity Optical element, TDR... Drive transistor, SW1 to SW5... Switching element, C1 to C4... Capacitance element, GSL [i] (GSL [1] to GSL [m]) ... Selection signal, GDR [i] ( GDR [1] to GDR [m]) …… Control signal, GRS [i] (GRS [1] to GRS [m]) …… Initialization signal, D [j] (D [1] to D [n] ) ... Data signal, VCTL ... Control potential, IDR ... Drive current, PRS ... Initialization period, PWR ... Write period, PDR ... Drive period.

Claims (6)

  1. A drive transistor including a gate whose potential is set according to a data signal and a characteristic control electrode for controlling a channel formed according to the potential of the gate, and electro-optic driven by a drive current flowing through the drive transistor A plurality of unit circuits each including an element;
    An electro-optical device comprising: a potential control circuit that variably sets a control potential and supplies the control potential to the characteristic control electrode of each drive transistor in the plurality of unit circuits.
  2. The potential control circuit sets the control potential to a reference potential equal to the source potential of the driving transistor in the standard mode, sets the control potential higher than the reference potential in the first mode, and sets the control potential to the second mode. The electro-optical device according to claim 1, wherein the control potential is set lower than the reference potential.
  3. Each of the plurality of unit circuits is
    A first switching element that controls electrical connection between the characteristic control electrode and the potential control circuit;
    A second switching element that diode-connects the driving transistor in a first period;
    A capacitive element having a first electrode to which the data signal is supplied in a second period after the first period has elapsed and a second electrode connected to the gate of the driving transistor;
    The electro-optical device according to claim 1, wherein the first switching element is controlled to be in an off state in the first period and is controlled to be in an on state in the second period.
  4.   An electronic apparatus comprising the electro-optical device according to claim 1.
  5. A control method for an electro-optical device including a plurality of unit circuits each including an electro-optical element driven by a driving current flowing in a driving transistor,
    The drive transistor includes a gate whose potential is set according to a data signal, and a characteristic control electrode that controls a channel formed according to the potential of the gate,
    Set the control potential to variable,
    An electro-optical device control method for supplying the control potential to the characteristic control electrodes of the drive transistors in the plurality of unit circuits.
  6. Each of the plurality of unit circuits includes a capacitive element having a first electrode and a second electrode connected to a gate of the driving transistor,
    In the first period, the drive transistor is diode-connected and the supply of the control potential to the characteristic control electrode is stopped.
    The method of controlling the electro-optical device according to claim 5, wherein a data signal is supplied to the first electrode and the control potential is supplied to the characteristic control electrode in a second period after the elapse of the first period.
JP2007238887A 2007-09-14 2007-09-14 Electro-optical device, control method of electro-optical device, and electronic apparatus Active JP5045323B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007238887A JP5045323B2 (en) 2007-09-14 2007-09-14 Electro-optical device, control method of electro-optical device, and electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007238887A JP5045323B2 (en) 2007-09-14 2007-09-14 Electro-optical device, control method of electro-optical device, and electronic apparatus

Publications (2)

Publication Number Publication Date
JP2009069571A true JP2009069571A (en) 2009-04-02
JP5045323B2 JP5045323B2 (en) 2012-10-10

Family

ID=40605884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007238887A Active JP5045323B2 (en) 2007-09-14 2007-09-14 Electro-optical device, control method of electro-optical device, and electronic apparatus

Country Status (1)

Country Link
JP (1) JP5045323B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010060816A (en) * 2008-09-03 2010-03-18 Canon Inc Pixel circuit, light emitting display device, and method of driving them
CN102208166A (en) * 2010-03-29 2011-10-05 索尼公司 Display device and electronic device
CN102737581A (en) * 2012-05-31 2012-10-17 昆山工研院新型平板显示技术中心有限公司 Pixel driving circuit, pixel display unit and display circuit
CN102842281A (en) * 2011-06-22 2012-12-26 索尼公司 Pixel circuit, display device, electronic apparatus, and method of driving pixel circuit
KR20130008658A (en) 2010-04-05 2013-01-23 파나소닉 주식회사 Organic el display and controlling method thereof
KR20130008659A (en) 2010-04-05 2013-01-23 파나소닉 주식회사 Organic el display and controlling method thereof
JP2013076994A (en) * 2011-09-14 2013-04-25 Semiconductor Energy Lab Co Ltd Light-emitting device
JP5300730B2 (en) * 2007-09-28 2013-09-25 パナソニック株式会社 Display device
JP2015132816A (en) * 2013-12-12 2015-07-23 株式会社半導体エネルギー研究所 light-emitting device
JP2018128685A (en) * 2011-09-16 2018-08-16 株式会社半導体エネルギー研究所 Light-emitting device
JP2018151658A (en) * 2013-09-12 2018-09-27 ソニー株式会社 Display device and electronic apparatus
WO2019064487A1 (en) * 2017-09-29 2019-04-04 シャープ株式会社 Display device and driving method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000267597A (en) * 1999-03-16 2000-09-29 Casio Comput Co Ltd Display element and driving method therefor, and display device
JP2003173165A (en) * 2001-09-29 2003-06-20 Toshiba Corp Display device
JP2003224437A (en) * 2002-01-30 2003-08-08 Sanyo Electric Co Ltd Current drive circuit and display device equipped with the current drive circuit
JP2004133013A (en) * 2002-10-08 2004-04-30 Tohoku Pioneer Corp Driving-device for light emitting display panel
WO2006060519A2 (en) * 2004-12-03 2006-06-08 E.I. Dupont De Nemours And Company Circuits including switches for electronic devices and methods of using the electronic devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000267597A (en) * 1999-03-16 2000-09-29 Casio Comput Co Ltd Display element and driving method therefor, and display device
JP2003173165A (en) * 2001-09-29 2003-06-20 Toshiba Corp Display device
JP2003224437A (en) * 2002-01-30 2003-08-08 Sanyo Electric Co Ltd Current drive circuit and display device equipped with the current drive circuit
JP2004133013A (en) * 2002-10-08 2004-04-30 Tohoku Pioneer Corp Driving-device for light emitting display panel
WO2006060519A2 (en) * 2004-12-03 2006-06-08 E.I. Dupont De Nemours And Company Circuits including switches for electronic devices and methods of using the electronic devices

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8687024B2 (en) 2007-09-28 2014-04-01 Panasonic Corporation Pixel circuit and display apparatus
JP5300730B2 (en) * 2007-09-28 2013-09-25 パナソニック株式会社 Display device
JP2010060816A (en) * 2008-09-03 2010-03-18 Canon Inc Pixel circuit, light emitting display device, and method of driving them
US8659519B2 (en) 2008-09-03 2014-02-25 Canon Kabushiki Kaisha Pixel circuit with a writing period and a driving period, and driving method thereof
CN102208166A (en) * 2010-03-29 2011-10-05 索尼公司 Display device and electronic device
JP2011209434A (en) * 2010-03-29 2011-10-20 Sony Corp Display device and electronic device
KR20130008658A (en) 2010-04-05 2013-01-23 파나소닉 주식회사 Organic el display and controlling method thereof
KR20130008659A (en) 2010-04-05 2013-01-23 파나소닉 주식회사 Organic el display and controlling method thereof
US8405583B2 (en) 2010-04-05 2013-03-26 Panasonic Corporation Organic EL display device and control method thereof
US8791883B2 (en) 2010-04-05 2014-07-29 Panasonic Corporation Organic EL display device and control method thereof
CN102842281A (en) * 2011-06-22 2012-12-26 索尼公司 Pixel circuit, display device, electronic apparatus, and method of driving pixel circuit
JP2013003568A (en) * 2011-06-22 2013-01-07 Sony Corp Pixel circuit, display unit, electronic apparatus and pixel circuit driving method
JP2017123337A (en) * 2011-09-14 2017-07-13 株式会社半導体エネルギー研究所 Light-emitting device
JP2013076994A (en) * 2011-09-14 2013-04-25 Semiconductor Energy Lab Co Ltd Light-emitting device
JP2018156091A (en) * 2011-09-14 2018-10-04 株式会社半導体エネルギー研究所 Electronic apparatus
JP2018128685A (en) * 2011-09-16 2018-08-16 株式会社半導体エネルギー研究所 Light-emitting device
US10622380B2 (en) 2011-09-16 2020-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, light-emitting device, and electronic device
CN102737581A (en) * 2012-05-31 2012-10-17 昆山工研院新型平板显示技术中心有限公司 Pixel driving circuit, pixel display unit and display circuit
CN102737581B (en) * 2012-05-31 2015-07-08 昆山工研院新型平板显示技术中心有限公司 Pixel driving circuit, pixel display unit and display circuit
JP2018151658A (en) * 2013-09-12 2018-09-27 ソニー株式会社 Display device and electronic apparatus
US10103212B2 (en) 2013-09-12 2018-10-16 Sony Corporation Display device, method of manufacturing the same, and electronic apparatus
US10121841B2 (en) 2013-09-12 2018-11-06 Sony Corporation Display device, method of manufacturing the same, and electronic apparatus
US10312314B2 (en) 2013-09-12 2019-06-04 Sony Corporation Display device, method of manufacturing the same, and electronic apparatus
US10615238B2 (en) 2013-09-12 2020-04-07 Sony Corporation Display device, method of manufacturing the same, and electronic apparatus
US10615237B2 (en) 2013-09-12 2020-04-07 Sony Corporation Display device, method of manufacturing the same, and electronic apparatus
US10147779B2 (en) 2013-09-12 2018-12-04 Sony Corporation Display device, method of manufacturing the same, and electronic apparatus
JP2015132816A (en) * 2013-12-12 2015-07-23 株式会社半導体エネルギー研究所 light-emitting device
US10453873B2 (en) 2013-12-12 2019-10-22 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
WO2019064487A1 (en) * 2017-09-29 2019-04-04 シャープ株式会社 Display device and driving method thereof

Also Published As

Publication number Publication date
JP5045323B2 (en) 2012-10-10

Similar Documents

Publication Publication Date Title
US8907874B2 (en) Display apparatus
WO2018036169A1 (en) Pixel circuit, display panel, display device and driving method
US8072396B2 (en) Unit circuit, electro-optical device, and electronic apparatus
US7098705B2 (en) Electronic circuit, method of driving electronic circuit, electronic device, electro-optical device, method of driving electro-optical device, and electronic apparatus
US8982018B2 (en) EL display panel module, EL display panel, integrated circuit device, electronic apparatus and driving controlling method
US8917224B2 (en) Pixel unit circuit and OLED display apparatus
KR100799288B1 (en) Electronic circuit, electronic device, method of driving electronic device, electro-optical device, and electronic apparatus
KR100961627B1 (en) Display apparatus and driving method thereof
TWI389079B (en) Display device, method for driving the same, and electronic apparatus
US8072401B2 (en) Organic light emitting diode display and related pixel circuit
US7889160B2 (en) Organic light-emitting diode display device and driving method thereof
US7038392B2 (en) Active-matrix light emitting display and method for obtaining threshold voltage compensation for same
JP4600780B2 (en) Display device and driving method thereof
TWI457899B (en) Display device
US8643591B2 (en) Display device and driving method thereof
JP4483725B2 (en) Light emitting device, its drive circuit, and electronic device
JP5665256B2 (en) Luminescent display device
JP3986051B2 (en) Light emitting device, electronic equipment
US20140204067A1 (en) Pixel Circuits and Driving Schemes for Active Matrix Organic Light Emitting Diodes
US8593445B2 (en) Display apparatus, driving methods and electronic instruments
US8743032B2 (en) Display apparatus, driving method for display apparatus and electronic apparatus
US7755617B2 (en) Electronic circuit, method for driving the same, electronic device, and electronic apparatus
JP4752315B2 (en) Electronic circuit, driving method thereof, electro-optical device, and electronic apparatus
KR100736740B1 (en) Electronic device, method of driving the same, electro-optical device, and electronic apparatus
JP4186961B2 (en) Self-luminous device, driving method thereof, pixel circuit, and electronic device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100723

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120210

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120214

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120403

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120619

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120702

R150 Certificate of patent or registration of utility model

Ref document number: 5045323

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150727

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250