JP4536392B2 - Display device and driving method of display device - Google Patents

Description

  The present invention relates to a display device using a current drive element and a method for driving the display device. For example, a display device and a display such as an organic EL (Electro Luminescence) display and FED (Field Emission Display) using a current drive element. The present invention relates to a method for driving the apparatus.

  In recent years, research and development has been actively conducted on organic EL displays, FEDs, and the like as display devices using current-driven elements (current-driven light-emitting elements, electro-optical elements). In particular, organic EL displays are attracting attention as portable displays such as mobile phones and PDAs (Personal Digital Assistants) as displays capable of emitting light with low voltage and low power consumption.

  In the current driving element, the luminance at the time of light emission changes due to the current through the driving transistor that controls the current supply to the current driving element. For this reason, in the case of using a current driving element, it is necessary to control to compensate for characteristic variations of the driving transistor (threshold voltage of the driving transistor, variation in mobility, etc.).

  FIG. 17 shows an example of a circuit configuration for an organic EL display (see Patent Document 1).

  The pixel circuit 300 represents one pixel of the organic EL display. The pixel circuit 300 includes four p-type TFTs (Thin Film Transistors) (driving TFTs, switching TFTs) 360, 365, 370, and 375, two capacitors 350 and 355, and an organic EL (Organic Light Emitting Diode). ) 380.

  A driving TFT 365, a switching TFT 375, and an organic EL 380 are connected in series between the power supply line + VDD 390 and the common cathode (GND line). A capacitor Cc 350 and a switching TFT 360 are connected in series between the gate terminal of the driving TFT 365 and the data line 310. A switching TFT 370 is connected between the gate terminal and the drain terminal of the driving TFT 365. A capacitor Cs 355 is connected between the gate terminal and the source terminal of the driving TFT 365. A select line 320, an auto zero line 330, and an illumination line 340 are connected to gate terminals of the switching TFTs 360, 370, and 375, respectively.

  In the pixel circuit 300, writing for driving is performed as follows.

  First, in the first period, the auto zero line 330 and the illumination line 340 are set to Low. As a result, the TFT 370 and the TFT 375 are turned on, and the drain terminal potential and the gate terminal potential of the driving TFT 365 become equal.

  Further, the select line 320 is set to Low and the reference voltage is input to the data line 310. As a result, the other terminal (the terminal on the data line 310 via the TFT 360) of the capacitor Cc350 is set as the reference voltage.

  At this time, a current flows from the driving TFT 365 toward the organic EL 380, and the gate potential of the driving TFT 365 becomes a potential at which the driving TFT 365 is turned on.

  Next, in the second period, the illumination line 340 is set high and the TFT 375 is turned off. As a result, the current of the power supply line + VDD 390 wraps around the gate of the driving TFT 365 and pushes up the value of Vgs. When the gate potential of the driving TFT 365 gradually increases and reaches a value (+ VDD−Vth) corresponding to the threshold voltage (−Vth) of the driving TFT 365, that is, when Vgs = Vth, the driving TFT 365 is Turns off.

  In the next third period, the auto zero line 330 is set to High. As a result, the switching TFT 370 is turned off. Therefore, the difference between the gate potential of the driving TFT 365 and the reference potential of the data line 310 is stored in the capacitor Cc350.

  That is, the gate potential of the driving TFT 365 is a value (+ VDD−Vth) corresponding to the threshold voltage (−Vth) when the potential of the data line 310 is the reference potential. Since this state is stored in the capacitor 350, if the potential of the data line 310 changes from the reference potential, a potential corresponding to the change is applied to the gate terminal of the driving TFT 365. That is, regardless of the threshold potential of the driving TFT 365, the potential compensated for the threshold voltage can be applied from the data line 310 to the gate terminal of the driving TFT 365.

  Thereafter, the select line is set to High, the gate terminal potential of the driving TFT 365 is maintained, and the pixel selection period ends.

  As described above, when the pixel circuit 300 shown in FIG. 17 is used, a variation in threshold potential of the driving TFT 365 is compensated, and a potential (desired potential-threshold potential) obtained by compensating the threshold potential is applied to the gate terminal of the driving TFT 365. Can be given. However, this pixel circuit cannot compensate for variations in mobility of the driving TFT 365.

  Therefore, an example of a pixel circuit configured to guarantee variation in mobility of the driving TFT is also known (see Non-Patent Document 1). Non-Patent Document 2 and Patent Document 2 show display devices using such pixel circuits. In these configurations, a drive current corresponding to the gradation is generated on the drive circuit side and supplied to the pixels. As a result, a potential that compensates for variations in threshold voltage and mobility of the driving TFT is applied to the gate terminal of the driving TFT.

Note that a low-temperature polysilicon TFT, a CG (Continuous Grain) silicon TFT (see Non-Patent Documents 3 and 4), or the like is used as a switching element in the pixel circuit. A detailed configuration of the organic EL element is disclosed in Non-Patent Document 5.
Special Table 2002-514320 Publication (International Publication Date: October 29, 1998) JP 2003-195812 A (publication date: July 9, 2003) “Active Matrix PolyLED Displays”, IDW'00, pp235-238. “A Poly-Si TFT 6-bit Current Data Driver for Active Matrix Organic Light Emitting Diode Displays”, EURODISPLAY, 2002, pp279-282. “4.0-in. TFT-OLED Displays and a Novel Digital Driving Method”, SID'00 Digest, pp.924-927, Semiconductor Energy Laboratory. “Continuous Grain Silicon Technology and Its Applications for Active Matrix Display”, AM-LCD 2000, pp.25-28, Semiconductor Energy Laboratory. “Polymer Light-Emitting Diodes for use in Flat Panel Display”, AM-LCD 2001, pp.211-214, Semiconductor Energy Laboratory.

  However, the above-described prior art described in Patent Document 1 has a problem in that variation in the value of current flowing through the driving TFT cannot be reduced because variation in mobility of the driving TFT cannot be compensated.

  On the other hand, in the prior art described in Patent Document 2 described above, for example, an analog current output circuit is provided in a drive circuit (source driver circuit) that generates a drive current, although variation in the current value flowing through the drive TFT can be reduced. However, there is a problem that the circuit scale of the drive circuit cannot be reduced. In addition, when supplying current from the driver circuit, it is necessary to charge the stray capacitance existing in the wiring for supplying current from the driver circuit to the pixel until the driving TFT is in a state of supplying a desired current. There is also a problem in that the period of time, that is, the selection period per pixel cannot be shortened.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a display in which variation in the current value flowing through the driving TFT is reduced without increasing the circuit scale of the driving circuit that supplies current to the pixel. An object of the present invention is to provide a device and a display device driving method.

In order to solve the above problems, a display device according to the present invention provides
A current driven element, a display device arranged a driving transistor for controlling the current, the pixel circuit arranged and light-emission control switching transistor in series in a matrix of the sheet subjected to the current driven element, the driven end A holding means for holding the potential difference between the two ends by connecting the other end to the input terminal of the input video signal via a signal switching switching element to the control terminal of the driving transistor, and the control terminal and the output terminal of the driving transistor And a current adjustment switching element arranged between the other end of the holding means and the output terminal of the driving transistor, and the signal switching switching in the first period The device and the potential control switching device are turned on, the light emission control switching transistor is turned off, and The other end of the holding means giving the potential of the input video signal, the signal switching the switching element and the potential control switching element in the second period is turned off, and the current adjustment switching elements turned on, it converts the voltage into a current the output terminal of the driving transistor connected to the reference potential via a voltage-current converting means for, by connecting to Rukoto the other end of the holding means, a current flowing through the driving transistor, for the drive It is characterized by being set by the voltage difference between the potential of the output terminal of the transistor and the reference potential .

  The current driving element (current driving light emitting element, electro-optical element) is, for example, an organic EL (OLED (Organic Light Emitting Diode)). Examples of the display device using the current driving element include an organic EL (Electro Luminescence) display and an FED (Field Emission Display).

  The driving transistor includes a control terminal to which a control input for controlling a supply current is input, an input terminal to which a current to be supplied is input, and an output terminal to supply a current to the current driving element. . For example, when a TFT is used as a transistor, the control terminal is a gate, the input terminal is a source, and the output terminal is a drain.

  The display device has a configuration in which pixel circuits each having a holding unit and an adjusting unit are arranged in a matrix in addition to a current driving element and a driving transistor.

  The holding means is a capacity for storing electric charge, and is realized by, for example, a capacitor (holding capacitor).

  A potential at which the driving transistor is just turned on can be set at the one end of the holding means. Here, setting a potential means writing a potential (voltage). Further, a potential control switching element that connects the control terminal and the output terminal of the driving transistor is arranged, and the potential control switching element is turned on. With this configuration, if no current is output from the output terminal of the driving transistor and a current is passed from the input terminal to the output terminal of the driving transistor, the driving transistor is just turned on at one end of the holding means. Potential can be set.

  A desired potential supplied from a supply wiring (signal wiring) having a desired potential is set on the other end side of the holding unit.

  In this state, the adjusting means connects the other end of the holding means to the output terminal of the driving transistor, and sets the potential of the output terminal to the desired potential. The adjusting means can be realized by a current adjusting switching element that turns on and off the connection between the other end of the holding means and the output terminal of the driving transistor.

  Here, the output terminal of the driving transistor is connected to a reference potential via voltage-current conversion means for converting a voltage into a current. The voltage-current conversion means is, for example, a resistor. This voltage / current conversion means may be provided inside the pixel circuit or outside the pixel circuit.

  Therefore, since the drain terminal set to the desired potential by the adjusting means is connected to the reference potential via the voltage / current converting means, the voltage / current converting means is used to respond to the potential difference between the desired potential and the reference potential. A predetermined current can be passed.

  Here, as described above, the one end side of the holding means holds the potential in a state in which the driving transistor is just turned on. For this reason, the above-described predetermined current flows through the driving transistor. In addition, when a current is subsequently passed through the driving transistor, a desired potential is applied to the storage capacitor or holding means in which one end is connected to the input terminal of the driving transistor and the other end is connected to the control terminal of the driving transistor. Therefore, the same current as described above can be supplied.

  Therefore, by using the holding unit and the adjusting unit, a predetermined current can be supplied to the current driving element via the driving transistor. As a result, variations in threshold voltage and mobility of the driving transistor can be compensated.

  Further, since a constant current circuit for creating a constant current is not required on the supply circuit (drive circuit) side that supplies current to the driving transistor, the circuit scale of the supply circuit is not increased.

  Further, in the above configuration, the path (second path) through which the current flows from the output terminal of the driving transistor to the reference potential via the voltage-current conversion unit is a supply wiring in which a desired potential is set at the other end of the holding unit It may be different from the route (first route) from or may be the same.

  If the paths are different, for example, the holding means of a certain pixel circuit causes a current to flow from the output terminal via the second path, and a desired potential is set from the first path to the holding means of another pixel circuit during that time. Can do. Thereby, the selection period per pixel can be shortened.

  In the above configuration, the holding unit may further include a signal switching switching element that switches on and off the connection between the supply wiring and the control terminal of the driving transistor. For example, the supply wiring is connected to the control terminal of the driving transistor through the signal switching switching element connected in series and the capacity of the holding means. With this configuration, by turning on only the signal switching element of the desired pixel circuit, it is possible to reliably set the desired potential only to the holding means of the desired pixel circuit. Therefore, the selection period per pixel can be reliably shortened.

  The first configuration of the display device according to the present invention is characterized in that, in the above configuration, a resistor connected from the output terminal of the driving transistor through a wiring is used as the voltage-current conversion means.

  Since a resistor other than the current driving element is used, the temperature dependency of the current flowing through the resistor can be suppressed. This resistor may be provided in the pixel circuit or in a supply circuit that supplies current to the pixel circuit.

  A second configuration of the display device according to the present invention is characterized in that, in the above configuration, the current driving element is used as the voltage-current conversion means.

  In this configuration, one end of the current driving element is connected to the driving transistor, and a reference potential is set to the other end which is a common electrode.

  This configuration eliminates the need for a resistor other than the current drive element and a current control switching element that switches on / off of the connection to the resistor, and therefore the scale of the pixel circuit and the scale of the supply circuit that supplies current to the pixel circuit Can be reduced.

  The display device according to the present invention is characterized in that, in the above configuration, the voltage-current conversion means is provided in a supply circuit that is provided outside the pixel circuit and supplies current to the pixel circuit.

  With this configuration, the pixel circuit does not require a resistor other than the current driving element and a current control switching element for switching on / off of the connection to the resistor, so that the scale of the pixel circuit is not increased.

  A preferred configuration of a display device according to the present invention is characterized in that in the above configuration, a light emission control switching element for switching on and off the connection between the driving transistor and the current driving element is provided.

  With this configuration, the current supply from the driving transistor to the current driving element can be turned on / off, so that the current can be supplied to the current driving element only when necessary.

  A preferred configuration of the display device according to the present invention is characterized in that, in the above configuration, the display device includes a current control switching element for switching on and off the connection between the output terminal of the driving transistor and the voltage-current conversion means.

  With this configuration, the timing of current adjustment using the voltage-current converter can be controlled using the current control switching element. The current control switching element may be provided in the pixel circuit or in a supply circuit that supplies current to the pixel circuit.

  In a preferred configuration of the display device according to the present invention, in the above configuration, a storage capacitor disposed between the input terminal of the driving transistor and the control terminal, the control terminal and the output terminal of the driving transistor, The pixel circuit includes a potential control switching element disposed between the signal line and a signal switching switching element connected in series with the holding means between the supply wiring and the control terminal of the driving transistor. It is characterized by having.

  If it is the said structure, using a maintenance capacitor | condenser and an electric potential control switching element, an electric current will be sent from the input terminal of a drive transistor to an output terminal, and the electric potential which will be in the state which a drive transistor will just turn on to one end of a holding means. Can be set. Further, the potential of the holding means can be maintained using the signal switching switching element.

The display device driving method according to the present invention is the display device driving method according to claim 1, wherein the control of the driving transistor is performed from the supply wiring via the holding means. Connecting to the terminal, connecting the control terminal and the output terminal of the driving transistor, and opening the connection from the supply wiring to the control terminal of the driving transistor through the holding means , The connection between the control terminal and the output terminal of the driving transistor is released, the terminal on the supply wiring side of the holding means and the output terminal of the driving transistor are connected, and the output of the driving transistor By connecting a terminal to a reference potential via the voltage-current converter, the current flowing through the driving transistor is It is characterized in that it includes a step of setting the voltage difference between the potential and the reference potential of the output terminal of the transistor.

  In the above method, first, the supply wiring is connected to the control terminal of the driving transistor through the holding capacitor, and the control terminal and the output terminal of the driving transistor are connected.

  By this step, the potential at which the driving transistor is just turned on can be set at the terminal of the holding capacitor on the driving transistor side.

  Next, the portion connected in the above step is opened, and the terminal on the supply wiring side of the holding capacitor and the output terminal of the driving transistor are connected.

  Here, it is further assumed that the output terminal of the driving transistor is connected to a predetermined reference potential via a predetermined voltage-current converter. As a result, a current corresponding to the potential difference between the potential set at the terminal on the supply wiring side of the holding capacitor and the reference potential can be passed through the voltage-current conversion means.

  Therefore, a predetermined current can be supplied to the current driving element via the driving transistor. As a result, variations in threshold voltage and mobility of the driving transistor can be compensated.

Display device according to the present invention, as described above, a current driven element, the current and the driving transistor for controlling a current to be provided feed to the drive element, a matrix of pixel circuits arranged and light-emission control switching transistor in series The display device is arranged at the one end, and one end is connected to the control terminal of the driving transistor and the other end is connected to the potential supply wiring of the input video signal through the signal switching switching element to hold the potential difference between both ends. Means, a potential control switching element disposed between the control terminal and the output terminal of the driving transistor, and a current adjustment switching disposed between the other end of the holding means and the output terminal of the driving transistor. And the signal switching switching element and the potential control switching element are turned on in the first period, and the light emission control switch is turned on. The switching transistor is turned off, the potential of the input video signal is applied to the other end of the holding means, the signal switching switching element and the potential control switching element are turned off in the second period, and the current adjustment switching element is turned on. a state, the output terminal of the driving transistor connected to the reference potential via a voltage-current converting means for converting the voltage into a current, by connecting to Rukoto the other end of the holding means, the driving transistor Is set by the voltage difference between the potential of the output terminal of the driving transistor and the reference potential .

  The holding unit can hold a potential corresponding to the variation of the driving transistor, and the adjustment unit can adjust the current flowing through the driving transistor, so that the current is supplied to the pixel circuit. A current circuit becomes unnecessary, and variations due to driving transistors can be compensated without increasing the circuit scale.

  The embodiment of the present invention will be described with reference to FIGS. 1 to 16 as follows.

  In the display device of the present invention, a low-temperature polysilicon TFT (Thin Film Transistor), a CG (Continuous Grain) silicon TFT, or the like is used as a switching element. In the embodiment described below, the switching element is a CG silicon TFT. As a configuration of the CG silicon TFT, for example, the one disclosed in Non-Patent Document 3 can be used, and as the manufacturing process of the CG silicon TFT, for example, the one disclosed in Non-Patent Document 4 can be used.

  In the following embodiments, an organic EL is used as a current driving element (current driving light emitting element, electro-optical element). As the configuration of the organic EL, for example, one disclosed in Non-Patent Document 5 can be used.

[Embodiment 1]
The display device 1 according to the present embodiment includes a plurality of pixel circuits Aij, a source driver circuit 2, and a gate driver circuit 3, as shown in FIG. The source driver circuit 2 and the gate driver circuit 3 are drive circuits for driving the pixel circuit.

  The pixel circuit Aij includes an organic EL element (current driving element) and a driving TFT (driving transistor) not shown. Here, assuming that n and m are integers, the above i means 1 to n, and j means 1 to m. In the following, a case corresponding to m = 6 will be described, but the present invention is not limited to this.

  Pixel circuits Aij are arranged in a matrix. In each pixel circuit Aij, display is performed under the control of a driving TFT that controls a current supplied to the organic EL element.

  The source driver circuit 2 supplies a signal voltage to the organic EL element of the pixel circuit Aij via the source wiring (supply wiring, signal wiring) Sj. The gate driver circuit 3 selects a driving TFT that supplies a desired potential (voltage) via the gate wiring Gi.

  The source driver circuit 2 includes one shift register 4 and a plurality of drive circuits (supply circuits) 5.

  The shift register 4 has an m-bit configuration. A start pulse SP is input from a control circuit (not shown) to the top register of the m-bit shift register 4. The shift register 4 transfers the start pulse SP with the clock clk in the shift register 4. Further, the shift register 4 outputs the same pulse to be transferred to each drive circuit 5 as a timing pulse PGj.

  The drive circuit 5 receives a timing pulse PGj and an analog voltage signal input signal Da output from a control circuit (not shown).

  The gate driver circuit 3 includes a shift register that transfers an input signal YI with a shift clock GP. The gate driver circuit 3 outputs a predetermined voltage to the gate wiring Gi and control wirings Ri, Ci, Wi (not shown) at a predetermined timing controlled by the shift register.

  In addition, control signals are input from a control circuit (not shown) to the gate driver circuit 2 and the source driver circuit 3, but detailed description thereof is omitted here.

  Next, the configuration of the drive circuit 5 and each pixel circuit Aij will be described with reference to FIG.

  More specifically, in addition to the analog signal voltage Da and the timing pulse PGj, a voltage wiring Vc and a control wiring Pc are connected to the drive circuit 5.

  The drive circuit 5 includes switching TFTs 15 and 16. A control wiring Pc is connected to the gate of the switching TFT 15. The switching TFT 15 switches the connection between the voltage wiring Vc and the source wiring Sj on and off according to the input to the control wiring Pc. The wiring of the timing pulse PGj is connected to the gate of the switching TFT 16. The switching TFT 16 switches on / off the connection between the input video signal wiring Da and the source wiring Sj according to the timing pulse PGj.

  Each pixel circuit Aij is disposed in the vicinity where the source line Sj and the gate line Gi intersect. In addition to the control wirings Ri, Wi, and Ci supplied from the gate driver, power supply wirings Vp and Vr are connected to the pixel circuit Aij from a power supply circuit (not shown).

  The pixel circuit Aij includes an organic EL (organic EL element) 20 and a driving TFT 6. The driving TFT 6 includes a gate terminal (control terminal, current control terminal), a source terminal (input terminal, reference potential terminal), and a drain terminal (output terminal, current input / output terminal). One end of the organic EL 20 is connected to the drain terminal of the driving TFT 6, and the other end of the organic EL is connected to the common wiring Vcom.

  The pixel circuit Aij includes, as switching TFTs, an n-type TFT (signal switching switching element) 8, TFT (potential control switching element) 9, TFT (adjusting means, current adjusting switching element) 10, p-type TFT ( A light emission control switching element) 7 and a TFT (current control switching element) 11. The pixel circuit Aij includes a capacitor (sustain capacitor) 12, a capacitor (holding means, holding capacitor) 13, and a resistor (voltage-current conversion means) 14.

  The driving TFT 6, TFT 7, and organic EL 20 are connected in series between the power supply wiring Vp and the common wiring Vcom.

  A TFT 8 and a capacitor 13 are connected in series between the source line Sj and the gate terminal of the driving TFT 6. Thus, one terminal of the capacitor 13 is connected to the gate terminal of the driving TFT 6, and the other terminal of the capacitor 13 is connected to the drain of the TFT 8.

  A capacitor 12 is connected between the gate terminal and the source terminal of the driving TFT 6. A switching TFT 9 is connected between the gate terminal and the drain terminal of the driving TFT 6. The TFT 10 is provided so as to connect the other terminal of the capacitor 13 to the drain of the driving TFT 6. The TFT 11 and the resistor 14 are connected in series between the drain terminal of the driving TFT 6 and the power supply wiring Vr.

  A control wiring Ri, a gate wiring Gi, a gate wiring Gi, a control wiring Ci, and a control wiring Wi are connected to the gate terminals of the TFTs 7, 8, 9, 10, and 11, respectively.

  The operations in the pixel circuit Aij of the display device 1 are as follows. The control wiring Pc, the input video signal wiring Da, the control wiring PGj (PG1, PGm), the source wiring Sj (S1, Sm), the gate wiring Gi, and the control wiring shown in FIG. This will be described below using operation timings of Ri, Wi, and Ci.

  As described below, the operation in the pixel circuit includes a period for setting the gate potential of the driving transistor (first period) and a period for setting the current flowing through the driving transistor with the gate potential set (second period). ), And then includes a period (third period) in which a current is supplied to the organic EL element via the driving transistor.

  In this embodiment, as described below, a period from time 0 to 12t1 is set as a selection period of the pixel circuit Aij. Among these, the time t1 to 11t1 in which the potential of the gate wiring Gi is High is defined as a first period.

  Note that, from time 0 to 24t1, the potential of the control wiring Ri is set to High (GH), and the switching TFT 7 is turned off. Then, the TFT 7 is turned on, and current is supplied to the organic EL 20 in the third period. Further, the current flowing through the driving TFT 6 is set until the TFT 7 is turned on after the TFT 8 is turned off (second period). In this way, the selection period per pixel can be shortened.

  First, between time 0 and t1, the potential of the control wiring Pc is set to High (GH), the switching TFT 15 is turned on, and a voltage is supplied from the voltage wiring Vc to the source wiring Sj. The potential of the voltage wiring Vc is set to a value larger than the potential Vda of the input video signal Da. This is because when the input video signal potential Vda is subsequently input to the source wiring, the driving TFT 6 is once turned on.

  Next, the operation in the period from time t1 to 11t1 will be described as the first period.

  First, during a period of time t1 to 2t1, the potential of the control wiring Wi is set to Low (GL), and the switching TFT 11 is turned on. As a result, the drain terminal of the driving TFT 6 and one terminal of the resistor 14 are connected, and a current flows from the power supply wiring Vp toward the power supply wiring Vr via the driving TFT 6, the switching TFT 11, and the resistance 14. As a result, the gate terminal potential of the driving TFT 6 is adjusted so that a current flows through the driving TFT 6. At time 2t1, the potential of the control wiring Wi is set to High (GH), and the switching TFT 11 is turned off.

  Further, the switching TFT 16 of the driving circuit 5 corresponding to each source wiring Sj is set with the potential of the control wiring PGj (j = 1 to m, m = 6) being set to High (GH) sequentially from time 2t1 to time 8t1. Is turned on every t1 hours. As a result, the potential Vda of the input video signal Da corresponding to the pixel Aij is input and held in the source line Sj (j = 1 to m).

  Further, in the first period of time t1 to 11t1, the potential of the gate wiring Gi is set to High, and the switching TFTs 8 and 9 are turned on.

  As a result, the switching TFT 8 connects the other terminal of the capacitor 13 to the source wiring Sj. Thereby, the other terminal of the capacitor 13 is set to the potential of the source line Sj. The potential in this case is a potential Vda supplied from the signal wiring Da to the source wiring Sj, as will be described later.

  Further, the gate terminal and the drain terminal of the driving TFT 6 are connected by the switching TFT 9. Here, the driving TFT 6 is set so that a current flows between the source and the drain. For this reason, the gate and drain terminal potentials rise with the current supplied from the source terminal. Since the potential rise continues until the driving TFT 6 is turned off, the gate-source terminal potential of the driving TFT 6 becomes the threshold voltage (Vth) of the driving TFT 6.

  Note that, during the period, the charge at both ends of the capacitor 13 changes in accordance with the change in the gate terminal potential of the driving TFT 6. However, the stray capacitance C is connected to the other terminal of the capacitor 13 through the source line Sj, and the stray capacitance C> the capacitance of the capacitor 13. For this reason, the potential of the other terminal of the capacitor 13 hardly changes.

  As described above, one end of the capacitor 13 is connected to the gate terminal of the driving TFT 6 and the other end is connected to the source line Sj to hold the potential difference between both ends. If the potential difference is stored in the capacitor 13 by the above writing with the gate wiring Gi set to Low (GL), even when the potential on the other end changes, the potential corresponding to the change is applied to the gate terminal of the driving TFT 6. Applied.

  Next, a non-selection period of the pixel circuit Aij after the time 12t1 will be described. According to the configuration of the pixel circuit Aij of the present embodiment, the current flowing through the driving TFT 6 can be adjusted and an appropriate current can be supplied to the organic EL 20 during this non-selection period.

  First, time 13t1 to 23t1 is set as the second period. During this period, the current flowing through the driving TFT 6 is adjusted.

  The potential of the control wiring Wi is set to Low (GL), and the switching TFT 11 is turned on. The drain terminal of the driving TFT 6 is connected to one terminal of the resistor 14 by the switching TFT 11. The other terminal of the resistor 14 is connected to the power supply wiring Vr. For this reason, the drain terminal of the driving TFT 6 is connected to the power supply wiring Vr as the reference potential via the resistor 14 as voltage-current conversion means for converting voltage into current.

  Further, the potential of the control wiring Ci is set to High (GH), and the switching TFT 10 is turned on. The other terminal of the capacitor 13 is connected to the drain terminal of the driving TFT 6 by the switching TFT 10. That is, the potential of the drain terminal of the driving TFT 6 is set to the same potential as the other terminal of the capacitor 13. When the potential of the drain terminal of the driving TFT 6 is set in this way, the current flowing through the driving TFT 6 can be adjusted as follows.

  That is, since the other terminal of the capacitor 13 and the drain terminal of the driving TFT 6 are connected, and the drain terminal of the driving TFT 6 and the resistor 14 are connected, the drain terminal potential of the driving TFT 6 is the other terminal of the capacitor 13. Becomes the value Vda ′ close to the potential Vda of the input video signal Da given earlier. The pixel circuit Aij is stabilized because the current flowing through the resistor 14 and the current flowing through the driving TFT 6 become equal. Therefore, the current Ids flowing through the driving TFT 6 is Ids≈ (Vda′−Vr) / R.

  Note that the gate potential of the driving TFT 6 is set to the threshold potential when the other terminal (TFT 8 side) of the capacitor 13 is at the potential Vda. Therefore, when the other terminal of the capacitor 13 is connected to the drain terminal of the driving TFT 6, if the drain terminal potential of the driving TFT 6 is Vda = 0, the current Ids flowing through the driving TFT 6 becomes zero. This state is a reference, and if Vda becomes larger than that, Ids becomes 0 or more. If Vda is smaller than the power supply wiring Vp, the current is determined by the above relational expression (Ids≈ (Vda′−Vr) / R). Therefore, the potential of the power supply wiring Vp is hardly related to the current flowing through the driving TFT 6. . More precisely, it is somewhat related, but it is unclear how much it is related.

  When the potential of the control wiring Ci is set to Low (GL) at time 23t1 and the switching TFT 10 is turned off, a potential corresponding to the current value Ids is held at the gate terminal of the driving TFT 6. Thus, since the driving TFT 6 is adjusted to the gate voltage having a predetermined current value, the adjusted current value Ids can be obtained by subsequently turning on the TFT 7.

More specifically, the current Ids can be obtained as long as the driving TFT 6 holds the gate voltage and the current flowing through the driving TFT 6 satisfies the condition Vds> Vgs−Vth. For example, when the current value of the driving TFT 6 is calculated by using an FET model, Ids = μwk (Vgs−Vth) ² when Vds> Vgs−Vth from the formula of the current flowing through the FET. Where μ is the mobility, w is the TFT gate width, and k is the proportionality constant.

  Here, the current Ids was flowing through the driving TFT 6 until just before the time 23t1. By turning off the TFT 10, the gate potential at that time is held using the capacitors 12 and 13. As described above, if the gate potential is maintained while a certain current Ids is flowing, the current flowing through the driving TFT 6 is maintained under the condition of Vds> Vgs−Vth.

  Since the current flowing through the TFT is set using Ids≈ (Vda′−Vr) / R so that the influence of the TFT mobility is automatically canceled, the TFT mobility, threshold value are thereafter set. A current value that is close to the current value can be obtained. (Actually speaking, there is a slight influence of Vds. Strictly speaking, assuming that the applied voltage to the organic EL is Vak when a desired current flows through the organic EL, Vp> Vgs. It is necessary to set −Vth + Vak. Preferably, Vp> 1V + Vak is set in consideration of the Vds-Ids characteristics under the constant gate voltage of the FET. This is because from Vp−Vak = Vds, Vds> Vgs−Vth and Vds = 0.1 V may not work very well. Thereby, a current is supplied to the organic EL 20 via the TFT 6.

  As described above, in the first period and the second period, the current is set for the pixel circuit Aij, and then the set current is supplied to the organic EL. Specifically, at time 24t1, the potential of the control wiring Ri is set low, the switching TFT 7 is turned on, and the current value Ids determined regardless of the mobility of the driving TFT 6 is directed from the driving TFT 6 to the organic EL 20 Shed.

  Note that the first period of the next pixel circuit A (i + 1) j starts after 12t1 period of the first period of Aij. This is due to the following reason. As in the pixel circuit Aij of this embodiment, when the voltage / current converter (resistor 14) is arranged other than the source line Sj as shown in FIG. 1, it is not necessary to use the source line Sj in the second period. For this reason, if only the first period elapses, the current setting of the next gate wiring G (i + 1) can be started using the source wiring Sj.

  With respect to the operation of the pixel circuit Aij described above, simulation results are shown in FIGS. 4A to 4C (hereinafter, the entirety of FIGS. 4A to 4C is simply referred to as FIG. 4). . 4A and 4B show the driving operation in the display device 1, and FIG. 4C shows the gate potential N1 of the driving TFT 6 in accordance with the operation shown in FIGS. 4A and 4B. The simulation result of the change in the drain potential N2 and the current Ids flowing between the source and drain of the driving TFT 6 is shown. Note that the gate potentials N1 (1) to N1 (5), the drain potentials N2 (1) to N2 (5), and the current Ids (1) flowing between the source and drain terminals of the driving TFT 6 shown in FIG. ) To Isd (5) are obtained using the threshold voltage / mobility characteristics of the driving TFT 6 shown in Table 1 below.

  Here, the time 0 to t1 corresponds to the time 2.304 to 2.308 ms shown in FIG. Also, the time t1 to 11t1 that is the first period corresponds to the time 2.308 to 2.364 ms shown in FIG.

  Among these, a current flows from the driving TFT 6 toward the resistor 14 during the time 2.308 to 2.312 ms shown in FIG. 4 corresponding to the time t1 to 2t1. Thereafter, the gate potential N1 of the driving TFT 6 becomes the threshold potential of the driving TFT 6 under the above conditions. Note that N1 = N2 during this period, and they are overlapped in the figure. Further, since the capacitances of the capacitors 12 and 13 are set to about 1 pF each, the current flowing through the driving TFT 6 becomes constant at several μs. The stray capacitance C of the source wiring Sj is 10 pF.

  Then, the first period ends at time 2.364 ms in FIG. 4 corresponding to time 11 t 1, and the second period starts at time 2.372 ms corresponding to time 13 t 1. Thereafter, the second period ends at time 2.424 ms of FIG. 4 corresponding to time 23 t 1, and the gate potential of the driving TFT 6 at this time is held in the capacitors 13 and 12.

  As shown in FIG. 4, the gate potential of the driving TFT 6 changes with the change of the potential of the control wiring Ci from High to Low at time 2.424 ms, and the current Ids flowing through the driving TFT is slightly changed. It has changed. On the other hand, since the anode voltage of the organic EL 20 returns from a low state to a high state in the third period, a capacitance is generated between the gate terminal of the driving TFT 6 or the other terminal of the capacitor 13 and the anode of the organic EL 20, thereby A change in the gate potential of the TFT 6 can also be compensated.

  FIG. 5 shows the result of simulating the current Ids flowing through the driving TFT 6 while changing the potential of the input video signal Da under the same conditions as described above.

  As shown in FIG. 5, according to the display device 1 having the pixel circuit Aij and the drive circuit 5, in a relatively small current region (Ids ≦ 0.5 μA), the result does not depend on the characteristic variation of the drive TFT 6. Obtainable.

  As described above, according to the display device 1, the variation in the value of the current flowing through the driving TFT 6 can be reduced.

  Further, as shown in the display device 1 in FIG. 2 and the drive circuit 5 in FIG. 1, the source driver circuit 2 can be configured with a relatively simple circuit configuration. That is, in the display device 1, the source driver circuit 2 disposed between the control circuit (control IC) and the source line Sj disposes a switching transistor for each source line Sj, and the timing corresponding to the input video signal. Thus, the video signal may be output to the source wiring Sj. Therefore, the scale of the source driver circuit 2 can be reduced, and the frame on the lower side of the panel can be narrowed. Further, it is possible to suppress a decrease in yield and to prevent a decrease in the number of panels that can be taken per sheet, thereby preventing an increase in cost per panel.

  Further, according to the display device 1, it is possible to display with a sufficient selection time secured. In the following, this point will be described with a specific estimate.

  As described above, the pixel circuit Aij of the display device 1 applies the desired potential Vda to the other terminal of the capacitor 13 in the first period, and determines the output current value of the driving TFT 6 in the second period of the non-selection period. Can do.

  In this way, as an external signal source outside the pixel circuit Aij, for example, a desired potential Vda corresponding to the video signal to be displayed is output from the drive circuit 5 including the control IC, and the capacitor 13 of the pixel circuit Aij. By giving to the other terminal, a current value to be given to each electro-optical element (current driving element) can be determined. For example, when a voltage is applied from the outside to the CR series circuit, the time required to reach a predetermined potential can be shortened according to the time constant.

Here, it is assumed that the resistance R from the external signal source to the source line Sj is 10 kΩ. Then, even if the stray capacitance C of the source wiring Sj is 10 pF, the time constant τ is
τ = RC = 10k × 10p = 0.1 μs
It becomes. In addition, when a voltage starts to be applied from the external signal source to the source line Sj at time t = 0, the potential v of the source line Sj at the time t has elapsed is
v = Vda (1-exp (-t / RC))
It becomes.

Here, when time t = 0.5 μs,
v = Vda (1-exp (-t / RC))
= Vda (1-exp (-0.5 / 0.1)) ≈0.993 Vda
Therefore, the potential of the source wiring Sj after the elapse of time t = 0.5 μs reaches 99.3% of the desired potential Vda. This state seems to fall within an allowable range as an error in the current value output from the driving transistor. Therefore, the time t1 required to charge the source wiring Sj one by one from the external signal source can be estimated as t1 = 0.5 μs / line.

Therefore, if the number of gate wirings is 240 (corresponding to QVGA) and one frame period is 1/60 s, the selection period t2 per gate wiring is
t2 = (1/60) / 240≈69 μs
It becomes. Accordingly, it is possible to estimate that t2 / t1≈138 source wirings Sj can be sequentially charged in the selection period t2 per gate.

  Actually, the entire selection period t2 cannot be used for charging the source wiring. For this reason, if the number is estimated slightly, the number of source wirings Sj that can be charged in order during the selection period is 80. This means that when the number of source lines Sj is 320, it is possible to display at the selection time t2 if the control IC is designed to output four RGB video signals in parallel.

  As described above, when the display device 1 is used, it is possible to display with a sufficient selection time secured.

[Embodiment 2]
In Embodiment Mode 2, another example of the display device according to the present invention will be described.

  In the pixel circuit configuration of the first embodiment, as shown in FIG. 1, the resistor 14 is arranged for each pixel. However, if the resistor 14 is disposed for each pixel, the number of elements disposed per pixel increases. For this reason, depending on the pixel size, it may be possible that an element necessary for the pixel does not fit.

Therefore, in the display device according to the second embodiment, the switching TFT 11 and the resistor 14 are removed from the configuration of the pixel circuit Aij in FIG. 1 shown in the first embodiment, as shown in FIG. Shall be. Thus, the number of elements per pixel is reduced as much as possible. Instead, the organic EL (current driving element) 20 has a function as voltage-current conversion means. Further, the switching TFT (light emission control switching element) 7 is provided with a function as a current control switching element for switching on / off the connection between the gate terminal of the driving TFT 6 and the voltage / current converting means.
Note that the pixel circuit Bij does not include the control wiring Wi and the power supply wiring Vr included in the pixel circuit Aij, but the others are the same. Hereinafter, the same members as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  Based on FIG. 7, the operation of the control wiring Pc, the input video signal wiring Da, the control wiring PGj (PG1, PGm), the source wiring Sj (S1, Sm), the gate wiring Gi, and the control wiring Ri, Ci in the pixel circuit Bij. Timing will be described.

  Also in the second embodiment, the time 0 to 12t1 is set as the selection period of the pixel Bij. Among these, the time t1 to 11t1 in which the potential of the gate wiring Gi is High is defined as a first period.

  First, between time 0 and t1, the potential of the control wiring Pc is set to High (GH), the switching TFT 15 is turned on, and a voltage is supplied from the voltage wiring Vc to the source wiring Sj. The potential of the voltage wiring Vc was set to a value larger than the potential Vda of the input video signal Da.

  Next, the operation in the first period (time t1 to 11t1) will be described.

  First, at time t1, the potential of the gate wiring Gi becomes High, so that the switching TFT 8 is turned on, and the potential of the source wiring Sj is applied to the other terminal of the capacitor 13. Since the switching TFT 9 is also turned on, the gate and drain terminals of the driving TFT 6 are short-circuited. For this reason, in the driving TFT 6, the gate potential is set to a state where some current flows between the source and the drain. Further, since the potential of the control wiring Ri is Low (GL) during the time t1 to 2t1, the switching TFT 7 remains on. For this reason, the anode of the organic EL 20 is connected to the drain terminal of the driving TFT 6. Thereafter, at time 2t1, the potential of the control wiring Ri is set to High (GH), and the switching TFT 7 is turned off.

  Further, during the period from 2t1 to 8t1, the potential of the control wiring PGj (j = 1 to m) is sequentially set to High (GH), and the switching TFT 16 of the drive circuit 5 corresponding to each source wiring Sj is turned on every t1 time. State. As a result, the potential Vda of the input video signal Da corresponding to the pixel Bij is input and held in the source line Sj (j = 1 to m).

  Thus, in the first period of time t1 to 11t1, the potential of the gate wiring Gi is set to High, and the switching TFTs 8 and 9 are turned on.

  As a result, the switching TFT 8 connects the other terminal of the capacitor 13 to the source wiring Sj. For this reason, the potential Vda of the input video signal Da corresponding to the pixel Bij is input from the switching TFT 8 to the other terminal of the capacitor 13.

  Further, the gate terminal and the drain terminal of the driving TFT 6 are connected by the switching TFT 9. Here, the initial state of the driving TFT 6 is a state in which a current flows between the source and drain terminals. For this reason, the gate terminal potential and the drain terminal potential are increased by the charge supplied from the source terminal. Since this potential rise continues until the driving TFT 6 is turned off, the potential between the gate and source terminals of the driving TFT 6 becomes the threshold voltage (Vth) of the driving TFT 6.

  Note that, during the above period, the charge at both ends of the capacitor 13 changes in accordance with the change in the gate terminal potential of the driving TFT 6. However, the stray capacitance C is connected to the other terminal of the capacitor 13 through the source line Sj, and the capacitance is such that the stray capacitance C> the capacitance of the capacitor 13. For this reason, the other terminal potential of the capacitor 13 hardly changes.

  Next, a non-selection period of the pixel circuit Bij after the time 12t1 will be described. First, time 13t1 to 23t1 is set as the second period.

  In the second period, the potential of the control wiring Ci is set to High (GH), and the switching TFT 10 is turned on. Thereby, the other terminal of the capacitor 13 is connected to the drain terminal of the driving TFT 6.

  Further, the potential of the control wiring Ri is set to Low (GL), and the switching TFT 7 is turned on. Thereby, the drain terminal of the driving TFT 6 is connected to the anode of the organic EL 20 through the switching TFT 7.

  As described above, in the present embodiment, the switching TFT 10 is turned on in the second period to connect the other terminal of the capacitor 13 and the drain terminal of the driving TFT 6 and the switching TFT 7 is turned on. .

  At this time, the current Ids flowing through the driving TFT 6 is determined by the potential Vda previously applied to the other terminal of the capacitor 13, the threshold / mobility characteristics of the driving TFT 6, and the voltage / current characteristics of the organic EL 20. That is, it is determined based on the potential applied to the other terminal of the capacitor 13.

  When the potential of the control wiring Ci becomes Low (GL) at time 23t1 and the switching TFT 10 is turned off, the potential corresponding to the current value Ids is held at the gate terminal of the driving TFT 6.

  As described above, the potential corresponding to the current value Ids can be held at the gate terminal of the driving TFT 6 by the first period and the second period of the pixel circuit Bij. Note that the first period for the next pixel circuit A (i + 1) j can be started from 12t1, as in the first embodiment.

  With respect to the operation of the pixel circuit Bij described above, simulation results are shown in FIGS. 8A to 8C (hereinafter, the whole of FIGS. 8A to 8C is simply referred to as FIG. 8). . 8A and 8B show a driving operation in the display device 1. FIG. 8C shows a gate potential N1 and a drain potential N2 of the driving TFT 6 and between the source and drain terminals of the driving TFT 6. The result of having simulated the change of the flowing electric current Ids is shown. Note that the gate potentials N1 (1) to N1 (5), the drain potentials N2 (1) to N2 (5), and the current Ids (1) flowing between the source and drain terminals of the driving TFT 6 shown in FIG. ) To Isd (5) are obtained using the threshold voltage / mobility characteristics of the driving TFT 6 shown in Table 1 above.

  Here, the time 0 to t1 corresponds to the time 1.988 to 1.992 ms shown in FIG. Further, the time t1 to 11t1 as the first period corresponds to the time 1.992 to 2.044 ms shown in FIG.

  Among these, a current flows from the driving TFT 6 toward the organic EL 20 during a period of time 1.992 to 1.996 ms corresponding to the period of time t1 to 2t1. Thereafter, the gate potential N1 of the driving TFT 6 becomes the threshold potential of the driving TFT 6 under the above conditions. During this time, N1 = N2 and are overlapped in the figure. Then, the first period ends at time 2.044 ms corresponding to the time 11t1.

  Next, the second period is started at time 2.052 ms corresponding to time 13t1, and the second period is ended at time 2.108ms corresponding to time 23t1. At this time, the gate potential of the driving TFT 6 is held in the capacitors 13 and 12.

  Note that, as shown in FIG. 8, the gate potential of the driving TFT 6 changes and the current Ids flowing through the driving TFT slightly changes with the change of the potential of the control wiring Ci at time 2.108 ms. .

  Here, in the circuit configuration of the pixel Bij shown in FIG. 6, the organic EL 20 also serves as a voltage-current conversion unit. For this reason, the operation of setting the control wiring Ci to Low in this time 2.108 ms (the above time 23t1) is not necessarily required. Rather, it is preferable to keep the potential of the control wiring Ci high as it is because the current Ids does not change as described above. In that case, the control wiring Ci is set to Low immediately before the first period, that is, at time 1.988 (time 0). As described above, it is preferable to turn off the switching TFT 10 before the gate wiring Gi is set to High. Thereafter, a current Ids flows from the driving TFT 6 to the organic EL 20.

  FIG. 9 shows the result of simulating this current Ids while changing the potential of the input video signal Da.

  As shown in FIG. 9, according to the configuration of the present embodiment, the value of the current flowing through the driving TFT 6 in a region where the current is relatively small (Ids ≦ 0.2 μA) regardless of variations in the characteristics of the driving TFT 6. Variation can be reduced. Therefore, a display device that can secure a sufficient selection time can be obtained.

  As described above, according to the configuration of the present embodiment, the number of elements per pixel can be reduced as compared with the first embodiment, and the source driver circuit can be configured with a relatively simple circuit configuration as in the first embodiment. 2 can be configured. Therefore, it is possible to narrow the frame on the lower side of the panel. Further, it is possible to suppress a decrease in yield and to prevent a decrease in the number of panels that can be taken per sheet, thereby preventing an increase in cost per panel.

[Embodiment 3]
In Embodiment 3, another example of the display device according to the present invention will be described.

  Here, in the above-described second embodiment, the pixel circuit Bij using the organic EL 20 as the voltage-current conversion unit has been described.

  However, the organic EL has temperature-dependent voltage-current characteristics. Further, the organic EL gradually increases its temperature as it continues to emit light, and eventually becomes a constant temperature saturated. For this reason, even if the same voltage is applied to the source wiring Sj between the case where the pixels that have already emitted light are continuously emitted and the case where the pixels that are not emitting light are newly emitted, the distance between the source and drain of the driving TFT 6 The current values flowing through are different. This is recognized as a burn-in phenomenon of a period of several ms.

  In addition, there is a change with time in the voltage-current characteristics of the organic EL. For this reason, in the case where a current is supplied to a pixel that frequently emits light and the case where a current is supplied to a pixel that emits light only occasionally, the current flows between the source and drain of the driving TFT 6 even if the same voltage is applied to the source wiring Sj. The current value will be different. This is recognized as a burning phenomenon that increases with the use time.

  Here, as in the pixel circuit Aij of FIG. 1 described in the first embodiment, if the resistor 14 is arranged in the pixel circuit as a voltage-current conversion means, the above-described burn-in can be made inconspicuous. However, there arises a problem that the number of elements per pixel increases.

  Therefore, in the third embodiment, a device is devised not on the pixel circuit Cij but on the drive circuit (supply circuit) 5a side. That is, as shown in FIG. 10, a resistor 19 (voltage / current converting means) is arranged in the drive circuit 5a. A switching TFT (current control switching element) 18 is connected between the source line Sj and the resistor 19. That is, in this configuration, the source wiring Sj is used as a path for adjusting the current using the resistor 19.

  Hereinafter, the configuration of the pixel circuit Cij and the drive circuit 5a will be described. Note that the display device used in this embodiment is only different from the pixel circuit Cij and the driving circuit 5a in the other respects, and the rest is the same as in the first and second embodiments. Therefore, the same members as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 10, in the pixel circuit Cij, the driving TFT 6, the switching TFT 7, and the organic EL 20 are connected in series between the power supply wiring Vp and the common wiring Vcom. A capacitor 12 is connected between the gate terminal and the source terminal of the driving TFT 6. Between the gate terminal of the driving TFT 6 and the source line Sj, a switching TFT 21 (signal switching switching element) and a capacitor 22 (holding means, holding capacitor) are connected in series.

  Thus, in the present embodiment, the other terminal of the capacitor 22 is connected to the source line Sj from the beginning. A switching TFT 21 is connected between one terminal of the capacitor 22 and the gate terminal of the driving TFT 6.

  A switching TFT 9 is connected between the gate terminal and the drain terminal of the driving TFT 6.

  Further, a switching TFT 17 (adjusting means, current adjusting switching element) is connected between the drain terminal of the driving TFT 6 and the source wiring Sj. Since the source wiring Sj is connected to the other terminal of the capacitor 22, it can be expressed that the switching TFT 17 is connected between the other terminal of the capacitor 22 and the drain terminal of the driving TFT 6.

  A gate wiring Gi is connected to the gate terminal of the switching TFT 21. Control wirings Ri, Pi, Ci are connected to gate terminals of the switching TFTs 7, TFT 9, and TFT 17, respectively.

  On the other hand, the drive circuit 5 a includes a switching TFT 18 and a resistor 19 in addition to the switching TFTs 15 and 16.

  The switching TFT 15 is connected between the voltage wiring Vc and the source wiring Sj. The switching TFT 16 is connected between the input video signal wiring Da and the source wiring Sj. The resistor 19 and the switching TFT 18 are connected in series between the power supply wiring Vr and the source wiring Sj. Control wirings Pc, PGj, and Wc are connected to the gate terminals of the switching TFTs 15, TFT 16, and TFT 18, respectively.

  Next, based on FIG. 11, in the pixel circuit Cij and the drive circuit 5a, the control wiring Pc, the input video signal wiring Da, the control wiring PGj (PG1, PGm), the source wiring Sj (S1, Sm), the control wiring Wc, The operation timing of the gate line Gi and the control lines Ri, Pi, Ci will be described.

  In the third embodiment, the time 0 to 16t1 is set as the selection period of the pixel Cij. Among these, the time t1 to 11t1 in which the potential of the gate wiring Gi is High is defined as a first period.

  First, between time 0 and t1, the potential of the control wiring Pc is set to High (GH), the switching TFT 15 is turned on, and a voltage is supplied from the voltage wiring Vc to the source wiring Sj. Note that the potential of the voltage wiring Vc was set to a value larger than the potential Vda of the input video signal Da.

  Further, since the potential of the control wiring Ri is set to Low (GL) until the time 2t1, the switching TFT 7 remains on. Here, since the potential of the control wiring Pi is High, the switching TFT 9 is turned on, and the gate and drain terminals of the driving TFT 6 are short-circuited. Since the organic EL 20 is connected to the drain terminal of the driving TFT 6 via the switching TFT 7, the gate potential of the driving TFT 6 is in a state where some current flows between the source and drain of the driving TFT 6. At time 2t1, the potential of the control wiring Ri is set to High (GH), and the switching TFT 7 is turned off.

  Next, during the period from time 2t1 to time 8t1, the potential of the control wiring PGj (j = 1 to m) is sequentially set to High (GH), and the switching TFT 16 of the drive circuit 5 corresponding to each source wiring Sj is set to t1 time. Turn on. As a result, the potential Vda of the input video signal Da corresponding to the pixel Cij is input and held in the source line Sj (j = 1 to m).

  In the first period of time t1 to 11t1, since the potential of the gate wiring Gi is High, the switching TFT 21 is turned on. For this reason, the one terminal of the capacitor 22 and the gate terminal of the driving TFT 6 are connected via the switching TFT 21.

  Further, the potential of the control wiring Pi is also set to High, and the switching TFT 9 is turned on. As a result, the gate terminal and the drain terminal of the driving TFT 6 are connected by the switching TFT 9. Here, since the initial state of the driving TFT 6 is a state in which a current flows between the source and drain terminals, the gate terminal and drain terminal potentials are increased by the charge supplied from the source terminal of the driving TFT 6. Since this potential rise continues until the driving TFT 6 is turned off, the potential between the gate and source terminals of the driving TFT 6 becomes the threshold voltage (Vth) of the driving TFT 6.

  Note that, during the period, the charge at both ends of the capacitor 22 changes in accordance with the change in the gate terminal potential of the driving TFT 6. However, since the stray capacitance C is connected to the other terminal of the capacitor 22 through the source wiring Sj, and the stray capacitance C> the capacity of the capacitor 22, the potential of the other terminal of the capacitor 22 hardly changes. The potential of the capacitor 22 is maintained by turning off the switching TFT 9 at time 11t1.

  Next, the second period of time 12t1 to 15t1 will be described. In the second period, the potential of the control wiring Ci is set to Low (GL) while the gate wiring Gi is set to High (GH). As a result, the switching TFT 17 is turned on. Thereby, the other terminal of the capacitor 13 is connected to the drain terminal of the driving TFT 6 through the source wiring Sj and the switching TFT 17.

  Further, the potential of the control wiring Wc is set to Low (GL), and the switching TFT 18 is turned on. Thereby, the source line Sj is connected to the resistor 19 through the switching TFT 18.

  Therefore, as in the first embodiment described above, when the current flowing through the driving TFT 6 is small, the other terminal potential of the capacitor 22 becomes a value close to the potential Vda of the input video signal Da previously applied. When this potential is the potential Vda ′, the current Ids flowing through the driving TFT 6 becomes Ids≈ (Vda′−Vr) / R using the resistance value R of the resistor 19 and the potential Vr of the power supply wiring Vr.

  At time 15t1, when the potential of the gate wiring Gi is set to Low (GL) and the switching TFT 22 is turned off, a potential corresponding to the current value Ids is held at the gate terminal of the driving TFT 6.

  As described above, the potential corresponding to the current value Ids can be held at the gate terminal of the driving TFT 6 by the first period and the second period of the pixel circuit Cij. Note that the first period of the next pixel circuit C (i + 1) j starts after 16t1.

  According to the configuration of the present embodiment, it is not necessary to arrange a resistor in the pixel circuit. For this reason, there is an effect of reducing the number of elements arranged per pixel. In addition, since the resistor is used as the voltage-current conversion means, the above-mentioned burning phenomenon can be alleviated. However, according to the configuration of this embodiment, since the source wiring Sj is used even in the second period, the scanning time (selection period) becomes long.

  Next, the operation of the pixel circuit Cij described as described above is simulated in FIGS. 12A to 12C (hereinafter, FIGS. 12A to 12C are simply referred to as FIG. 12). Results are shown. 12A and 12B show a driving operation in the display device 1. FIG. 12C shows a gate potential N1 and a drain potential N2 of the driving TFT 6 in the pixel circuit Cij, and a source A change in current Ids flowing between the drains is shown. In the calculation of FIG. 12C, the conditions shown in Table 1 above were used as the threshold voltage / mobility characteristics of the driving TFT 6.

  Here, the time 0 to t1 corresponds to the time 3.284 to 3.288 ms shown in FIG.

  Further, the time t1 to 11t1 that is the first period corresponds to the time 3.288 to 3.340 ms shown in FIG. 12, and the time 12t1 to 15t1 that is the second period is the time 3.344 to 3.356 ms shown in FIG. It corresponds to.

  In the first period, first, a current flows from the driving TFT 6 toward the organic EL 20 during a time period of 3.288 to 3.292 ms corresponding to the time period t1 to 2t1. The gate potential N1 of the driving TFT 6 is the threshold potential of the driving TFT 6 under the above conditions. During this time, N1 = N2 and are overlapped in the figure. The first period ends at time 3.340 ms corresponding to time 11t1. The second period starts from time 3.344 ms corresponding to time 12t1. The second period ends at time 3.356 ms corresponding to time 15t1. The gate potential of the driving TFT 6 at this time is held in the capacitors 13 and 12. Thereafter, a current Ids flows from the driving TFT 6 toward the organic EL 20.

  FIG. 13 shows the result of simulating the current Ids while changing the potential of the input video signal Da. As shown in FIG. 13, according to the configuration of the present embodiment, the value of the current flowing through the driving TFT 6 in a region where the current is relatively small (Ids ≦ 0.4 μA) regardless of the characteristic variation of the driving TFT 6. Variation can be reduced.

  As described above, according to the configuration of the present embodiment, for example, the source driver circuit 2 can be configured with a relatively simple circuit configuration as described above even when the number of elements per pixel is reduced as compared with the configuration of the first embodiment. Can be configured. For this reason, the frame on the lower side of the panel can be narrowed. Further, it is possible to suppress a decrease in yield, prevent a decrease in the number of panels that can be taken per sheet, and prevent an increase in cost per panel.

[Embodiment 4]
In the fourth embodiment, still another example of the display device according to the present invention will be described.

  In the configuration of the third embodiment described above, the source wiring Sj (first wiring) is also used in the second period. As described above, if the time for using the source wiring becomes long, the selection time required for each gate wiring increases. For example, in the first and second embodiments, the selection time required per gate wiring is 12 t1, whereas in the third embodiment, the selection time is increased to 16 t1. When the selection time increases in this way, there may be a case where a sufficient selection time cannot be secured depending on the display device.

  In the present embodiment, in order to solve such a problem, as shown in FIG. 14, the pixel circuit Dij includes a resistance wiring (wiring) Tj arranged in parallel to the source wiring Sj and a switching TFT (current). Control switching element) 23. The resistor (voltage / current converting means) 24 is arranged outside the pixel circuit, that is, on the source driver circuit 5 side. This configuration is a substitute for the resistor 14 and the switching TFT 11 of the pixel circuit Aij shown in FIG.

  As shown in FIG. 14, in the pixel circuit Dij, the switching TFT 23 is connected between the drain terminal of the driving TFT 6 and the wiring Tj. Further, a resistor 24 is connected between the resistance wiring Tj and the power supply wiring Vr. The rest is the same as the configuration of the pixel circuit Aij in FIG.

  This makes it possible to use the resistance wiring Tj instead of using the source wiring Sj in the second period. Therefore, as in Embodiments 1 and 2, the first period of the pixel circuit D (i + 1) j can be started after the 12t1 period. Since other operations are the same as those in the first embodiment, detailed description thereof is omitted here.

  In the pixel circuit Aij shown in FIG. 14, the number of wirings per pixel increases as the resistance wiring Tj increases, and there is a concern that necessary elements cannot be arranged in the pixel. In that case, the resistance wiring Tj may be formed on the same surface as the pixel electrode 25 as in the layout shown in FIG. The pixel electrode 25 is made of ITO, a reflective electrode (Al), or the like. Inside the bank 26 (inside the ellipse), no bank is formed and an organic EL is formed. Therefore, as shown in the figure, a bank is formed between the pixel electrodes, and the pixel electrode is formed in a part below the bank, so that the wiring can be made with the same material as the pixel electrode therebetween.

  In FIG. 15, the drain terminal of the driving TFT 6 and the anode 25 of the organic EL are connected by a through hole 27. Similarly, the drain terminal of the switching TFT 23 and the resistance wiring Tj are connected by a through hole 28. Further, these through holes 28 are hidden under the insulating film or bank 26.

  Thus, according to the configuration of the present embodiment, a display device that can ensure a sufficient selection time is obtained.

[Embodiment 5]
In the display devices described in the first to third embodiments, an analog video signal is input as an analog voltage signal from a controller circuit (not shown). However, the display device according to the present invention can be applied not only when inputting such an analog video signal but also when inputting a digital video signal. In the present embodiment, the configuration of the display device 31 in such a case will be described.

  The display device 31 of the present embodiment is a display device that performs time-division gradation display using a 1-bit digital video signal.

  As shown in FIG. 16, the display device 31 includes a source driver circuit 32, a gate driver circuit 33, and a pixel circuit Aij.

  The address Add is input to the gate driver circuit 33. The gate driver circuit 33 outputs a necessary control signal to the gate wiring Gi, the control wiring Ri, and the like corresponding to the input address Add.

  The source driver circuit 32 receives the data signal Dx, the start pulse SP, the clock clk, and the latch pulse LP. The source driver circuit 32 has a 1-bit configuration. The shift register 34 is m bits, the register 35 is m bits, the latch 36 is m bits, and the analog switch circuit 37 is configured to select one potential from two potentials.

  The start pulse SP is input to the source driver circuit 32 to the first register of the m-bit shift register 34. The shift register 34 transfers the start pulse SP with the clock clk in the shift register 34. The shift register 34 transfers the start pulse SP and outputs it to the register 35 as a timing pulse SSP.

  The register 35 has m bits, and the input 1-bit data Dx is held for each position of the corresponding source wiring Sj by the timing pulse SP sent from the shift register 34 and transferred to the latch 36.

  Then, the latch 36 outputs the data Dx as m-bit data to the analog switch circuit 37 at the timing of the latch pulse LP. In the analog circuit 37, the corresponding potential is selected and output to the source line Sj.

  Since the subsequent operation is the same as in the first to third embodiments, the description thereof is omitted.

  Thus, the display device according to the present invention can also be applied to a digital video display circuit that performs time-division gradation display.

  In this case, as can be seen by comparing the display device 31 of FIG. 16 and the display device 101 of FIG. 19 of the conventional example, in the display device 31, the configuration of the register 35, the latch 36, and the analog switch circuit 37 (drive circuit). Becomes easy. Therefore, the source driver circuit 2 can be configured with a relatively simple circuit configuration, and the frame on the lower side of the panel can be narrowed. In addition, it is possible to prevent a decrease in the yield, prevent a decrease in the number of panels that can be taken per sheet, and prevent an increase in cost per panel.

  As described above, according to the present invention, it is possible to provide a display device that can shorten the selection period per pixel and reduce the size of the source driver circuit.

  As described in the above embodiment, in the display device according to the present invention, the potential holding capacitor and the compensation capacitor are connected to the gate terminal of the driving TFT, and the other terminal of the compensation capacitor is desired in the first period. The gate terminal and the drain terminal of the driving TFT are short-circuited, and the gate terminal and the drain terminal of the driving TFT are opened in the second period, and the other terminal of the compensation capacitor is connected to the drain terminal of the driving TFT. And the output current value is set to simplify the source driver circuit configuration.

  Here, the difference between the prior art and the display device according to the present invention (hereinafter referred to as the present display device) will be supplementarily described.

  As described above, the configuration described in Patent Document 1 as shown in FIG. 17 cannot compensate for variations in TFT mobility.

  On the other hand, according to the configuration of the display device shown in FIG. 1, for example, as described above, the variation in the current value flowing through the driving TFT can be reduced.

  This is because the present display device includes configurations of the switching elements 10 and 11 and the resistor 14 as can be seen by comparing FIG. 17 and FIG. That is, this display device uses these configurations to hold the potential corresponding to the desired current value Ids at the gate terminal of the driving TFT 6, and the set current Ids from the driving TFT 6 toward the organic EL 20. Realize the function to flow.

  Further, as described above, variations in TFT mobility can also be compensated for by the configuration described in Patent Document 2 and the like.

  That is, the configuration of Patent Document 2 and the like and the configuration of the present display device are for correcting variations in mobility of TFTs by different methods. According to the configuration of the present display device, effects such as suppression of increase in circuit scale and shortening of the selection period per pixel, which cannot be obtained with the configuration of Patent Document 2, etc., are obtained.

  Hereinafter, the configuration described in Patent Document 2 will be briefly described with reference to FIGS.

  As shown in FIG. 18, the pixel circuit aij is connected with a power supply wiring Vs, a scanning wiring Gi, and a source wiring Sj. The pixel circuit aij includes a driving TFT 110, switching TFTs 111, 112, and 113, a capacitor 114, and an organic EL element 109. One end of the organic EL element 109 of the pixel circuit aij is connected to the counter electrode Vcom.

  The driving TFT 110, the switching TFT 111, and the organic EL element 109 are arranged in series between the power supply wiring Vs and the counter electrode Vcom. The switching TFT 112 is connected between the source line Sj and the drain terminal of the driving TFT 110. The switching TFT 113 is connected between the gate terminal and the drain terminal of the driving TFT 110. The scanning wiring Gi is connected to the gate terminals of the switching TFTs 111, 112, and 113, respectively. The capacitor 114 is connected between the source terminal and the gate terminal of the driving TFT 110.

  The pixel circuit aij is driven as follows. First, in the selection period, the scanning wiring Gi is set to Low. As a result, the switching TFT 111 is turned off and the switching TFTs 112 and 113 are turned on.

  In this state, a current is supplied from the power supply wiring Vs to the source wiring Sj through the driving TFT 110 and the switching TFT 112. Here, the value of the current flowing through the source line Sj can be controlled by a current source of a source driver circuit (not shown) connected to the source line Sj. Therefore, when the output current value of the driving TFT 110 is controlled to be a predetermined current value by the current source of the source driver circuit, the gate voltage of the driving TFT 110 is set to a predetermined value.

  As described above, the gate potential of the driving TFT 110 is equal to the current supplied from the current source of the source driver circuit by the output current value of the driving TFT 110 regardless of variations in threshold voltage and mobility in the driving TFT 110. Set to be a value. Thereafter, the selection period ends.

  FIG. 19 shows an example of a display device including the pixel circuit shown in FIG. The display device 101 includes a plurality of pixel circuits aij, a source driver circuit 102, a gate driver circuit 103, and a reference current source 104.

  Each pixel circuit aij is arranged in the vicinity where the source line Sj and the gate line Gi intersect.

  The source driver circuit 102 includes a shift register 105, a register 106, a latch 107, and a plurality of driving circuits 108. The source driver circuit 102 has a 6-bit configuration, the shift register 105 has m bits, the register 106 has m × 6 bits, the latch 107 has m × 6 bits, and the drive circuit 108 has 6 bits each.

  In the source driver circuit 102, the start pulse SP is input to the head register of the shift register 105. In the shift register 105, the start pulse SP is transferred in the shift register 105 in accordance with the clock clk. The start pulse SP is transferred and output from the shift register 105 to the register 106 as a timing pulse SSP. The register 106 receives a timing pulse SSP and 6-bit data Da. The register 106 holds the data Da for each position of the corresponding source wiring Sj and transfers it to the latch 107 in accordance with the timing pulse SSP. The latch 107 outputs 6-bit data to the drive circuit 108 for each source wiring Sj according to the input latch pulse LP.

  Next, the configuration of the drive circuit 108 will be described with reference to FIG. The drive circuit 108 sets a drive current from the reference current lines I0 to I5, the data signal lines D0 to 5 and the memorizing signal MSj connected from the reference current source 104, and outputs the drive current to the source line Sj. It is.

  Connected to the drive circuit 108 are data signal lines D0 to D5 to which data is input from the latch 107, and reference current wirings I0 to I5 to which current is input from the reference current source 104. The drive circuit 108 is connected to a source line Sj for outputting a set current and a line for the memorizing signal MSj.

  The drive circuit 108 includes six current copier circuits corresponding to the number of reference current wirings and data signal lines. In FIG. 20, for the sake of simplicity, only the current copier circuit 115 connected to the reference current wirings I0 and I5 is shown, and the current copier circuit connected to the reference current wirings I1 to I4 is omitted. Since each current copier circuit has a similar function, the current copier circuit 115 connected to the data signal line D5 and the reference current wiring I5 will be described below.

  The current copier circuit 115 connected to the reference current wiring I5 includes an n-type driving TFT 116, n-type switching TFTs 117 to 119, and a storage capacitor 120.

  The source terminal of the driving TFT 116 is grounded. One electrode (ground side electrode) of the storage capacitor 120 is connected to the source terminal of the driving TFT 116 and grounded. The other electrode (gate side electrode) of the storage capacitor 120 is connected to the gate terminal of the driving TFT 116.

  The memorizing signal MSj is input to the gate terminals of the switching TFTs 117 and 118. The gate terminal of the switching TFT 119 is connected to the data signal line D5. The source terminal of the switching TFT 117 is connected to the gate side electrode of the storage capacitor 120. The drain terminal of the switching TFT 118 is connected to the reference current wiring I5. The drain terminal of the switching TFT 119 is connected to the source line Sj. The drain terminal of the switching TFT 117, the source terminal of the switching TFT 118, the source terminal of the switching TFT 119, and the drain terminal of the driving TFT 116 are connected to each other.

  The output operation to the source line Sj in the drive circuit 108 configured as described above is performed as follows.

  First, the data TFTs D0 to D5 are set to Low to turn off the switching TFT 119. Further, the memorizing signal MSj is set to High, and the switching TFTs 117 and 118 are turned on. As a result, the reference current I5 output from the reference current source 104 flows between the drain and source terminals of the driving TFT 116 through the drain and source terminals of the switching TFT 118. At this time, the gate potential of the driving TFT 116 is in a state in which the reference current I5 flows, so that the potential of the gate side electrode of the storage capacitor 120 is a potential corresponding to the state.

  Thereafter, the memorizing signal MSj is set to Low, and the switching TFTs 117 and 118 are turned off. As a result, the set potential is held in the gate side electrode of the storage capacitor 120. Therefore, the storage capacitor 120 can hold a potential corresponding to the reference current I5 at the gate terminal of the driving TFT 116.

  In this state, the data signal D5 is set to High, and the switching TFT 119 is turned on. Thus, the reference current I5 corresponding to the gate potential of the driving TFT 116 can be output to the source line Sj via the driving TFT 119.

  Thus, in each current copier circuit 115, if the reference currents I0 to I5 are output to the source line Sj according to the data signals D0 to D5, respectively, the driving current corresponding to 6-bit gradation display (64 gradations). Can be output from the drive circuit 108.

  That is, in the conventional configuration described with reference to FIGS. 18 to 20, a drive current corresponding to the gradation is generated on the drive circuit side and supplied to the pixel circuit.

  As described above, this conventional configuration can reduce variations in the current value flowing through the driving TFT by a method different from the configuration of the display device. However, in this conventional configuration, the selection period per pixel cannot be shortened as compared with the present display device, and the source driver circuit cannot be reduced because the source driver circuit is, for example, a constant current circuit. Has drawbacks. This will be described in more detail as follows.

  The point that the size of the source driver cannot be reduced will be described as follows. That is, in the drive circuit 108 shown in FIG. 20, 4 × 6 = 24 TFTs are required for each source wiring Sj. Further, a 6-bit latch 107 and a 6-bit register 106 are required for each source wiring Sj. For this reason, it is difficult to reduce the circuit scale.

  In addition, since the area necessary for configuring the source driver circuit 102 is increased, the frame for arranging the source driver circuit 102 under the panel is increased. Furthermore, when the scale of the source driver circuit 102 required for one source wiring Sj increases, the yield decreases when the source driver circuit 102 is made of TFT. As a result, the number of panels that can be taken per predetermined sheet is reduced, leading to an increase in cost per panel.

  Next, the point that the selection period per pixel cannot be shortened will be described as follows. In the circuit configuration of FIG. 18, a stray capacitance C is generated in the source line Sj. A current value I0 flowing from the source line Sj toward the source driver 102 is determined in advance. In this case, assuming that the initial potential of the source line Sj is V0, a charge Q of Q = C × V0 exists in the source line Sj. On the other hand, if the gate potential necessary for the driving TFT 110 to finally flow the current I0 is Vg, the potential of the source wiring Sj needs to change from V0 to Vg. Therefore, the charge ΔQ that should flow from the source line Sj toward the source driver 102 shown in FIG. 19 is ΔQ = C × (V0−Vg). Since the time Δt required to flow this charge ΔQ is current i = ΔQ / Δt (differential value of charge change), Δt = ΔQ / I0.

  Consider this estimate more specifically. First, the stray capacitance of the source wiring Sj is such that the unselected switching TFT 112 serves as the stray capacitance of the source wiring Sj when the pixel circuit configuration as shown in FIG. 18 is arranged in a matrix as shown in FIG. It is because. For this reason, the stray capacitance of the source wiring Sj is several pF.

  Such a pixel circuit is driven by a driving circuit 108 shown in FIG. Since the driving circuit 108 has a 6-bit gradation (64 gradations) configuration, when the minimum value of the output current value is 1, the maximum value is 63.

  Here, the current to be passed through the organic EL 109 arranged in the pixel is several μA or less. This maximum current value is assumed to be 10 μA. Then, the minimum current value is 10 μA / 63≈0.16 μA. Further, it is assumed that the stray capacitance C of the source wiring Sj is 10 pF.

  At this time, if the current i to be passed through the organic EL 109 is 0.16 μA, the time t1 required to change the potential v of the source wiring Sj by 1V is t1 = v × C / i = 1 × 10 pF / 0. 16 μA = 63 μs.

  On the other hand, if the number of gate wirings in the display device shown in FIG. 19 is 240 (corresponding to QVGA), the selection period t2 per gate wiring is t2 = (1/60 ) / 240≈69 μs.

  According to the above estimation, in the display device having the configuration shown in FIG. 19, when the potential set at the gate terminal of the driving TFT 110 arranged in each pixel changes by 1.1 V or more, it can be assigned to writing as described above. The selection period t2 becomes insufficient.

  The gate width of the driving TFT is set so that the limit of the current value flowing through the TFT is several times larger than I0. For this reason, according to the structure of this display apparatus, selection time can be shortened rather than the structure of the prior art shown in FIG.

  Here, the display device described above is a display device in which driving transistors and current driving elements are arranged in a matrix, and a first capacitor is connected between a current control terminal and a reference potential terminal of the driving transistor, A second capacitor and a first switch transistor are connected in series between the current control terminal of the driving transistor and the first wiring so that one terminal of the second capacitor is on the current control terminal side of the driving transistor. In the first period, the other terminal of the second capacitor is short-circuited to the first wiring, and the current control terminal and the current input / output terminal of the driving transistor are short-circuited. The current control terminal and the current input / output terminal of the transistor are opened, and the other terminal of the second capacitor is connected to the driving transistor. It is configured to connect to the inflow output terminal, and can be expressed.

  Note that “the one terminal of the second capacitor is on the current control terminal side of the driving transistor” means that, among the two terminals of the second capacitor, the current control terminal side of the driving transistor is called one terminal. Means that.

  Further, “short-circuiting the other terminal of the second capacitor with the first wiring” means that the capacitor 22 (second capacitor) and the source wiring Sj (first wiring) shown in FIG. 10, for example, are always short-circuited. , Including.

  In the first period, a desired potential Vda is applied to the other terminal of the second capacitor through the first wiring, and between the current control terminal (gate terminal) potential of the driving transistor and the reference potential terminal (source terminal or drain terminal). Is a potential corresponding to the threshold potential (Vth) of the driving transistor.

  Then, in the second period, by opening the current control terminal and the current input / output terminal of the driving transistor, when the other terminal of the second capacitor is at the previously applied potential Vda, the driving transistor The current control terminal potential becomes a potential Vgs corresponding to the threshold potential (Vth).

  Therefore, in the second period, the other terminal of the second capacitor is connected to the current input / output terminal (drain terminal) of the driving transistor. At this time, if voltage / current conversion means such as a resistor or a diode is connected to the current input / output terminal of the driving transistor, the current flowing through the current input / output terminal of the driving transistor is converted to voltage / current by the desired potential Vda. The current value Ida is determined by the means. A potential corresponding to the current value Ida is set at the current control terminal of the driving transistor.

  As described above, the display device can determine the output current value of the driving transistor by applying a desired potential Vda to the other terminal of the second capacitor in the first period. Then, a desired potential Vda corresponding to a video signal to be displayed is output from an external signal source such as a control IC, and is supplied to the other terminal of the second capacitor of each pixel of the display device, whereby a current to be supplied to each current driving element. A value can be defined.

  The display device is a display device in which driving transistors and current driving elements are arranged in a matrix, wherein a first capacitor is connected between a current control terminal and a reference potential terminal of the driving transistor, and A second capacitor and a first switching transistor are connected in series between the current control terminal of the driving transistor and the first wiring, and one terminal of the second capacitor is on the current control terminal side of the driving transistor; A second switch transistor is connected between the current control terminal and the current input / output terminal of the drive transistor, and a second switch transistor is connected between the other terminal of the second capacitor and the current input / output terminal of the drive transistor. It can also be expressed as a configuration including a three-switch transistor.

  According to the above configuration, the second switching transistor is turned on in the first period, whereby the current control terminal and the current input / output terminal of the driving transistor can be short-circuited.

  In the second period, the second switching transistor is turned off, so that the current control terminal and the current input / output terminal of the driving transistor can be opened.

  In the second period, by turning on the third switching transistor, the other terminal of the second capacitor can be connected to the current input / output terminal of the driving transistor.

  There are three configurations for this connection. In the first configuration, one terminal of the second capacitor is connected to the current control terminal of the driving transistor, and the other terminal of the second capacitor is connected to the third switching transistor.

  In the second configuration, one terminal of the second capacitor is connected to the current control terminal of the driving transistor, and the third switch transistor is connected to the first wiring.

  The third configuration is a case where the first switch transistor is connected to the current control terminal of the drive transistor, and the third switch transistor is connected to the first wiring.

  In the above configuration, a configuration in which a fourth switching transistor is provided between the current input / output terminal of the driving transistor and the current driving element is also preferable.

  In the display device, in the first period, the potential of the current input / output terminal of the driving transistor is a potential corresponding to the threshold potential (Vth) of the driving transistor. Therefore, when a current drive element such as an organic EL is used as the current drive element, the voltage applied to the current drive element in the first period varies due to the influence of the threshold potential (Vth) of the driving transistor. As a result, the current Ids flowing through the current input / output terminal of the driving transistor varies due to the influence of the threshold potential (Vth) of the driving transistor. Since the current variation affects the current flowing through the current input / output terminal of the driving transistor in the second period, it is not preferable.

  Therefore, it is preferable to make the current Ids flowing through the current input / output terminal of the driving transistor constant during the first period. Specifically, as in a preferred configuration of the present invention, a fourth switch transistor is provided between the current input / output terminal of the drive transistor and the current drive element, and the fourth switch transistor is turned off in the first period. Thus, the current Ids flowing through the current input / output terminal of the driving transistor in the first period is set to zero.

  In the display device described above, a configuration in which a fifth switch transistor is provided between the current input / output terminal of the driving transistor and the voltage / current conversion means is also preferable.

  Here, in the display device according to the present invention, a case where a current driving element is used as a voltage-current conversion means connected to the current input / output terminal of the driving transistor in the second period, and a case where another element such as a resistor is used. There is.

  When an organic EL is used as the current drive element, the current drive element itself exhibits diode characteristics, so that the current drive element can be used as voltage-current conversion means.

  However, the voltage-current characteristics of organic EL are temperature dependent and also change with time. For this reason, it is preferable to introduce voltage-current conversion means that does not depend on temperature or change with time.

  Therefore, as in the preferred configuration of the present invention, the voltage / current conversion means is configured using a resistor, another organic EL element, or the like separately from the current driving element. A fifth switch transistor is connected between the voltage-current converter and the current input / output terminal of the driving transistor. In the second period, it is preferable that the current value Ida corresponding to the desired potential Vda is obtained by using the voltage-current converter by turning on the fifth switch transistor.

  In the above-described configuration, the display device described above preferably includes a fifth switch transistor between the first wiring and the voltage-current conversion unit.

  That is, as described above, when the voltage / current conversion means is configured using a resistor, another organic EL element, or the like, in addition to the current drive element, the voltage / current conversion means is a pixel (drive transistor and current drive element). It may be difficult to arrange for each display unit). In such a case, it is preferable that the voltage / current conversion means is disposed for each first wiring, and a fifth switch transistor is provided between the first wiring and the voltage / current conversion means.

  The specific embodiments or examples described above are merely to clarify the technical contents of the present invention, and the present invention is not limited to such specific examples and should not be interpreted in a narrow sense. Various modifications are possible within the scope of the claims, and the technique of the present invention is also applied to the modified embodiment and the embodiment obtained by appropriately combining the technical means disclosed in the embodiment. Included in the scope.

  Since the display device according to the present invention does not increase the circuit scale of the driving circuit, the frame of the panel can be narrowed, and can be applied to, for example, a portable display device.

It is a circuit diagram which shows an example of the pixel circuit contained in one Embodiment of the display apparatus of this invention. It is a block diagram which shows the outline of the said display apparatus. 4 is a timing chart showing operation timings of the pixel circuit and a driving circuit for driving the pixel circuit. (A) is a graph showing a part of an example of the driving operation in the display device, (b) is a graph showing another part of the example of the driving operation, (c) is a graph showing (a) and ( It is a graph which shows the result of having simulated the change of the gate electric potential N1, the drain electric potential N2, and the source-drain current Ids of the TFT for a drive of the said pixel circuit according to the operation | movement of b). It is a graph which shows the simulation result of the electric current value which flows through the organic EL element of the said pixel circuit. It is a circuit diagram which shows an example of the pixel circuit contained in other embodiment of the display apparatus of this invention. 4 is a timing chart showing operation timings of the pixel circuit and a driving circuit for driving the pixel circuit. (A) is a graph showing a part of an example of the driving operation in the display device, (b) is a graph showing another part of the example of the driving operation, (c) is a graph showing (a) and ( It is a graph which shows the result of having simulated the change of the gate electric potential N1, the drain electric potential N2, and the source-drain current Ids of the TFT for a drive of the said pixel circuit according to the operation | movement of b). It is a graph which shows the simulation result of the electric current value which flows through the organic EL element of the said pixel circuit. FIG. 10 is a circuit diagram illustrating an example of a pixel circuit included in still another embodiment of the display device of the present invention. 4 is a timing chart showing operation timings of the pixel circuit and a driving circuit for driving the pixel circuit. (A) is a graph showing a part of an example of the driving operation in the display device, (b) is a graph showing another part of the example of the driving operation, (c) is a graph showing (a) and ( It is a graph which shows the result of having simulated the change of the gate electric potential N1, the drain electric potential N2, and the source-drain current Ids of the TFT for a drive of the said pixel circuit according to the operation | movement of b). It is a graph which shows the simulation result of the electric current value which flows through the organic EL element of the said pixel circuit. FIG. 10 is a circuit diagram illustrating an example of a pixel circuit included in still another embodiment of the display device of the present invention. It is a top view which shows the schematic layout of the said pixel circuit. It is a schematic block diagram which shows other embodiment of the display apparatus of this invention. It is a circuit diagram which shows an example of the pixel circuit contained in the conventional display apparatus. It is a circuit diagram which shows the pixel circuit contained in another example of the conventional display apparatus. It is a block diagram which shows schematic structure of the said display apparatus. It is a block diagram which shows schematic structure of the drive circuit contained in the said display apparatus.

Explanation of symbols

1, 31 Display device 2, 32 Source driver circuit 3, 33 Gate driver circuit,
5, 5a Drive circuit (supply circuit)
6 Driving TFT (Driving transistor)
7 TFT for switch (light emission control switching element, current control switching element)
8, 21 TFT for switching (signal switching element)
9 Switch TFT (potential control switching element)
10, 17 TFT for switch
(Adjustment means, current adjustment switching element)
11, 18, 23 Switch TFT (current controlled switching element)
12 Capacitor (sustain capacitor)
13, 22 Capacitor (holding means, holding capacitor)
14, 19, 24 Resistance (voltage-current conversion means)
20 Organic EL (current drive element, voltage-current conversion means)
Aij, Bij, Cij, Dij Pixel circuit Sj Source wiring (supply wiring)
Gi gate wiring Tj resistance wiring (wiring)

Claims (6)

A current driven element, a display device arranged a driving transistor for controlling the current, the pixel circuit arranged and light-emission control switching transistor in series in a matrix of the sheet subjected to the current driven element,
Holding means for holding a potential difference between both ends by connecting one end to the control terminal of the driving transistor and the other end to a potential supply wiring of the input video signal via a signal switching switching element ;
A potential control switching element disposed between a control terminal and an output terminal of the driving transistor;
A current adjusting switching element disposed between the other end of the holding means and the output terminal of the driving transistor;
In the first period, the signal switching switching element and the potential control switching element are turned on, the light emission control switching transistor is turned off, and the potential of the input video signal is applied to the other end of the holding means,
In the second period, the signal switching switching element and the potential control switching element are turned off, the current adjusting switching element is turned on, and the voltage switching circuit is connected to a reference potential through voltage-current conversion means for converting voltage into current. set to the output terminal of the driver transistor, the connections to Rukoto the other end of the holding means, a current flowing through the driving transistor, the voltage difference between the potential and the reference potential of the output terminal of the driving transistor A display device characterized by:   The display device according to claim 1, wherein a resistor connected from the output terminal of the driving transistor through a wiring is used as the voltage-current conversion unit.   The display device according to claim 1, wherein the current driving element is used as the voltage-current conversion unit. The display device according to claim 1, wherein the voltage-current conversion unit is provided in a drive circuit that is provided outside the pixel circuit and supplies the input video signal to the pixel circuit .   2. The display device according to claim 1, further comprising a current control switching element for switching on and off the connection between the output terminal of the driving transistor and the voltage-current converter. A driving method of a display device according to claim 1,
Connecting the supply wiring to the control terminal of the driving transistor through the holding means , and connecting the control terminal and the output terminal of the driving transistor;
The connection from the supply wiring to the control terminal of the driving transistor via the holding means is released, the connection between the control terminal of the driving transistor and the output terminal is released, and the holding means A terminal on the supply wiring side and the output terminal of the driving transistor are connected, and the output terminal of the driving transistor is connected to a reference potential via the voltage-current conversion means, thereby flowing to the driving transistor. A method for driving a display device, comprising: setting a current by a voltage difference between an output terminal potential of the driving transistor and a reference potential .

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