JP4945063B2 - Active matrix display device - Google Patents

Active matrix display device Download PDF

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JP4945063B2
JP4945063B2 JP2004073145A JP2004073145A JP4945063B2 JP 4945063 B2 JP4945063 B2 JP 4945063B2 JP 2004073145 A JP2004073145 A JP 2004073145A JP 2004073145 A JP2004073145 A JP 2004073145A JP 4945063 B2 JP4945063 B2 JP 4945063B2
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period
signal line
switch
correction
scanning signal
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JP2005258326A (en
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博人 仲戸川
良朗 青木
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東芝モバイルディスプレイ株式会社
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The present invention relates to a display equipment, particularly relates to an active matrix display equipment.

  In recent years, organic electroluminescence (hereinafter referred to as EL) display devices have been attracting attention as displays for portable information devices typified by mobile phones because of their light weight, thinness, and high brightness. In a typical organic EL display device, each pixel is provided with memory so that a drive current having a magnitude corresponding to the video signal written in the writing period continues to flow to the organic EL element in the subsequent light emission period. Yes. That is, an active matrix driving method is adopted.

  By the way, in this organic EL display device, display unevenness is caused by the threshold voltage Vth of the drive control element (drive transistor) for controlling the magnitude of the drive current Id corresponding to the video signal varying between the pixels. May occur. To solve this problem, it has been proposed to provide a threshold cancel circuit in each pixel to correct the characteristics of the driving transistor (see Patent Document 1 below).

  According to this circuit, the influence of the threshold value Vth on the drive current Id can be minimized. Therefore, even if the threshold value Vth of the driving transistor varies between pixels, it is possible to reduce the influence of such variations on the driving current Id supplied to the organic EL element.

However, this technique employs a method in which the characteristic correction operation and the writing operation are performed on the next row after the characteristic correction operation and the writing operation are performed on a certain row. That is, both the characteristic correction operation and the writing operation are performed within one horizontal scanning period. For this reason, it is difficult to allocate sufficient time for both the characteristic correction operation and the writing operation, and as a result, there is a problem that display unevenness cannot be sufficiently solved.
US Pat. No. 6,229,506

An object of the present invention is to provide both can allocate enough time display equipment with characteristics correction and write operations.

According to one aspect of the present invention, comprising: a scanning signal line; a video signal line intersecting with the scanning signal line; and a pixel disposed in the vicinity of an intersection of the scanning signal line and the video signal line, Each of the pixels includes a drive current control element including a control terminal, a first terminal connected to the first power supply terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage therebetween, A first capacitor connected between the first terminal and the control terminal, an input terminal is connected to the video signal line, and its conduction state is in accordance with a scanning signal supplied through the scanning signal line. A selection switch to be switched, a second capacitor connected between the output terminal of the selection switch and the control terminal, a correction switch connected between the second terminal and the control terminal, and an input Terminal is connected to the second terminal An output control switch, and a display element that is connected between the output terminal of the output control switch and the second power supply terminal and whose optical characteristics change according to the magnitude of the flowing current. In the writing period, a writing operation is performed to supply a video signal from the video signal line to the terminal on the selection switch side of the second capacitor through the selection switch, and continues to the writing period. In the effective display period, the selection switch and the correction switch are turned off and the output control switch is turned on to pass the drive current through the display element, and in the correction period preceding the writing period. the and the correction switch the output control switch nonconductive and conductive, in this state, the selection switch from the video signal line By supplying a reset signal to the selection switch terminal of said second capacitor and performs a characteristic correction operation including providing a correction signal that reflects the characteristics of the drive current control element to the control terminal, nonconductive sequentially performs for each row of the pixels, respectively, said at least one of the selection switches and the correction switch of the pixels is performed before Symbol characteristic correction operation of said write operation and said characteristic correction operation A separation period to be in a state is provided within the correction period and after the start of supply of the reset signal, and with respect to the pixels in the previous row within the separation period for the pixels in a certain row An active matrix display device is provided which is configured to perform the writing operation.

  During the separation period, the selection switch may be in a non-conductive state while the correction switch for the pixel performing the characteristic correction operation is in a conductive state.

Alternatively, in the separation period, both the selection switch and the correction switch of the pixel performing the characteristic correction operation may be in a non-conductive state. In this case, in each of the characteristic correction periods, after the separation period, the signal supplied from the video signal line is switched from the video signal to the reset signal, and the pixel selection switch and the correction switch performing the characteristic correction operation Both may be made conductive again. Furthermore, in this case, the conduction state of each selection switch and correction switch of the pixel may be controlled by a control signal supplied via the same control line.
The display element may be an organic EL element.

According to the present invention, display equipment that can allocate enough time to both the characteristic correction and write operations is provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the same or similar component, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing a display device according to one embodiment of the present invention. Here, an organic EL display device is illustrated as an example.

  The organic EL display device 1 includes an organic EL panel 2 and a controller 3 that controls the display operation of the organic EL panel 2.

  The organic EL panel 2 has, for example, a 17-inch XGA display region, and a plurality of pixels PX arranged in a matrix on a support substrate 4 having light transmission properties and insulation properties such as a glass plate, and these pixels PX A plurality of scanning signal lines ScanMa, ScanMb, and ScanMc extending along the row, a plurality of video signal lines DataN extending in a direction substantially orthogonal to the row of the pixels PX, and the scanning signal lines ScanMa and ScanMb. , ScanMc are sequentially provided with a scanning signal line driver YDR for driving each of them and a video signal line driver XDR for driving the video signal lines DataN.

  Each pixel PX includes an organic EL element OLED that is a self-light-emitting element as a light-emitting element, and also includes a drive current control circuit and a characteristic correction circuit.

  The drive current control circuit includes a drive current control element TR, a selection switch SW1, and a capacitor C1. Here, as an example, a p-channel thin film transistor (hereinafter referred to as TFT) is used for the drive current control element TR, and an n-channel TFT is used for the selection switch SW1. These TFTs use, for example, a polycrystalline silicon film as their active layers, and can be formed in the same process as the TFTs constituting the scanning signal line driver YDR and the video signal line driver XDR.

  The drive current control element TR is connected in series with the organic EL element OLED between the pair of power supply terminals VDD and VSS. The drive current control element TR outputs a drive current having a magnitude corresponding to the voltage between the control terminal and the power supply terminal VDD to the organic EL element OLED.

  The selection switch SW1 is connected between the video signal line DataN and the control terminal of the drive current control element TR. That is, the selection switch SW1 has a source connected to the video signal line DataN, a drain connected to a control terminal of the drive current control element TR via a capacitor C2, which will be described later, and a gate connected to the corresponding scanning signal line ScanMa. Has been. The selection switch SW1 switches conduction / non-conduction between the video signal line DataN and the terminal on the selection switch SW1 side of the capacitor C2 according to the first scanning signal supplied via the scanning signal line ScanMa.

  The capacitor C1 is connected between the power supply terminal VDD and the control terminal of the drive current control element TR. The capacitor C1 plays a role of holding the voltage between the control terminal of the drive current control element TR and the power supply terminal VDD substantially constant for a predetermined period.

  Specifically, the selection switch SW1 is connected to the video signal line DataN and the drive current control element TR by the first scanning signal supplied from the scanning signal line driver YDR via the scanning signal line ScanMa corresponding to the writing operation. A signal supplied from the video signal line driver XDR via the video signal line DataN, for example, the video signal Vsig (= 0 to 4V), is output to the node A when the control terminal is brought into conduction. The driving current control element TR supplies a driving current Id having a magnitude corresponding to the video signal Vsig output from the selection switch SW1 to the organic EL element OLED.

  Note that the selection switch SW1 is connected between the control terminal and the output terminal of the drive current control element TR by the second scanning signal supplied from the scanning signal line driver YDR via the scanning signal line ScanMb corresponding to the characteristic correction operation. In the conductive state, the reset signal Vrst (= 8V) supplied from the video signal line driver XDR via the video signal line DataN is output to the node A. Further, the power supply terminals VDD and VSS are set to potentials of +10 V and 0 V, for example.

  Here, the characteristic correction circuit is a threshold cancel circuit, and includes a correction switch SW2, an output control switch SW3, and a capacitor C2. Here, as an example, p-channel TFTs are used for the correction switch SW2 and the output control switch SW3.

  The correction switch SW2 is connected between the output terminal and the control terminal of the drive current control element TR. The correction switch SW2 switches conduction / non-conduction between the output terminal of the drive current control element TR and the control terminal according to the second scanning signal supplied via the scanning signal line ScanMb.

  The output control switch SW3 is connected in series between the output terminal of the drive current control element TR and the organic EL element OLED. The output control switch SW3 switches conduction / non-conduction between the output terminal of the drive current control element TR and the organic EL element OLED according to the third scanning signal supplied via the scanning signal line ScanMc.

  The capacitor C2 is connected between the selection switch Sw1 and the control terminal of the drive current control element TR. Capacitor C2 prevents the movement of charges between nodes A and B and enables the potential change of node B corresponding to the potential change of node A.

  The organic EL element OLED has a structure in which an organic material layer including a light emitting layer which is a thin film including a red, green, or blue luminescent organic compound is interposed between a cathode and an anode. The organic EL element OLED generates excitons by injecting electrons and holes into an organic layer and recombining them, and emits light by light emission generated when the excitons are deactivated.

  The organic thin film layer may have a structure in which three layers of an anode buffer layer, a light emitting layer, and a cathode buffer layer are laminated, or a two-layer or single-layer structure in which these are functionally combined.

  The controller 3 is formed on a printed circuit board arranged outside the organic EL panel 2 and controls operations of the scanning signal line driver YDR and the video signal line driver XDR. The controller 3 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signals. The scanning control signal and the horizontal scanning control signal are supplied to the scanning signal line driver YDR and the video signal line driver XDR, respectively, and the digital video signal is supplied to the video signal line driver XDR in synchronization with the horizontal and vertical scanning timings.

  The video signal line driver XDR converts the digital video signal into an analog format under the control of the horizontal scanning control signal in each horizontal scanning period, and converts the video signal Vsig obtained thereby into a plurality of video signal lines DataN. In contrast, supply in parallel. Further, the video signal line driver XDR supplies the reset signal Vrst to the plurality of video signal lines DataN in parallel in each horizontal scanning period under the control of the horizontal scanning control signal.

  The scanning signal line driver YDR performs, for example, the first connection in each display period (= 1 frame period + vertical blanking period = correction period + writing period + effective display period) under the control of the vertical scanning control signal. A plurality of first scanning signals for changing the selection switch Sw1 in the on state → off state → on state → off state corresponding to the period, the separation period, the second connection period + the writing period, and the effective display period Sequentially supplied to the scanning signal line ScanMa. In this example, the correction period is equal to the sum of the reset period and the threshold cancellation period. In this example, the first connection period is the sum of the reset period and the beginning of the threshold cancellation period, the second connection period is the end of the threshold cancellation period, and the separation period is the first connection period. This is a period provided between the period and the second connection period (intermediate period of the threshold cancellation period), and is a period for electrically separating the temporary pixel and the corresponding video signal line during the characteristic correction operation. Further, here, after the supply of the first scanning signal at a level for turning on the selection switch Sw1 corresponding to the first connection period to the certain scanning signal line Scan (m−1) a is started, A period until the supply to the scanning signal line Scanma starts is defined as one horizontal scanning period (1H).

  The selection switch SW1 of each row receives the video signal in the first connection period, the second connection period, and the writing period only once per display period by the first scanning signal supplied from the corresponding scanning signal line ScanMa. The line DataN and the node A are made conductive, and are made non-conductive during other periods. The drive current control element TR supplies the drive current Id corresponding to the video signal Vsig supplied via the video signal line DataN during the writing period in which the selection switch SW1 is in a conductive state during the effective display period ( In the light emission period), the organic EL element OLED is supplied. These video signals Vsig are updated every display period, which is a video signal update cycle.

  In addition, the scanning signal line driver YDR, for example, in the respective display periods under the control of the vertical scanning control signal, for example, the first connection period, the separation period, and the second connection, as described with respect to the scanning signal line ScanMa. The second scanning signal for changing the correction switch Sw2 in the order of ON state → OFF state → ON state → OFF state corresponding to the period, the writing period + the effective display period is sequentially supplied to the plurality of scanning signal lines ScanMb. To do. The correction switch SW2 in each row outputs the output of the drive current control element TR in the first connection period and the second connection period only once per display period by the second scanning signal supplied from the corresponding scanning signal line ScanMb. Conduction is established between the terminal and the control terminal, and non-conduction is performed during other periods.

  Further, as described with respect to the scanning signal line ScanMa, the scanning signal line driver YDR performs, for example, a reset period, a threshold cancellation period + a writing period in each display period under the control of the vertical scanning control signal. A third scanning signal for changing the output control switch SW3 from the on state to the off state to the on state corresponding to the effective display period is sequentially supplied to the plurality of scanning signal lines ScanMc. The output control switch SW3 of each row is driven by the driving current control element TR and the organic EL element in the reset period and the effective display period only once per display period by the third scanning signal supplied from the corresponding scanning signal line ScanMc. Conduction between the OLED and non-conduction during other periods.

FIG. 2 is an equivalent circuit diagram of the pixel PX of the display device 1 shown in FIG.
As described above, each pixel PX includes a characteristic correction circuit in addition to the organic EL element OLED and the drive current control circuit. The drive current control circuit includes a drive current control element TR, a selection switch SW1, and a capacitor C1, and the characteristic correction circuit includes a correction switch SW2, an output control switch SW3, and a capacitor C2. . These switches SW1 to SW3 have the relationship shown in FIG. 3 in order to initialize the control voltage of the drive current control element TR to a level substantially equal to the threshold voltage Vth of the drive current control element TR in the correction period prior to the writing period. Is turned on / off.

FIG. 3 is a diagram illustrating an example of a driving method of the pixel PX illustrated in FIG.
As shown in FIG. 3, the correction period includes a reset period and a threshold cancellation period. In this example, no separation period is provided within the correction period.

  In the reset period, the voltage between the input terminal and the control terminal of the drive current control element TR is set to be larger than the threshold voltage Vth. Specifically, the switches SW1 to SW3 are turned on. In the reset period, the reset signal Vrst is supplied from the video signal line driver XDR to each video signal line DataN. By this operation, the potential of the node A is increased by the reset signal Vrst supplied through the selection switch SW1, and the potentials of the nodes B and C are decreased by the discharge current flowing through the correction switch SW2.

  In the subsequent threshold cancellation period, the output control switch SW3 is set to the off state while the switches SW1 and SW2 are maintained in the on state. As a result, the potential of the node B rises to a level substantially equal to the threshold voltage Vth of the drive current control element TR due to the charging current flowing through the correction switch SW2. At this time, the reset signal Vrst is supplied to the electrode on the node A side of the capacitor C2.

  In the writing period, the selection switch SW1 is turned on, and the switches SW2 and SW3 are turned off. As a result, the video signal Vsig is supplied to the node A via the selection switch SW1 instead of the reset signal Vrst supplied via the selection switch SW1. As a result, the potential of the node B becomes substantially equal to the sum of the threshold voltage Vth and the video signal Vsig.

  In the effective display period, the output control switch SW3 is turned on, and the switches SW1 and SW2 are turned off. As a result, the drive current Id is supplied to the organic EL element OLED via the output control switch SW3. Here, the drive current Id is determined by the potential difference between the reset signal Vrst and the video signal Vsig, and even if the threshold voltage Vth of the drive current control element TR varies between the pixels PX, such variation is caused. Can have an effect on the drive current Id.

In this aspect, the display device 1 is driven as described below.
FIG. 4 is a timing chart showing an example of a driving method that can be used in the display device 1 shown in FIG. Reference numerals Clka and Clkb shown in FIG. 4 indicate clock signals, Starta and Startb indicate start signals, and Video indicates a video signal, both of which are signals output by the controller 3. Reference numerals ScanMa, ScanMb, and ScanMc shown in FIG. 4 indicate scanning signals that the scanning signal line driver YDR outputs to the scanning signal lines ScanMa, ScanMb, and ScanMc, respectively.

  The scanning signal line driver YDR includes a shift register that generates a first pulse having a width of one horizontal period (Tw-Starta) corresponding to each horizontal scanning period from the start signal Starta and the clock signal Clka, and the start signal Startb and the clock signal Clka. To a shift register that generates a second pulse having a width (Tw-Startb) that is an integral multiple of one horizontal scanning period. The scanning signal line driver YDR generates a first scanning signal from the first and second pulses and the clock signal Clkb, and sequentially outputs the first scanning signal to the first scanning signal line ScanMa. The scanning signal line driver YDR generates a second scanning signal from the first and second pulses and the clock signal Clkb, and sequentially outputs the second scanning signal to the second scanning signal line ScanMb. Further, the scanning signal line driver YDR generates a third scanning signal from the first and second pulses and the clock signal Clkc, and sequentially outputs them to the third scanning signal line ScanMc.

  Specifically, in the reset period, the scanning signal line driver YDR supplies the first scanning signal of the selection level (here, High level) to the first scanning signal line ScanMa, and the second and third scanning signal lines ScanMb. , ScanMc is supplied with the second and third scanning signals of the selected level (here, Low level).

  In the threshold cancellation period, the scanning signal line driver YDR first supplies the first scanning signal of the selection level (here, High level) to the first scanning signal line ScanMa, and selects the selection level (here, the scanning signal line ScanMb). A second scanning signal at a low level is supplied, and a scanning signal at a non-selection level (here, a high level) is supplied to the third scanning signal line ScanMc. Note that the sum of this period and the reset period is the first connection period.

  Next, the scanning signal line driver YDR supplies the non-selection level (here, Low level) to the first scanning signal line ScanMa while supplying the non-selection level (here, High level) scanning signal to the third scanning signal line ScanMc. The first scanning signal is supplied, and the second scanning signal of the non-selection level (here, High level) is supplied to the second scanning signal line ScanMb. This period is a separation period (correction suspension period).

  Thereafter, the scanning signal line driver YDR supplies the selection level (here, High level) to the first scanning signal line ScanMa again while supplying the scanning signal of the non-selection level (here, High level) to the third scanning signal line ScanMc. The first scanning signal is supplied to the second scanning signal line ScanMb, and the second scanning signal of the selection level (here, Low level) is supplied. This period is the second connection period.

  In the writing period following the correction period, the scanning signal line driver YDR supplies the first scanning signal of the selection level (here, High level) to the first scanning signal line ScanMa, and the second and third scanning signal lines ScanMb. , ScanMc is supplied with the second and third scanning signals of the non-selection level (here, High level).

  In the effective display (light emission) period, the scanning signal line driver YDR supplies a low level scanning signal to the scanning signal lines ScanMa and ScanMc, and supplies a high level scanning signal to the scanning signal line ScanMb.

  In this aspect, writing is performed on the pixels PX in the previous row from the start to the end of the characteristic correction operation (= reset operation + threshold cancel operation) to the pixels PX in a certain row. Perform the action. Typically, a correction period in which the characteristic correction operation is performed on the pixels PX in a certain row and a correction period in which the characteristic correction operation is performed on the pixels in the next row are partially overlapped. In this way, the effective display (light emission) period is longer than when the characteristic correction operation to the pixel PX in the next row is started after completing both the characteristic correction operation and the writing operation to the pixel PX in a certain row. It is possible to allocate sufficient time for both the characteristic correction operation and the writing operation while setting the time sufficiently long (the ratio of the effective display period to one display period is desirably 50% or more).

  Further, in this aspect, a separation period is provided in the correction period, and while the pixels PX in a certain row are separated from the video signal line DataN, the writing operation for the pixels PX in the previous row is performed. Therefore, without separately providing a reset signal line for supplying the reset signal Vrst, writing to the pixels PX in the correction period during which the characteristic correction operation is performed on the pixels PX in a certain row and the previous rows. The writing period for performing the operation can be overlapped. Therefore, it is possible to allocate a sufficient time for both the characteristic correction operation and the writing operation while setting the effective display period sufficiently long without increasing the number of wirings.

  Thus, according to this aspect, sufficient time can be allocated to both the characteristic correction operation and the writing operation. Further, according to this aspect, there is no increase in the number of wirings for realizing this. Therefore, according to this aspect, the display unevenness due to the variation between the pixels PX in the characteristics of the drive current control circuit can be sufficiently eliminated with a relatively small number of wires.

  Various modifications can be made to the driving method described with reference to FIG. This will be described with reference to FIGS.

  FIG. 5 is a diagram illustrating an example of a driving method that can be used in the display device 1 illustrated in FIG. 1. FIG. 5 is a diagram showing another example of a driving method that can be used in the display device 1 shown in FIG.

  5 and 6 illustrate the conduction states of the switches SW1 to SW3 in the correction period, the writing period, and the effective display period for the pixel PX in the (M-1) th row and the pixel PX in the Mth row. . In the figure, “ON / OFF” indicates that the switch may be either on or off. In addition, “RST” described in the column of “video signal / reset signal” indicates that the reset signal Vrst is supplied to the video signal line DataN, and “VideoM” indicates M rows for the video signal line DataN. It shows that the video signal Vsig corresponding to the eye pixel PX is supplied.

  As shown in FIG. 5, while the video signal Vsig corresponding to the pixel PX in the (M-1) th row, that is, VideoM-1, is supplied to the video signal line DataN, the pixel PX in the Mth row is for correction. The switch SW2 may be in an on state. That is, in the example described with reference to FIG. 4, the threshold cancellation operation is interrupted in the separation period, but the threshold cancellation operation can be continued in the separation period. Also in this case, the same effect as described above can be obtained.

  Further, in the driving method shown in FIG. 5, while the video signal Vsig corresponding to the pixel PX in the (M−1) th row, that is, VideoM−1, is supplied to the video signal line DataN, the pixel PX in the Mth row. In FIG. 6, the selection switch SW1 is turned off. However, as shown in FIG. 6, the selection switch SW1 of the pixel PX in the Mth row may be turned on during that period. That is, as shown in FIG. 6, the correction switch SW2 is turned off at the M-th pixel PX while the writing operation is being performed on the video signal line DataN with respect to the (M-1) -th pixel PX. In this state, even if the selection switch SW1 of the pixel PX in the Mth row is turned on during that period, the same effect as described above can be obtained.

  As described above, the driving method described with reference to FIG. 4 can be variously modified.

  Further, the driving method described above can also be used in a display device having a circuit configuration different from that shown in FIG.

  FIG. 7 is a plan view schematically showing a display device according to a modified example of this aspect. Here, an organic EL display device is illustrated as an example. FIG. 8 is a timing chart showing an example of a driving method that can be used in the display device 1 shown in FIG.

  The display device 1 shown in FIG. 7 does not include the second scanning signal line ScanMb, and each pixel PX includes a TFT SW having the same conductivity type as the correction switch SW2 as a selection switch SW1, in this case, a p-channel TFT. The display device 1 has the same structure as that of the display device 1 shown in FIG. 1 except that the gate that is the control terminal of the correction switch SW2 is connected to the first scanning signal line ScanMa. As shown in FIG. 8, the display device 1 does not generate the second scanning signal and the same method as described with reference to FIG. 4 except that the signal level of the first scanning signal is reversed. Can be driven.

  In the display device 1 shown in FIG. 7, the second scanning signal line ScanMb is omitted by connecting the gate, which is the control terminal of the correction switch SW2, to the first scanning signal line ScanMa. Therefore, compared to the display device 1 of FIG. 1, it is possible to allocate a sufficient time for both the characteristic correction operation and the writing operation while setting the effective display period sufficiently long with a smaller number of wires.

  In addition, this invention is not limited to the above-mentioned aspect, It can change further in the range which does not deviate from the summary. For example, in the previous embodiment, a specific circuit configuration is employed for the pixel, but other circuit configurations may be employed for the pixel. For example, n-channel TFTs or p-channel TFTs may be used as the switches SW1 to SW3. Further, other switching elements such as a transmission gate may be used as the switches SW1 to SW3.

  In the previous embodiment, the case where the characteristic correction circuit corrects variation in the threshold voltage Vth of the drive current control element TR has been described. However, the characteristic correction circuit corrects characteristic variation in the drive current control circuit. If it is, it is not necessary to correct the variation of the threshold voltage Vth of the drive current control element TR.

  In the above-described aspect, the video signal is written for each pixel row. However, the present invention is not limited to this, and writing may be performed for a plurality of rows at the same time.

  Further, in the above-described aspect, the case where the digital-analog conversion of the video signal is performed by the video signal line driver XDR formed on the substrate 4 has been described, but this conversion may be performed outside the organic EL panel 2.

  The video signal line driver XDR may supply an analog video signal to the corresponding video signal line DataN in a time division manner. Further, the power supply voltage supplied to the organic EL element OLED may be set for each emission color.

  Further, in the above-described embodiment, the transistor that uses the polysilicon as the active layer is described as the transistor that constitutes the pixel, but amorphous silicon may be used. In particular, when amorphous silicon is used, it is desirable to apply the present invention because it is important to secure a correction period.

  Further, in the above-described aspect, the organic EL display device 1 using the organic EL element OLED as the display element has been described, but other display elements are used as long as the optical characteristics change according to the magnitude of the flowing current. May be. That is, the above technique can be applied to a display device other than the organic EL display device, for example, a display device including a self-light emitting element such as a light emitting diode display device or a field emission display device.

  When an increase in the number of switches and an increase in the number of wirings are allowed in each pixel PX, the technique described below can be used for both the characteristic correction operation and the writing operation while setting the effective display period sufficiently long. Enough time can be allocated.

  FIG. 9 is a plan view schematically showing a display device according to a reference example. Here, an organic EL display device is illustrated as an example.

  The organic EL display device 1 includes an organic EL panel 2 and a controller 3 that controls the display operation of the organic EL panel 2.

  The organic EL panel 2 has, for example, a 17-inch XGA display area, and a plurality of pixels PX arranged in a matrix on a light-transmissive insulating substrate 4 such as a glass plate, and along the rows of these pixels PX. A plurality of scanning signal lines ScanMa, ScanMb, and ScanMc that extend, a plurality of video signal lines DataN that extend in a direction substantially orthogonal to the row of the pixels PX, and a scanning signal line ScanMa, ScanMb, and ScanMc, respectively. A scanning signal line driver YDR that sequentially drives and a video signal line driver XDR that drives the video signal line DataN are provided. The organic EL panel 2 is provided with a reset signal line RST independent of the video signal line DataN in a direction along the pixel column, that is, a direction substantially parallel to the video signal line DataN.

  Each pixel PX includes an organic EL element OLED that is a self-light-emitting element as a light-emitting element, and also includes a drive current control circuit and a characteristic correction circuit.

  The drive current control circuit includes a drive current control element TR, a selection switch SW1, and a capacitor C1. Here, as an example, a p-channel TFT is used for the drive current control element TR, and an n-channel TFT is used for the selection switch SW1. These TFTs use, for example, a polycrystalline silicon film as their active layers, and can be formed in the same process as the TFTs constituting the scanning signal line driver YDR and the video signal line driver XDR.

  The drive current control element TR is connected in series with the organic EL element OLED between the pair of power supply terminals VDD and VSS. The drive current control element TR outputs a drive current having a magnitude corresponding to the voltage between the control terminal and the power supply terminal VDD to the organic EL element OLED.

  The selection switch SW1 is connected between the video signal line DataN and the control terminal of the drive current control element TR. That is, the selection switch SW1 has a source connected to the video signal line DataN, a drain connected to a control terminal of the drive current control element TR via a capacitor C2, which will be described later, and a gate connected to the corresponding scanning signal line ScanMa. Has been. The selection switch SW1 switches conduction / non-conduction between the video signal line DataN and the terminal on the selection switch SW1 side of the capacitor C2 according to the first scanning signal supplied via the scanning signal line ScanMa.

  The capacitor C1 is connected between the power supply terminal VDD and the control terminal of the drive current control element TR. The capacitor C1 plays a role of holding the voltage between the control terminal of the drive current control element TR and the power supply terminal VDD substantially constant for a predetermined period.

  Specifically, the selection switch SW1 is connected to the video signal line DataN and the drive current control element TR by the first scanning signal supplied from the scanning signal line driver YDR via the scanning signal line ScanMa corresponding to the writing operation. A signal supplied from the video signal line driver XDR via the video signal line DataN, for example, the video signal Vsig (= 0 to 4V), is output to the node A when the control terminal is brought into conduction. The driving current control element TR supplies a driving current Id having a magnitude corresponding to the video signal Vsig output from the selection switch SW1 to the organic EL element OLED. The power supply terminals VDD and VSS are set to potentials of + 10V and 0V, for example.

  Here, the characteristic correction circuit is a threshold cancel circuit, and includes a correction switch SW2, an output control switch SW3, a reset switch SW4, and a capacitor C2. Here, as an example, p-channel TFTs are used for the correction switch SW2, the output control switch SW3, and the reset switch SW4.

  The reset switch SW4 is connected between a reset signal line RST that supplies a reset signal Vrst (= 8V) and a control terminal of the drive current control element TR. That is, the reset switch SW4 has a source connected to the reset signal line RST, a drain connected to the control terminal of the drive current control element TR via the capacitor C2, and a gate connected to the scanning signal line ScanMb. The reset switch SW4 switches conduction / non-conduction between the reset signal line RST and the terminal on the selection switch SW1 side of the capacitor C2 according to the second scanning signal supplied via the scanning signal line ScanMb.

  The correction switch SW2 is connected between the output terminal and the control terminal of the drive current control element TR. The correction switch SW2 switches conduction / non-conduction between the output terminal of the drive current control element TR and the control terminal according to the second scanning signal supplied via the scanning signal line ScanMb.

  The output control switch SW3 is connected in series between the output terminal of the drive current control element TR and the organic EL element OLED. The output control switch SW3 switches conduction / non-conduction between the output terminal of the drive current control element TR and the organic EL element OLED according to the third scanning signal supplied via the scanning signal line ScanMc.

  The capacitor C2 is connected between the selection switch Sw1 and the control terminal of the drive current control element TR. Capacitor C2 prevents the movement of charges between nodes A and B and enables the potential change of node B corresponding to the potential change of node A.

  The organic EL element OLED has a structure in which an organic material layer including a light emitting layer which is a thin film including a red, green, or blue luminescent organic compound is interposed between a cathode and an anode. The organic EL element OLED generates excitons by injecting electrons and holes into an organic layer and recombining them, and emits light by light emission generated when the excitons are deactivated.

  The organic thin film layer may have a structure in which three layers of an anode buffer layer, a light emitting layer, and a cathode light emitting layer are laminated, or a two-layer or single-layer structure in which these are functionally combined.

  The controller 3 is formed on a printed circuit board arranged outside the organic EL panel 2 and controls operations of the scanning signal line driver YDR and the video signal line driver XDR. The controller 3 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signals. The scanning control signal and the horizontal scanning control signal are supplied to the scanning signal line driver YDR and the video signal line driver XDR, respectively, and the digital video signal is supplied to the video signal line driver XDR in synchronization with the horizontal and vertical scanning timings.

  The video signal line driver XDR converts the digital video signal into an analog format under the control of the horizontal scanning control signal in each horizontal scanning period, and converts the video signal Vsig obtained thereby into a plurality of video signal lines DataN. In contrast, supply in parallel.

  The scanning signal line driver YDR performs, for example, a reset period + in each display period (= 1 frame period + vertical blanking period = correction period + writing period + effective display period) under the control of the vertical scanning control signal. A first scanning signal is sequentially supplied to the plurality of scanning signal lines ScanMa to change the selection switch Sw1 in the order of OFF state → ON state → OFF state corresponding to the threshold cancellation period, writing period, and effective display period. In this example, the correction period is equal to the sum of the reset period and the threshold cancellation period. Further, here, after the first scanning signal supplied to the scanning signal line ScanMa changes to a level at which the selection switch Sw1 is turned on corresponding to the first connection period, it again corresponds to the first connection period. A period until the level of the selection switch Sw1 is changed to the ON state is determined as one horizontal scanning period (1H).

  The selection switch SW1 in each row conducts between the video signal line DataN and the node A in the writing period only once per display period by the first scanning signal supplied from the corresponding scanning signal line ScanMa. The other period is non-conductive. The drive current control element TR supplies the drive current Id corresponding to the video signal Vsig supplied via the video signal line DataN during the writing period in which the selection switch SW1 is in a conductive state during the effective display period ( In the light emission period), the organic EL element OLED is supplied. These video signals Vsig are updated every display period, which is a video signal update cycle.

  Also, the scanning signal line driver YDR, for example, the correction period and the writing period + effective display in each display period under the control of the vertical scanning control signal, as described for the scanning signal line ScanMa. A second scanning signal for changing the correction switch SW2 and the reset switch SW4 from the on state to the off state corresponding to the period is sequentially supplied to the plurality of scanning signal lines ScanMb. The correction switch SW2 in each row is connected between the output terminal and the control terminal of the drive current control element TR in the correction period only once per display period by the second scanning signal supplied from the corresponding scanning signal line ScanMb. Is made conductive, and is made non-conductive in other periods. Similarly, the reset switch SW4 of each row conducts between the reset signal line RST and the node A in the correction period only once per display period by the second scanning signal supplied from the corresponding scanning signal line ScanMb. It is made non-conductive during other periods.

  Further, as described with respect to the scanning signal line ScanMa, the scanning signal line driver YDR performs, for example, a reset period, a threshold cancellation period + writing in each display period under the control of the vertical scanning control signal. A third scanning signal for changing the output control switch SW3 from the on state to the off state to the on state corresponding to the period and the effective display period is sequentially supplied to the plurality of scanning signal lines ScanMc. The output control switch SW3 of each row is driven by the driving current control element TR and the organic EL element in the reset period and the effective display period only once per display period by the third scanning signal supplied from the corresponding scanning signal line ScanMc. Conduction between the OLED and non-conduction during other periods.

FIG. 10 is an equivalent circuit diagram of the pixel PX of the display device 1 shown in FIG.
As described above, each pixel PX includes a characteristic correction circuit in addition to the organic EL element OLED and the drive current control circuit. The drive current control circuit includes a drive current control element TR, a selection switch SW1, and a capacitor C1, and the characteristic correction circuit includes a correction switch SW2, an output control switch SW3, a reset switch SW4, and a capacitor C2. It has. The switches SW2 to SW4 have the relationship shown in FIG. 11 in order to initialize the control voltage of the drive current control element TR to a level substantially equal to the threshold voltage Vth of the drive current control element TR in the correction period prior to the writing period. Is turned on / off.

FIG. 11 is a diagram illustrating an example of a driving method of the pixel PX illustrated in FIG.
As shown in FIG. 11, the correction period includes a reset period and a threshold cancellation period.

  In the reset period, the voltage between the input terminal and the control terminal of the drive current control element TR is set to be larger than the threshold voltage Vth. Specifically, the selection switch SW1 is turned off and the switches SW2 to SW4 are turned on. By this operation, the potential of the node A is raised by the reset signal Vrst supplied via the reset switch SW4, and the potentials of the nodes B and C are lowered by the discharge current flowing via the correction switch SW2.

  In the subsequent threshold cancellation period, the output control switch SW3 is set to the off state while the selection switch SW1 is maintained in the off state. As a result, the potential of the node B rises to a level substantially equal to the threshold voltage Vth of the drive current control element TR due to the charging current flowing through the correction switch SW2. At this time, the reset signal Vrst is supplied to the electrode on the node A side of the capacitor C2.

  In the writing period, the selection switch SW1 is turned on and the switches SW2 to SW4 are turned off. As a result, the video signal Vsig is supplied to the node A via the selection switch SW1 instead of the reset signal Vrst supplied via the reset switch SW4. As a result, the potential of the node B becomes substantially equal to the sum of the threshold voltage Vth and the video signal Vsig.

  In the effective display period, the output control switch SW3 is turned on, and the switches SW1, SW2, and SW4 are turned off. As a result, the drive current Id is supplied to the organic EL element OLED via the output control switch SW3. Here, the drive current Id is determined by the potential difference between the reset signal Vrst and the video signal Vsig, and even if the threshold voltage Vth of the drive current control element TR varies between the pixels PX, such variation is caused. Can have an effect on the drive current Id.

In the present reference example, the display device 1 is driven as described below.
FIG. 12 is a timing chart illustrating an example of a driving method that can be used in the display device 1 illustrated in FIG. 9. Reference numerals Clka and Clkb shown in FIG. 12 indicate clock signals, Starta and Startb indicate start signals, and Video indicates a video signal, both of which are signals output by the controller 3. Further, reference numerals ScanMa, ScanMb, and ScanMc shown in FIG. 12 indicate scanning signals that the scanning signal line driver YDR outputs to the scanning signal lines ScanMa, ScanMb, and ScanMc, respectively.

  The scanning signal line driver YDR generates a first pulse having a width of one horizontal period (Tw-Starta) corresponding to each horizontal scanning period from the start signal Starta and the clock signal Clka, and sequentially transfers the first pulse to the next stage. A shift register that outputs the first pulse as the first scanning signal to the corresponding scanning signal line, and a width (Tw-Startb) that is an integral multiple of one horizontal scanning period corresponding to each horizontal scanning search period from the start signal Startb and the clock signal Clka. And a shift register that sequentially outputs the second pulse of each stage to the corresponding scanning signal line as a second scanning signal. The scanning signal line driver YDR sequentially outputs the first pulse as the first scanning signal to the first scanning signal line ScanMa, and sequentially outputs the second pulse as the second scanning signal to the second scanning signal line ScanMb. Further, the scanning signal line driver YDR generates a third scanning signal from the second pulse and the clock signal Clkb, and sequentially outputs the third scanning signal to the third scanning signal line ScanMc.

  Specifically, in the reset period, the scanning signal line driver YDR supplies the scanning signal line ScanMa with a scanning signal having a non-selection level (here, Low level) and ScanMb, ScanMc being a selection level (here, Low level). In the threshold cancellation period, the scanning signal line driver YDR supplies a scanning signal at a low level to the scanning signal lines ScanMa and ScanMb, and supplies a scanning signal at a non-selection level (here, a high level) to the scanning signal line ScanMc. In the writing period, the scanning signal line driver YDR supplies the scanning signal line ScanMa with a selection level (here, High level) and ScanMb and ScanMc with a non-selection level (here, High level). In the effective display (light emission) period, the scanning signal line driver YDR supplies a low level scanning signal to the scanning signal lines ScanMa and ScanMc, and supplies a high level scanning signal to the scanning signal line ScanMb.

  In this reference example, the scanning signal line driver YDR starts the characteristic correction operation (= reset operation + threshold cancel operation) for a pixel PX in a certain row, and is n times one horizontal period (n is an integer equal to or greater than 1). ), The characteristic correction operation for the pixel PX in the next row is started. That is, the writing period in which the writing operation is performed on the pixels PX in a certain row and the correction period in which the characteristic correction operation is performed on the pixels in the next row are at least partially overlapped. In this way, the effective display (light emission) period is longer than when the characteristic correction operation to the pixel PX in the next row is started after completing both the characteristic correction operation and the writing operation to the pixel PX in a certain row. It is possible to allocate sufficient time for both the characteristic correction operation and the writing operation while setting the time sufficiently long (the ratio of the effective display period to one display period is desirably 50% or more).

  In this reference example, a reset signal line RST for supplying the reset signal Vrst is provided separately from the video signal line DataN for supplying the video signal Vsig. If the wiring for supplying the reset signal Vrst is made independent of the wiring for supplying the video signal Vsig as described above, the reset signal Vrst is caused by the wiring capacity during the transition from the light emission operation to the characteristic correction operation. It is possible to prevent the supply to the node A from being delayed. That is, according to this reference example, unlike the case where the video signal line DataN for supplying the video signal Vsig is used together with the supply of the reset signal Vrst, when the operation of the pixel PX is switched from the light emission operation to the characteristic correction operation. The potential at the node A immediately changes to a level equal to the reset signal Vrst. Therefore, according to the present reference example, it is difficult to completely initialize the control voltage of the drive current control element TR due to the relatively long time required for the potential of the node A to be stabilized.

  Thus, according to the present reference example, sufficient time can be allocated to both the characteristic correction operation and the writing operation. In addition, according to this reference example, the potential of the node A can be quickly changed to a level equal to the reset signal Vrst when switching from the light emission operation to the characteristic correction operation. Therefore, according to this reference example, it is possible to sufficiently eliminate display unevenness due to variation in the characteristics of the drive current control circuit between the pixels PX.

  The correction period is appropriately set depending on the size and definition of the organic EL panel, but is preferably 50 μsec or more in the organic EL panel of this aspect class. Here, the writing period (that is, one horizontal period) is set to about 21 μsec, whereas the correction period is about 50 μsec, and the correction period may be set longer than the length of one horizontal period. Accordingly, in this reference example, as shown in FIG. 12, a correction period for performing the characteristic correction operation on the pixel PX in a certain row and a correction period for performing the characteristic correction operation on the pixel PX in the next row are partially divided. By superimposing, the characteristic correction can be performed over a plurality of horizontal scanning periods, and a sufficient correction period can be obtained without reducing the light emission time.

  In the present reference example, the reset signal line RST is provided along the direction along the pixel column, that is, along the direction parallel to the video signal line DataN. According to such a structure, the reset signal Vrst can be supplied from the separate reset signal line RST to the pixels PX included in the pixel row during the characteristic correction operation for the selected pixel row. In this case, the reset signal line can be divided by the number of the reset signal lines RST without being concentrated on one wiring as compared with the case where the reset signal is supplied in the direction along the pixel row. The occurrence of a voltage drop in the RST can be suppressed. Then, crosstalk between pixels caused by this voltage drop is improved, and a more uniform image display becomes possible. In particular, a good display operation can be performed even when the number of pixels increases and the number of scanning lines increases.

  The technique described above as a reference example is not limited to the display device 1 shown in FIG. 9 and the driving method shown in FIG. 12, and can be variously modified.

  For example, instead of the structure that can supply the reset signal Vrst from the video signal line driver XDR shown in FIG. 9, a structure that can supply the reset signal Vrst from the reset signal supply terminal RESET as shown in FIG. 13 may be adopted. . By forming a circuit for supplying a reset signal on the PCB, the manufacturing yield of the array substrate can be improved. Moreover, the area of the frame part which is a non-display area | region of an array substrate can be reduced, and a narrow frame can be achieved. In addition, the reset signal can be easily adjusted.

  Further, as shown in FIG. 14, the reset signal line RST may be arranged in a direction along the pixel row, that is, in parallel with the scanning signal line DataN. The display device 1 adopting such a structure can be driven by the same method as described above.

  Further, as shown in FIG. 15, it is possible to arrange the reset signal line RST in parallel to the pixel row and share the reset signal line RST between adjacent pixel rows. In this way, the number of wirings arranged in the arrangement direction of the pixel rows can be reduced. In particular, in an organic EL display device having a display surface on the substrate side on which the wirings are formed, the emission extraction efficiency can be further improved. Is possible.

  More specifically, the reset signal line RST is arranged in parallel to the pixel row, and for example, the scanning signal lines ScanMb and ScanMc that are located in the even-numbered rows are omitted, and the pixels PX2 in the even-numbered rows and their pixels PX2 are omitted. The scanning signal lines ScanMb and ScanMc (M is an odd number here) and the reset signal line RST are shared with the pixel PX1 in the upper row. The circuit configuration of the pixels PX1 and PX2 is the same as the circuit configuration of the pixel PX.

  According to this structure, the number of wirings necessary for supplying the reset signal Vrst and the second and third scanning signals and the area occupied by the wirings in the display region can be reduced. Therefore, it is easy to increase the size and definition of the display device 1.

  When the structure shown in FIG. 15 is adopted, the characteristic correction operation for the pixels PX1 and PX2 is performed every two rows, and the writing operation is performed every row. Specifically, as shown in FIG. 16, the characteristic correction operation is simultaneously performed on the pixel PX2 in the 2n-th row (n is a natural number) and the pixel PX1 in the 2n-1 row, and the characteristic correction operation on them is performed. Is completed, the characteristic correction operation is simultaneously performed on the pixel PX2 in the 2 (n + 1) th row and the pixel PX1 in the 2 (n + 1) -1th row. Further, after the characteristic correction operation for the pixel PX2 in the 2n-th row and the pixel PX1 in the 2n-1-th row is completed, the pixel PX2 in the 2 (n + 1) -th row and the pixel PX1 in the 2 (n + 1) -1-th row are processed. In parallel with the characteristic correction operation, a writing operation is sequentially performed for each pixel on the 2n-th row pixel PX2 and the 2n-1-th row pixel PX1.

  Thus, in the present reference example, the characteristic correction operation for the pixel PX2 in the 2n-th row and the characteristic correction operation for the pixel PX1 in the 2n-1 row are performed simultaneously. In addition, in this reference example, the correction period for the pixel PX2 in the 2n-th row and the writing period for the pixel PX1 in the 2n-1th row do not overlap, but the correction period for the pixel PX2 in the 2n-th row and the 2n + 1-th row Is overlapped with the writing period for the pixel PX1. Therefore, sufficient time can be allocated to both the characteristic correction operation and the writing operation. In the present reference example, similarly to the examples shown in FIGS. 9, 13 and 14, the reset signal line RST for supplying the reset signal Vrst separately from the video signal line DataN for supplying the video signal Vsig. Therefore, when switching from the light emission operation to the characteristic correction operation, the potential of the node A can be quickly changed to a level equal to the reset signal Vrst. Therefore, in this reference example, the same effect as described in the above reference example can be obtained.

  Further, as shown in FIG. 17, the reset signal line RST may be shared with a wiring connected to the power supply terminal VDD.

  According to this structure, since the reset signal line RST can be shared with a part of the wiring that connects the organic EL element OLED and the power supply terminal VDD, the area occupied by the wiring in the display region can be reduced. However, in this structure, since the reset signal Vrst is equal to the power supply voltage VDD, the maximum value of the video signal Vsig needs to be substantially equal to the power supply voltage VDD.

  Further, as shown in FIG. 18, the reset signal lines RST may be arranged in a lattice shape, and the reset signal lines RST crossing each other may be connected at the intersections.

  According to such a structure, the same effect as described in the above reference example can be obtained. In addition, according to this structure, since the reset signal is supplied from the wiring arranged in a lattice pattern in the display surface, the voltage drop in the reset signal line RST can be further suppressed. For this reason, variations in the voltage drop that occurs between the reset signal lines RST are further reduced, and even if a voltage drop occurs, it can be suppressed from being visually recognized as crosstalk, and a more uniform display is possible.

  As described above, when at least partially overlapping the writing period in which the writing operation is performed on the pixels PX in a certain row and the correction period in which the characteristic correcting operation is performed on the pixels in the next row, It is possible to allocate sufficient time for both the correction operation and the writing operation. In addition, if the video signal supply and the reset signal supply to the pixels are performed by independent wirings, for example, when the load increases due to an increase in size or the horizontal scanning period must be shortened due to an increase in definition. Even so, a sufficient correction period can be secured. Furthermore, when a reset signal is supplied from a plurality of wirings to a plurality of pixels that simultaneously perform the characteristic correction operation, a voltage drop can be suppressed, so that more uniform display is possible.

  The technique according to the reference example can be further modified. For example, in the previous reference example, a specific circuit configuration is employed for the pixel PX, but other circuit configurations may be employed for the pixel PX. For example, n-channel TFTs or p-channel TFTs may be used as the switches SW1 to SW4. Further, other switching elements such as a transmission gate may be used as the switches SW1 to SW4. For example, a transmission gate may be used as the reset switch SW4, and on / off of the reset switch SW4 may be controlled by a second scanning signal having a polarity opposite to that described above.

  In the above reference example, the case where the characteristic correction circuit corrects the variation in the threshold voltage Vth of the drive current control element TR has been described. However, the characteristic correction circuit corrects the characteristic variation of the drive current control circuit. If it is to be performed, the variation correction limited to the threshold voltage Vth of the drive current control element TR may not be performed.

  In the structure shown in FIG. 15, one reset signal line RST is shared by two rows of pixels PX1 and PX2, but one or more reset signal lines RST may be shared by three or more rows of pixels. .

  In the above-described reference example, the video signal is written for each pixel row. However, the present invention is not limited to this, and a plurality of rows may be simultaneously written.

  Further, in the above-described reference example, the case where the correction switch SW2 and the reset switch SW4 are controlled using the common scanning signal line ScanMb has been described. However, their on / off is controlled using independent scanning signal lines. May be. By controlling in this way, it is possible to further stabilize the operation and improve the display quality.

  In the above-described reference example, the case where the digital-analog conversion of the video signal is performed by the video signal line driver XDR formed on the glass substrate has been described. However, this conversion may be performed outside the organic EL panel 2. .

  The video signal line driver XDR may supply an analog video signal to the corresponding video signal line DataN in a time division manner. Further, the power supply voltage supplied to the organic EL element may be set for each emission color.

  Further, in the above-described reference example, the transistor that uses the polysilicon as the active layer is described as the transistor constituting the pixel. However, amorphous silicon may be used. In particular, when amorphous silicon is used, it is important to apply the technique according to the above reference example because it is important to secure a correction period.

  Furthermore, in the above-described reference example, the organic EL display device 1 using the organic EL element OLED as the display element has been described. However, other display elements may be used as long as the optical characteristics change according to the magnitude of the flowing current. May be. That is, the above technique can be applied to a display device other than the organic EL display device, for example, a display device including a self-light emitting element such as a light emitting diode display device or a field emission display device.

1 is a plan view schematically showing a display device according to one embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a pixel of the display device shown in FIG. 1. FIG. 3 is a diagram illustrating an example of a method for driving the pixel illustrated in FIG. 2. 4 is a timing chart illustrating an example of a driving method that can be used in the display device illustrated in FIG. 1. FIG. 4 is a diagram illustrating an example of a driving method that can be used in the display device illustrated in FIG. 1. FIG. 6 is a diagram showing another example of a driving method that can be used in the display device shown in FIG. 1. The top view which shows schematically the display apparatus which concerns on the modification of the form of FIG. 8 is a timing chart illustrating an example of a driving method that can be used in the display device illustrated in FIG. 7. The top view which shows schematically the display apparatus which concerns on a reference example. FIG. 10 is an equivalent circuit diagram of a pixel of the display device shown in FIG. 9. FIG. 11 illustrates an example of a method for driving the pixel illustrated in FIG. 10. 10 is a timing chart illustrating an example of a driving method that can be used in the display device illustrated in FIG. 9. FIG. 10 is a plan view schematically showing a display device according to a modification of the embodiment shown in FIG. 9. FIG. 10 is a plan view schematically showing a display device according to a modification of the embodiment shown in FIG. 9. FIG. 10 is a plan view schematically showing a display device according to a modification of the embodiment shown in FIG. 9. FIG. 16 is a timing chart illustrating an example of a driving method that can be used in the display device illustrated in FIG. 15. FIG. 10 is a plan view schematically showing a display device according to a modification of the embodiment shown in FIG. 9. FIG. 10 is a plan view schematically showing a display device according to a modification of the embodiment shown in FIG. 9.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Organic EL display device, 2 ... Organic EL panel, 3 ... Controller, 4 ... Light transmissive insulating substrate, PX ... Pixel, PX1 ... Pixel, PX2 ... Pixel, YDR ... Scanning signal line driver, XDR ... Video signal line driver ScanMa ... scanning signal line, ScanMb ... scanning signal line, ScanMc ... scanning signal line, DataN ... video signal line, RST ... reset signal line, OLED ... organic EL element, TR ... drive current control element, SW1 ... selection switch, SW2 ... correction switch, SW3 ... output control switch, SW4 ... reset switch, C1 ... capacitor, C2 ... capacitor, VDD ... power supply terminal, VSS ... power supply terminal, RESET ... reset signal supply terminal, A ... node, B ... node , C ... node.

Claims (4)

  1. A scanning signal line, a video signal line intersecting with the scanning signal line, and a pixel disposed in the vicinity of the intersection of the scanning signal line and the video signal line,
    Each of the pixels includes a drive current control element that includes a control terminal, a first terminal connected to the first power supply terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage therebetween. A first capacitor connected between the first terminal and the control terminal, an input terminal is connected to the video signal line, and a conduction state thereof corresponds to a scanning signal supplied via the scanning signal line. A switching switch for switching, a second capacitor connected between the output terminal of the selection switch and the control terminal, a correction switch connected between the second terminal and the control terminal, An output control switch having an input terminal connected to the second terminal, and an optical characteristic is changed according to the magnitude of a current that is connected between the output terminal of the output control switch and the second power supply terminal. Departure And a display device as an element,
    In the writing period, a writing operation for supplying a video signal from the video signal line to the selection switch side terminal of the second capacitor through the selection switch is performed.
    In the effective display period following the writing period, the selection switch and the correction switch are set in a non-conductive state and the output control switch is set in a conductive state, and the drive current is supplied to the display element.
    In the correction period prior to the writing period, the output control switch is turned off and the correction switch is turned on, and in this state, the second switch from the video signal line through the selection switch. by supplying a reset signal to the selection switch side terminal of the capacitor, it performs a characteristic correction operation including providing a correction signal that reflects the characteristics of the drive current control element to the control terminal,
    Nonconductive sequentially performs for each row of the pixels, respectively, said at least one of the selection switches and the correction switch of the pixels is performed before Symbol characteristic correction operation of said write operation and said characteristic correction operation A separation period to be in a state is provided within the correction period and after the start of supply of the reset signal, and with respect to the pixels in the previous row within the separation period for the pixels in a certain row An active matrix display device configured to perform the writing operation.
  2.   2. The active matrix type according to claim 1, wherein in the separation period, the selection switch is set in a non-conductive state while the correction switch of the pixel performing the characteristic correction operation is in a conductive state. Display device.
  3. In the separation period, both the selection switch and the correction switch of the pixel performing the characteristic correction operation are in a non-conductive state,
    The selection switch of the pixel is performing the characteristic correction work with in the respective front Kiho positive interval switching to the reset signal the signal supplied from the video signal from the video signal line after said separation period 2. The active matrix display device according to claim 1, wherein both the correction switch and the correction switch are turned on again. 3.
  4.   4. The active matrix display device according to claim 3, wherein the selection switch and the correction switch of each of the pixels are controlled in conduction state by a control signal supplied via the same control line. .
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