JP2003133949A5 - - Google Patents

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Publication number
JP2003133949A5
JP2003133949A5 JP2001324756A JP2001324756A JP2003133949A5 JP 2003133949 A5 JP2003133949 A5 JP 2003133949A5 JP 2001324756 A JP2001324756 A JP 2001324756A JP 2001324756 A JP2001324756 A JP 2001324756A JP 2003133949 A5 JP2003133949 A5 JP 2003133949A5
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JP
Japan
Prior art keywords
signal
frequency
value
control signal
current value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001324756A
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English (en)
Japanese (ja)
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JP2003133949A (ja
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Publication date
Application filed filed Critical
Priority to JP2001324756A priority Critical patent/JP2003133949A/ja
Priority claimed from JP2001324756A external-priority patent/JP2003133949A/ja
Priority to US10/106,257 priority patent/US6667640B2/en
Publication of JP2003133949A publication Critical patent/JP2003133949A/ja
Publication of JP2003133949A5 publication Critical patent/JP2003133949A5/ja
Pending legal-status Critical Current

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JP2001324756A 2001-10-23 2001-10-23 Ｐｌｌ回路 Pending JP2003133949A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001324756A JP2003133949A (ja) 2001-10-23 2001-10-23 Ｐｌｌ回路
US10/106,257 US6667640B2 (en) 2001-10-23 2002-03-27 Phase locked loop circuit having a wide oscillation frequency range for reducing jitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001324756A JP2003133949A (ja) 2001-10-23 2001-10-23 Ｐｌｌ回路

Publications (2)

Publication Number Publication Date
JP2003133949A JP2003133949A (ja) 2003-05-09
JP2003133949A5 true JP2003133949A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 2005-06-30

Family

ID=19141431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001324756A Pending JP2003133949A (ja) 2001-10-23 2001-10-23 Ｐｌｌ回路

Country Status (2)

Country Link
US (1) US6667640B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JP2003133949A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW563318B (en) * 2002-05-20 2003-11-21 Via Optical Solution Inc Timing recovery circuit and method
US6836167B2 (en) * 2002-07-17 2004-12-28 Intel Corporation Techniques to control signal phase
US6977959B2 (en) * 2003-01-17 2005-12-20 Xilinx, Inc. Clock and data recovery phase-locked loop
US6952124B2 (en) * 2003-09-15 2005-10-04 Silicon Bridge, Inc. Phase locked loop circuit with self adjusted tuning hiep the pham
JP4651298B2 (ja) * 2004-04-08 2011-03-16 三菱電機株式会社 周波数自動補正ｐｌｌ回路
US7161970B2 (en) * 2004-09-10 2007-01-09 Ftd Solutions Pte, Ltd. Spread spectrum clock generator
JP4519746B2 (ja) * 2005-09-22 2010-08-04 ローム株式会社 クロック生成回路、およびそれを搭載した電子機器
KR100839499B1 (ko) * 2006-12-22 2008-06-19 삼성전자주식회사 딜레이 제어 장치 및 방법
JP4768645B2 (ja) * 2007-02-16 2011-09-07 パナソニック株式会社 Ｐｌｌ回路、およびそれを備えた無線装置
GB0705544D0 (en) * 2007-03-22 2007-05-02 Nokia Corp Radio receiver or transmitter and method for reducing an IQ gain imbalance
KR100880924B1 (ko) * 2007-12-20 2009-02-04 주식회사 하이닉스반도체 직류 대 직류 전압 변환 장치
US8373460B2 (en) * 2011-03-28 2013-02-12 Freescale Semiconductor, Inc. Dual loop phase locked loop with low voltage-controlled oscillator gain
US9252791B1 (en) * 2014-12-22 2016-02-02 Freescale Semiconductor,Inc. Phase locked loop and method for generating an oscillator signal
TWI668965B (zh) * 2018-06-05 2019-08-11 円星科技股份有限公司 時脈產生電路及時脈產生方法
CN109656304B (zh) * 2018-12-13 2021-02-12 成都芯源系统有限公司 电流产生电路及其霍尔电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334952A (en) * 1993-03-29 1994-08-02 Spectralink Corporation Fast settling phase locked loop
EP0929157A4 (en) * 1997-07-24 2002-07-17 Mitsubishi Electric Corp PLL FREQUENCY SYNTHETIZER AND METHOD FOR CONTROLLING THE PLL FREQUENCY SYNTHETIZER
JP3185735B2 (ja) 1997-12-08 2001-07-11 日本電気株式会社 Ｐｌｌ回路
US6308055B1 (en) * 1998-05-29 2001-10-23 Silicon Laboratories, Inc. Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications
US6329872B1 (en) * 1998-08-14 2001-12-11 Nortel Networks Limited Charge pump circuit for a phase locked loop

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