JP2003069201A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2003069201A
JP2003069201A JP2001256493A JP2001256493A JP2003069201A JP 2003069201 A JP2003069201 A JP 2003069201A JP 2001256493 A JP2001256493 A JP 2001256493A JP 2001256493 A JP2001256493 A JP 2001256493A JP 2003069201 A JP2003069201 A JP 2003069201A
Authority
JP
Japan
Prior art keywords
copper
plating layer
boron
layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001256493A
Other languages
Japanese (ja)
Inventor
Hiroshi Tsukamoto
弘志 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001256493A priority Critical patent/JP2003069201A/en
Publication of JP2003069201A publication Critical patent/JP2003069201A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that peeling occurs between a wiring layer and a copper plated layer, or swelling is produced in the copper plated layer. SOLUTION: This wiring board is formed by adhering a wiring layer 2 in which electrodes of an electronic part 3 are connected to an insulation substrate 1 by means of a low-melting-point soldering material 5. A copper-boron plated layer 6 containing more than 0.3 wt.% boron, a copper plated layer 7, and a gold plated layer 8 are adhered in sequence to the surface of an area where at least the electrodes of the electronic part 3 in the wiring layer 2 are connected by means of the soldering material 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を収容
するための半導体素子収納用パッケージや混成集積回路
基板等に用いられる配線基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a semiconductor element housing package for housing a semiconductor element, a hybrid integrated circuit board and the like.

【0002】[0002]

【従来の技術】従来、半導体素子収納用パッケージや混
成集積回路基板等に用いられる配線基板は、一般に、酸
化アルミニウム質焼結体や窒化アルミニウム質焼結体等
の電気絶縁材料から成る絶縁基体と、該絶縁基体の表面
および内部に被着されたタングステン、モリブデン、マ
ンガン等の金属材料から成る配線層とにより形成されて
おり、絶縁基体の表面に半導体素子や容量素子、抵抗器
等の電子部品を搭載するとともに該電子部品の各電極を
配線層に錫−鉛半田等の低融点ロウ材を介して電気的に
接続するようになっている。
2. Description of the Related Art Conventionally, a wiring board used for a package for accommodating semiconductor elements, a hybrid integrated circuit board, or the like generally has an insulating base made of an electrically insulating material such as an aluminum oxide sintered body or an aluminum nitride sintered body. A wiring layer made of a metal material such as tungsten, molybdenum, manganese or the like deposited on the surface and inside of the insulating base, and on the surface of the insulating base, an electronic component such as a semiconductor element, a capacitive element, or a resistor. And each electrode of the electronic component is electrically connected to the wiring layer via a low melting point brazing material such as tin-lead solder.

【0003】かかる配線基板は、配線層の所定部位を外
部電気回路基板の配線導体に錫−鉛半田等の低融点ろう
材を介し接続することによって外部電気回路基板上に実
装され、同時に配線基板に搭載されている電子部品の各
電極も所定の外部電気回路に電気的に接続されることと
なる。
Such a wiring board is mounted on the external electric circuit board by connecting a predetermined portion of the wiring layer to a wiring conductor of the external electric circuit board through a low melting point brazing material such as tin-lead solder, and at the same time, the wiring board. Each electrode of the electronic component mounted on the board is also electrically connected to a predetermined external electric circuit.

【0004】また前記配線基板は、通常、配線層の露出
表面に銅めっき層および金めっき層が順次被着されてお
り、該銅めっき層によって配線層の電気抵抗を低く、か
つ配線層に対する低融点ロウ材の接合を良好としてお
り、また金めっき層によって配線層及び銅めっき層の酸
化腐蝕を有効に防止している。
In addition, the wiring board usually has a copper plating layer and a gold plating layer sequentially deposited on the exposed surface of the wiring layer, and the copper plating layer lowers the electrical resistance of the wiring layer and lowers the wiring layer. The melting point brazing material is bonded well, and the gold plating layer effectively prevents oxidative corrosion of the wiring layer and the copper plating layer.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来の配線基板においては、銅めっき層を形成している銅
の結晶粒の平均粒径が一般に約1μmであり、タングス
テン、モリブデン、マンガン等の金属材料から成る配線
層表面の凹凸径(凹部:約1μm)に比べて大きい。そ
のため配線層表面に銅めっき層を被着させても銅めっき
層は配線層表面の凹部内に十分入り込まずに配線層表面
と銅めっき層との間に多数の空隙部が形成されてしま
い、その結果、銅めっき層と配線層との密着強度が弱く
なり、外力印加によって銅めっき層が配線層より容易に
剥離したり、配線層表面と銅めっき層との間の空隙部に
入り込んでいる気体が配線層に電子部品の電極を低融点
ロウ材を介して接続する際の熱等によって大きく膨張
し、銅めっき層にフクレ等が発生してしまうという欠点
を有していた。
However, in the above-mentioned conventional wiring board, the average grain size of the crystal grains of copper forming the copper plating layer is generally about 1 μm, and metals such as tungsten, molybdenum and manganese are included. It is larger than the uneven diameter (recess: approximately 1 μm) on the surface of the wiring layer made of a material. Therefore, even if a copper plating layer is deposited on the surface of the wiring layer, the copper plating layer does not sufficiently enter into the concave portion of the surface of the wiring layer, and many voids are formed between the wiring layer surface and the copper plating layer, As a result, the adhesion strength between the copper plating layer and the wiring layer is weakened, and the copper plating layer is easily separated from the wiring layer by the application of an external force, or enters into the void between the wiring layer surface and the copper plating layer. The gas has a drawback in that it greatly expands due to heat or the like when connecting an electrode of an electronic component to a wiring layer via a low melting point brazing material, and blister or the like is generated in the copper plating layer.

【0006】本発明は上記従来の欠点に鑑み案出された
もので、その目的は配線層と銅めっき層との間に剥離が
発生したり銅めっき層にフクレ等が生じるのを有効に防
止し、配線層に銅めっき層及び金めっき層を強固に被着
させることによって配線層に電子部品の電極を低融点ロ
ウ材を介して強固に取着接続することができる配線基板
を提供することにある。
The present invention has been devised in view of the above-mentioned conventional drawbacks, and its purpose is to effectively prevent peeling between the wiring layer and the copper plating layer or blistering or the like in the copper plating layer. Then, by providing a copper plating layer and a gold plating layer firmly on the wiring layer, an electrode of an electronic component can be firmly attached and connected to the wiring layer via a low melting point brazing material. It is in.

【0007】[0007]

【課題を解決するための手段】本発明は、絶縁基体に電
子部品の電極が低融点ロウ材を介して接続される配線層
を被着形成してなる配線基板であって、前記配線層のう
ち少なくとも電子部品の電極が低融点ロウ材を介して接
続される領域の表面に、ホウ素の含有量が0.3重量%
以上の銅−ホウ素めっき層と、銅めっき層と、金めっき
層を順次被着させたことを特徴とするものである。
SUMMARY OF THE INVENTION The present invention is a wiring board in which an electrode of an electronic component is adhered and formed on an insulating substrate through a low melting point brazing material. At least 0.3% by weight of boron is contained on the surface of the region where the electrode of the electronic component is connected through the low melting point brazing material.
The above-mentioned copper-boron plating layer, copper plating layer, and gold plating layer are successively deposited.

【0008】また本発明は、前記銅−ホウ素めっき層の
厚みが0.03μm以上であることを特徴とするもので
ある。
Further, the present invention is characterized in that the thickness of the copper-boron plating layer is 0.03 μm or more.

【0009】更に本発明は、前記銅−ホウ素めっき層を
形成する銅の結晶粒の平均粒径が0.02μm以下であ
ることを特徴とするものである。
Further, the present invention is characterized in that the average grain size of the copper crystal grains forming the copper-boron plating layer is 0.02 μm or less.

【0010】本発明の配線基板によれば、少なくとも電
子部品の電極が低融点ロウ材を介して接続される配線層
の表面に、ホウ素の含有量が0.3重量%以上で銅−ホ
ウ素の結晶粒径が0.3μm以下と小さい銅−ホウ素め
っき層を被着させたことから配線層の表面に多数の凹凸
があったとしても、この凹部内に銅−ホウ素の結晶が良
好に入り込んで配線層と銅−ホウめっき層とが間に空隙
部を形成することなく強固に被着し、また銅−ホウ素め
っき層上に、該銅−ホウ素めっき層及び金めっき層のい
ずれとも密着性が良好である銅めっき層を被着させたこ
とから、配線層に銅めっき層及び金めっき層を強固に被
着させることができるとともに前記銅めっき層によって
配線層の電気抵抗を小さなものとなすことができ、更に
金めっき層によって配線層の酸化腐蝕を有効に防止しつ
つ配線層に電子部品の電極を低融点ロウ材を介して確
実、強固に電気的接続することが可能となる。
According to the wiring board of the present invention, at least the electrode of the electronic component is connected to the surface of the wiring layer through the low melting point brazing material, and the content of boron is 0.3% by weight or more. Even if there are many irregularities on the surface of the wiring layer because the copper-boron plating layer having a small crystal grain size of 0.3 μm or less is deposited, the copper-boron crystals are satisfactorily introduced into the depressions. The wiring layer and the copper-boro plating layer are firmly adhered to each other without forming a void between them, and the copper-boron plating layer has adhesion to both the copper-boron plating layer and the gold plating layer. Since the good copper plating layer is deposited, the copper plating layer and the gold plating layer can be firmly deposited on the wiring layer, and the electrical resistance of the wiring layer is made small by the copper plating layer. And the gold plating layer The electrode of the electronic component to the wiring layer while effectively prevent oxidation corrosion of the wiring layers securely via the low melting point brazing material, it is possible to firmly electrically connected.

【0011】[0011]

【発明の実施の形態】次に本発明を添付図面に基づいて
詳細に説明する。図1は、本発明の配線基板を半導体素
子収納用パッケージに適用した場合の一実施例を示す断
面図であり、1は絶縁基体、2は配線層である。この絶
縁基体1と配線層2とで半導体素子3を搭載するための
配線基板4が構成される。
DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment in which the wiring board of the present invention is applied to a package for accommodating semiconductor elements, 1 is an insulating substrate, and 2 is a wiring layer. The insulating substrate 1 and the wiring layer 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.

【0012】前記絶縁基体1は、酸化アルミニウム質焼
結体、ムライト質焼結体、窒化アルミニウム質焼結体、
炭化珪素質焼結体、ガラスセラミック焼結体等の電気絶
縁材料から成り、その上面に半導体素子3を搭載する搭
載部を有し、該搭載部表面に露出した配線層2に半導体
素子3の電極が半田等の低融点ロウ材からなる接続部材
5を介して接続される。
The insulating substrate 1 is made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body, and has a mounting portion for mounting the semiconductor element 3 on its upper surface, and the wiring layer 2 exposed on the surface of the mounting portion is provided with the semiconductor element 3 of the semiconductor element 3. The electrodes are connected via a connecting member 5 made of a low melting point brazing material such as solder.

【0013】前記絶縁基体1は、例えば、酸化アルミニ
ウム質焼結体から成る場合には、酸化アルミニウム、酸
化珪素、酸化カルシウム、酸化マグネシウム等の原料粉
末に適当な有機バインダー、溶剤を添加混合して泥漿状
のセラミックスラリーとなすとともに該セラミックスラ
リーを従来周知のドクターブレード法やカレンダーロー
ル法等のシート成形技術を採用してシート状のセラミッ
クグリーンシート(セラミック生シート)を得、しかる
後、前記セラミックグリーンシートに切断加工や打ち抜
き加工等を施して適当な形状とするとともにこれを複数
枚積層し、最後に前記積層されたセラミックグリーンシ
ートを還元雰囲気中、約1600℃の温度で焼成するこ
とによって製作されるまた前記絶縁基体1は、その上面
の搭載部から下面にかけて多数の配線層2が被着形成さ
れており、該配線層2の搭載部に露出した部位には半導
体素子3の各電極が錫−鉛半田等の低融点ロウ材から成
る接続部材5を介して電気的に接続され、また絶縁基体
1の下面に導出された部位には外部電気回路基板の配線
導体が半田等の低融点ロウ材を介して電気的に接続され
る。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, an appropriate organic binder and a solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. A sheet-shaped ceramic green sheet (ceramic green sheet) is obtained by forming the slurry into a slurry and adopting the sheet-forming technology such as the doctor blade method and the calendar roll method which are well known in the art. Produced by cutting and punching the green sheets to form an appropriate shape, stacking a plurality of these, and finally firing the stacked ceramic green sheets in a reducing atmosphere at a temperature of about 1600 ° C. In addition, the insulating base 1 is formed from the mounting portion on the upper surface to the lower surface. A large number of wiring layers 2 are formed over the wiring member 2. The electrodes of the semiconductor element 3 are connected to the connecting member 5 made of a low melting point brazing material such as tin-lead solder in the exposed portion of the wiring layer 2. The wiring conductor of the external electric circuit board is electrically connected to the portion led out to the lower surface of the insulating substrate 1 through a low melting point brazing material such as solder.

【0014】前記配線層2は、搭載される半導体素子3
の電極を外部電気回路に接続する作用をなし、例えば、
タングステンやモリブデン、モリブデン/マンガン、タ
ングステン/銅、モリブデン/銅、タングステン/モリ
ブデン/銅等のタングステン、モリブデン、マンガンの
少なくとも1種を主成分とする金属材料により形成され
ている。
The wiring layer 2 has a semiconductor element 3 mounted thereon.
Functioning to connect the electrodes of the to an external electrical circuit, for example,
It is formed of a metal material containing at least one of tungsten, molybdenum, molybdenum / manganese, tungsten / copper, molybdenum / copper, tungsten / molybdenum / copper, and the like, molybdenum, and manganese.

【0015】前記配線層2は、タングステン等の金属粉
末に適当な有機バインダーや溶剤を添加混合して得た金
属ペーストを絶縁基体1となるセラミックグリーンシー
トに予め従来周知のスクリーン印刷法により所定パター
ンに印刷塗布しておくことによって、絶縁基体1の所定
位置に被着形成される。
For the wiring layer 2, a metal paste obtained by adding and mixing an appropriate organic binder or solvent to a metal powder such as tungsten is formed in a predetermined pattern on a ceramic green sheet which becomes the insulating substrate 1 in advance by a conventionally known screen printing method. By printing and coating on, the insulating substrate 1 is adhered and formed at a predetermined position.

【0016】前記配線層2は、図2に示す如く、少なく
とも半導体素子3の電極が低融点ロウ材から成る接続部
材5を介して接続される領域に銅−ホウ素めっき層6、
銅めっき層7、金めっき層8が順次被着されている。
As shown in FIG. 2, the wiring layer 2 has a copper-boron plating layer 6, at least in a region where electrodes of the semiconductor element 3 are connected via a connecting member 5 made of a low melting point brazing material.
A copper plating layer 7 and a gold plating layer 8 are sequentially deposited.

【0017】前記銅−ホウ素めっき層6は、配線層2に
銅めっき層7および金めっき層8を密着性良く被着させ
る下地金属層として作用する。
The copper-boron plating layer 6 acts as a base metal layer for depositing the copper plating layer 7 and the gold plating layer 8 on the wiring layer 2 with good adhesion.

【0018】前記銅−ホウ素めっき層6は、例えば、配
線層2の表面にパラジウム活性を施した後、この配線層
2を、ジメチルアミンボラン等のホウ素系化合物を還元
剤として用いたホウ素系無電解銅めっき液中に所定時間
浸漬することによって配線層2の表面に所定厚みに被着
される。この場合、前記銅−ホウ素めっき層6は被着時
に共析して含有されるホウ素成分の作用により銅の結晶
粒の成長が効果的に抑制されて銅−ホウ素の結晶粒の平
均粒径は、例えば、0.3μm以下の小さなものとな
り、その結果、配線層2表面の多数の凹部があったとし
ても、この凹部内に銅−ホウ素の結晶が良好に入り込ん
で配線層2と銅−ホウ素めっき層6とは間に空隙部を形
成することなく強固に密着させることができる。
The copper-boron plating layer 6 is formed, for example, by subjecting the surface of the wiring layer 2 to palladium activation, and then using this wiring layer 2 with a boron-based compound containing a boron-based compound such as dimethylamineborane as a reducing agent. The surface of the wiring layer 2 is adhered to a predetermined thickness by immersing it in an electrolytic copper plating solution for a predetermined time. In this case, the copper-boron plating layer 6 effectively suppresses the growth of copper crystal grains by the action of the boron component contained by eutectoid deposition, and the average grain size of the copper-boron crystal grains is For example, even if there are a large number of recesses on the surface of the wiring layer 2 as a result of a small size of 0.3 μm or less, copper-boron crystals can well enter the recesses and the wiring layer 2 and the copper-boron can be It can be firmly adhered to the plating layer 6 without forming a gap between them.

【0019】なお、前記銅−ホウ素めっき層6は、銅−
ホウ素の結晶粒の平均粒径を0.3μm以下の小さなも
のとするにはホウ素の含有量を0.3重量%以上として
おく必要があり、ホウ素の含有量を0.3重量%以上と
しておくことによって銅−ホウ素の結晶粒の粒径は0.
3μm以下となり、配線層2の表面に凹凸を有するとし
ても凹部内に良好に入り込んで配線層2に強固に被着す
る。
The copper-boron plating layer 6 is made of copper-
In order to reduce the average grain size of boron crystal grains to 0.3 μm or less, the content of boron must be 0.3% by weight or more, and the content of boron should be 0.3% by weight or more. As a result, the grain size of the copper-boron crystal grains is 0.
The thickness is 3 μm or less, and even if the surface of the wiring layer 2 has irregularities, the wiring layer 2 enters into the recesses well and adheres firmly to the wiring layer 2.

【0020】また前記銅−ホウ素めっき層6は、銅−ホ
ウ素の結晶粒の平均粒径を0.02μm以下としておく
と銅−ホウ素めっき層6を表面に凹凸を有する配線層2
により一層強固に被着させることができる。従って、前
記銅−ホウ素めっき層6は、銅−ホウ素の結晶粒の平均
粒径を0.02μm以下としておくことが好ましく、よ
り好適には0.01μm以下としておくのがよい。
In the copper-boron plating layer 6, if the average grain size of copper-boron crystal grains is 0.02 μm or less, the wiring layer 2 having the copper-boron plating layer 6 having irregularities on its surface is formed.
This makes it possible to adhere more firmly. Therefore, the copper-boron plating layer 6 preferably has an average grain size of copper-boron crystal grains of 0.02 μm or less, and more preferably 0.01 μm or less.

【0021】また、前記銅−ホウ素めっき層6の平均粒
径を0.02μm以下とするには、銅−ホウ素めっき層
6中のホウ素含有率を0.5重量%程度以上とすること
によって行なわれ、電気伝導性等の特性を考慮すれば
0.5重量%〜4重量%の範囲とすることが好ましい。
The average particle size of the copper-boron plating layer 6 is set to 0.02 μm or less by setting the content of boron in the copper-boron plating layer 6 to about 0.5% by weight or more. In consideration of characteristics such as electric conductivity, it is preferable to set it in the range of 0.5% by weight to 4% by weight.

【0022】更に前記銅−ホウ素めっき層6は、その厚
みが0.03μm未満の薄いものとなると配線層2の表
面全体を銅−ホウ素めっき層6で完全に覆うのが難し
く、後述する銅めっき層7および金めっき層8を配線層
2に強固に被着させるのが困難となる傾向にある。従っ
て、前記銅−ホウ素めっき層6は、その厚さを0.03
μm以上としておくことが好ましい。
Further, when the thickness of the copper-boron plating layer 6 is less than 0.03 μm, it is difficult to completely cover the entire surface of the wiring layer 2 with the copper-boron plating layer 6, and the copper plating described later is performed. It tends to be difficult to firmly adhere the layer 7 and the gold plating layer 8 to the wiring layer 2. Therefore, the copper-boron plating layer 6 has a thickness of 0.03.
It is preferable that the thickness is at least μm.

【0023】また更に、前記銅−ホウ素めっき層6の表
面には該銅−ホウ素めっき層6と後述する金めっき層8
のいずれに対しても密着性が優れた銅めっき層7が被着
形成されている。
Furthermore, on the surface of the copper-boron plating layer 6, the copper-boron plating layer 6 and a gold plating layer 8 described later are formed.
The copper plating layer 7 having excellent adhesiveness is formed on any of the above.

【0024】前記銅めっき層7は、配線層2に金めっき
層8を強固に被着させ、かつ配線層2に対し半田等の低
融点ろう材を強固に被着させるとともに配線層2の電気
抵抗を下げる作用をなす。
The copper plating layer 7 firmly adheres the gold plating layer 8 to the wiring layer 2 and also firmly adheres the low melting point brazing material such as solder to the wiring layer 2 and the electrical conductivity of the wiring layer 2. It acts to reduce resistance.

【0025】前記銅めっき層7は、例えば、銅−ホウ素
めっき層6を被着させた配線層2を、ホルマリンを還元
剤として用いた無電解銅めっき液中に所定時間浸漬する
ことによって銅−ホウ素めっき層6の表面に所定厚みに
被着形成される。この場合、ホルマリンを還元剤として
用いた無電解銅めっき液を用いると、このめっき液が自
己触媒作用を有するため銅−ホウ素めっき層6の表面に
活性処理を施すことなく、銅めっき層7を所定厚みに、
かつ銅−ホウ素めっき層6に対し接合強度を大として被
着させることが可能となる。
The copper plating layer 7 is formed by, for example, immersing the wiring layer 2 on which the copper-boron plating layer 6 is deposited in an electroless copper plating solution using formalin as a reducing agent for a predetermined time. The surface of the boron plating layer 6 is formed to have a predetermined thickness. In this case, when an electroless copper plating solution using formalin as a reducing agent is used, the plating solution has an autocatalytic action, so that the surface of the copper-boron plating layer 6 is not subjected to activation treatment and the copper plating layer 7 is formed. To a predetermined thickness,
In addition, it becomes possible to adhere the copper-boron plating layer 6 with high bonding strength.

【0026】なお、前記銅めっき層7は、共析成分を含
有しないホルマリン等を用いて形成され高純度であるこ
とから配線層2の半田等の低融点ロウ材に対する接合性
が大きく改善されるとともに電気抵抗が極めて小さい値
となり、配線層2を伝搬する電気信号等に減衰が発生す
るのを有効に防止することが可能となる。
Since the copper plating layer 7 is formed of formalin or the like containing no eutectoid component and has a high purity, the bondability of the wiring layer 2 to the low melting point brazing material such as solder is greatly improved. At the same time, the electric resistance becomes a very small value, and it becomes possible to effectively prevent the occurrence of attenuation in the electric signal or the like propagating through the wiring layer 2.

【0027】また、前記銅めっき層7はその表面に金め
っき層8が被着形成されている。前記金めっき層8は、
配線層2、銅−ホウ素めっき層6および銅めっき層7の
酸化腐食を防止するとともに、配線層2に対する低融点
ロウ材の接合性を良好なものとする作用をなす。
The copper plating layer 7 has a gold plating layer 8 deposited on the surface thereof. The gold plating layer 8 is
It acts to prevent oxidative corrosion of the wiring layer 2, the copper-boron plating layer 6 and the copper plating layer 7 and to improve the bondability of the low melting point brazing material to the wiring layer 2.

【0028】前記金めっき層8は、例えば、金化合物で
あるシアン化金カリウムおよび錯化剤であるエチレンジ
アミン四酢酸を主成分とする無電解金めっき液中に、前
記銅めっき層7が被着されている配線層2を所定時間浸
漬させることによって銅めっき層7の表面に所定厚みに
被着される。
The gold plating layer 8 is formed by depositing the copper plating layer 7 in an electroless gold plating solution containing, as a main component, gold gold cyanide as a gold compound and ethylenediaminetetraacetic acid as a complexing agent. By immersing the formed wiring layer 2 for a predetermined time, the surface of the copper plating layer 7 is adhered to a predetermined thickness.

【0029】前記金めっき層8は、その厚みが0.05
μm未満の薄いものとなると、銅−リンめっき層6や銅
めっき層7の酸化腐蝕を有効に防止するのが困難となる
おそれがあり、また0.8μmを超えて厚くすると、半
導体素子3の電極を配線層2に半田等の低融点ロウ材か
らなる接続部材5を介して接続したとき、低融点ロウ材
5の錫と金との間で脆い金属間化合物が生成され、半導
体素子3の配線層2に対する接続の信頼性が大きく低下
してしまう危険性がある。従って、前記金めっき層8
は、その厚さを0.05μm〜0.8μmの範囲として
おくことが好ましい。
The gold plating layer 8 has a thickness of 0.05.
When the thickness is less than μm, it may be difficult to effectively prevent the oxidative corrosion of the copper-phosphorus plating layer 6 and the copper plating layer 7, and when the thickness exceeds 0.8 μm, the semiconductor element 3 of When the electrode is connected to the wiring layer 2 via the connecting member 5 made of a low melting point brazing material such as solder, a brittle intermetallic compound is generated between tin and gold of the low melting point brazing material 5 and the semiconductor element 3 There is a risk that the reliability of the connection to the wiring layer 2 will be greatly reduced. Therefore, the gold plating layer 8
Preferably has a thickness in the range of 0.05 μm to 0.8 μm.

【0030】また一方、前記半導体素子3が搭載された
絶縁基体1は、その上面に蓋体9が樹脂、ガラス、ロウ
材等からなる封止材を介して接合され、この蓋体9と絶
縁基体1とによって半導体素子3を内部に気密に封止す
るようになっている。
On the other hand, the insulating base body 1 on which the semiconductor element 3 is mounted has an upper surface to which a lid 9 is bonded via a sealing material made of resin, glass, a brazing material or the like, and insulated from the lid 9. The semiconductor element 3 is hermetically sealed inside by the base 1.

【0031】前記蓋体9は酸化アルミニウム質焼結体や
ムライト質焼結体、窒化アルミニウム質焼結体等のセラ
ミックス材料、あるいは鉄−ニッケル−コバルト合金や
鉄−ニッケル合金等の金属材料から成り、例えば、酸化
アルミニウム質焼結体から成る場合には、酸化アルミニ
ウム、酸化珪素、酸化マグネシウム、酸化カルシウム等
の原料粉末を従来周知のプレス成形法を採用することに
よって椀状に成形するとともにこれを約1500℃の温
度で焼成することによって形成される。
The lid 9 is made of a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, or a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. For example, in the case of an aluminum oxide sintered body, a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide or the like is formed into a bowl shape by adopting a conventionally known press forming method and It is formed by firing at a temperature of about 1500 ° C.

【0032】かくして上述の本発明の配線基板を適用し
た半導体素子収納用パッケージによれば、絶縁基体1上
面の搭載部表面に露出した配線層2に半導体素子3の電
極を半田等の低融点ロウ材から成る接続部材5を介して
電気的、機械的に接続し、しかる後、絶縁基体1の上面
に蓋体9を樹脂やガラス、ロウ材等から成る封止材を介
して接合させ、絶縁基体1と蓋体9とから成る容器内部
に半導体素子3を気密に収容することによって最終製品
としての半導体装置が完成する。
Thus, according to the semiconductor element housing package to which the above-described wiring board of the present invention is applied, the electrodes of the semiconductor element 3 are soldered to the wiring layer 2 exposed on the surface of the mounting portion on the upper surface of the insulating substrate 1 to form a low melting point solder. Electrically and mechanically via a connecting member 5 made of a material, and thereafter, a lid 9 is joined to the upper surface of the insulating base 1 via a sealing material made of resin, glass, brazing material, etc. A semiconductor device as a final product is completed by hermetically accommodating the semiconductor element 3 inside a container composed of the base 1 and the lid 9.

【0033】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、本発明の配線基板
を、半導体素子、容量素子、抵抗器等の電子部品を搭載
する混成集積回路用の配線基板に適用してもよい。
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, the wiring board of the present invention can be used as a semiconductor element. It may be applied to a wiring board for a hybrid integrated circuit on which electronic parts such as a capacitor and a resistor are mounted.

【0034】[0034]

【発明の効果】本発明の配線基板によれば、少なくとも
電子部品の電極が低融点ロウ材を介して接続される配線
層の表面に、ホウ素の含有量が0.3重量%以上で銅−
ホウ素の結晶粒径が0.3μm以下と小さい銅−ホウ素
めっき層を被着させたことから配線層の表面に多数の凹
凸があったとしても、この凹部内に銅−ホウ素の結晶が
良好に入り込んで配線層と銅−ホウ素めっき層とが間に
空隙部を形成することなく強固に被着し、また銅−ホウ
素めっき層上に、該銅−ホウ素めっき層及び金めっき層
のいずれとも密着性が良好である銅めっき層を被着させ
たことから、配線層に銅めっき層および金めっき層を強
固に被着させることができるとともに前記銅めっき層に
よって配線層の電気抵抗を小さなものとなすことがで
き、更に金めっき層によって配線層の酸化腐蝕を有効に
防止しつつ配線層に電子部品の電極を低融点ロウ材を介
して確実、強固に電気的接続することが可能となる。
According to the wiring board of the present invention, at least the electrode of the electronic component is connected to the surface of the wiring layer through the low melting point brazing material, and the content of boron is 0.3% by weight or more.
Even if there are many irregularities on the surface of the wiring layer because the copper-boron plating layer having a small crystal grain size of boron of 0.3 μm or less is deposited, the copper-boron crystals are well formed in the depressions. The wiring layer and the copper-boron plating layer are tightly adhered to each other without forming a gap between the wiring layer and the copper-boron plating layer, and the copper-boron plating layer is adhered to both the copper-boron plating layer and the gold plating layer. Since the copper plating layer having good properties is deposited, the copper plating layer and the gold plating layer can be firmly deposited on the wiring layer, and the electrical resistance of the wiring layer is reduced by the copper plating layer. In addition, the gold plating layer can effectively prevent oxidative corrosion of the wiring layer, and securely and firmly electrically connect the electrode of the electronic component to the wiring layer via the low melting point brazing material.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment in which a wiring board of the present invention is applied to a semiconductor element housing package.

【図2】図1に示す配線基板の要部拡大図である。FIG. 2 is an enlarged view of a main part of the wiring board shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 2・・・・配線層 3.・・・半導体素子 4・・・・配線基板 5・・・・接続部材 6・・・・銅−ホウ素めっき層 7・・・・銅めっき層 8・・・・金めっき層 9・・・・蓋体 1 ... Insulating substrate 2 ... Wiring layer 3. ... Semiconductor elements 4 ... Wiring board 5 ... Connection members 6 ... Copper-boron plating layer 7 ... Copper plating layer 8 ... Gold plating layer 9 ... Lid

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】絶縁基体に電子部品の電極が低融点ロウ材
を介して接続される配線層を被着形成してなる配線基板
であって、前記配線層のうち少なくとも電子部品の電極
が低融点ロウ材を介して接続される領域の表面に、ホウ
素の含有量が0.3重量%以上の銅−ホウ素めっき層
と、銅めっき層と、金めっき層を順次被着させたことを
特徴とする配線基板。
1. A wiring board comprising a wiring layer on which an electrode of an electronic component is connected to an insulating substrate via a low melting point brazing material, wherein at least the electrode of the electronic component is low in the wiring layer. A copper-boron plating layer having a boron content of 0.3 wt% or more, a copper plating layer, and a gold plating layer are sequentially deposited on the surface of the region connected through the melting point brazing material. And a wiring board.
【請求項2】前記銅−ホウ素めっき層の厚みが0.03
μm以上であることを特徴とする請求項1に記載の配線
基板。
2. The thickness of the copper-boron plating layer is 0.03.
The wiring board according to claim 1, wherein the wiring board has a thickness of at least μm.
【請求項3】前記銅−ホウ素めっき層を形成する銅の結
晶粒の平均粒径が0.02μm以下であることを特徴と
する請求項1に記載の配線基板。
3. The wiring board according to claim 1, wherein the average grain size of the crystal grains of copper forming the copper-boron plating layer is 0.02 μm or less.
JP2001256493A 2001-08-27 2001-08-27 Wiring board Pending JP2003069201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001256493A JP2003069201A (en) 2001-08-27 2001-08-27 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001256493A JP2003069201A (en) 2001-08-27 2001-08-27 Wiring board

Publications (1)

Publication Number Publication Date
JP2003069201A true JP2003069201A (en) 2003-03-07

Family

ID=19084301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001256493A Pending JP2003069201A (en) 2001-08-27 2001-08-27 Wiring board

Country Status (1)

Country Link
JP (1) JP2003069201A (en)

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