JP3488838B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP3488838B2
JP3488838B2 JP06366899A JP6366899A JP3488838B2 JP 3488838 B2 JP3488838 B2 JP 3488838B2 JP 06366899 A JP06366899 A JP 06366899A JP 6366899 A JP6366899 A JP 6366899A JP 3488838 B2 JP3488838 B2 JP 3488838B2
Authority
JP
Japan
Prior art keywords
external lead
nickel
semiconductor element
lead terminal
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP06366899A
Other languages
Japanese (ja)
Other versions
JP2000260925A (en
Inventor
英昭 里
義博 細井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP06366899A priority Critical patent/JP3488838B2/en
Publication of JP2000260925A publication Critical patent/JP2000260925A/en
Application granted granted Critical
Publication of JP3488838B2 publication Critical patent/JP3488838B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を収容
するための半導体素子収納用パッケージに関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは、一般に酸化アルミニウム質
焼結体等の電気絶縁材料から成り、上面の略中央部に半
導体素子を収容するための凹部及び該凹部周辺から外周
端にかけて導出されたタングステン、モリブデン、マン
ガン等の高融点金属粉末から成る配線層を有する絶縁基
体と、半導体素子を外部電気回路に電気的に接続するた
めに前記配線層に銀ロウを介して取着された鉄−ニッケ
ル−コバルト合金(54重量%Fe−29重量%Ni−17重
量%Co)から成る外部リード端子と、蓋体とから構成
されており、絶縁基体の凹部底面に半導体素子をガラ
ス、樹脂、ロウ材等の接着材を介して接着固定するとと
もに半導体素子の各電極を前記配線層にボンディングワ
イヤを介して電気的に接続し、しかる後、絶縁基体上面
に蓋体をロウ材、ガラス、樹脂等の封止材により接合さ
せ、内部に半導体素子を気密に封止することによって半
導体装置となる。
2. Description of the Related Art Conventionally, a semiconductor element accommodating package for accommodating a semiconductor element is generally made of an electrically insulating material such as an aluminum oxide sintered body, and has a recessed portion for accommodating the semiconductor element in a substantially central portion of its upper surface. And an insulating substrate having a wiring layer made of a refractory metal powder such as tungsten, molybdenum, or manganese led out from the periphery of the recess to the outer peripheral edge, and the wiring layer for electrically connecting the semiconductor element to an external electric circuit. An external lead terminal made of an iron-nickel-cobalt alloy (54% by weight Fe-29% by weight Ni-17% by weight Co) attached via a silver solder, and a lid body. The semiconductor element is adhered and fixed to the bottom surface of the recess through an adhesive such as glass, resin, or brazing material, and each electrode of the semiconductor element is electrically connected to the wiring layer through a bonding wire. Continued, and thereafter brazing material the lid on insulating base top surface, glass, are joined by a sealing material such as a resin, a semiconductor device by sealing a semiconductor element hermetically in the interior.

【0003】かかる半導体装置は外部リード端子が外部
電気回路基板の配線導体に半田等の導電性接合材を介し
て接続され、これによって半導体素子の各電極が外部電
気回路に電気的に接続されることとなる。
In such a semiconductor device, an external lead terminal is connected to a wiring conductor of an external electric circuit board through a conductive bonding material such as solder, whereby each electrode of the semiconductor element is electrically connected to the external electric circuit. It will be.

【0004】また、前記半導体素子収納用パッケージは
外部リード端子と外部電気回路との電気的接続を良好と
するために、また外部リード端子が酸化腐食するのを有
効に防止するために、通常、外部リード端子の外表面に
はニッケル及び必要に応じて金が電解めっき法等により
被着されている。
In addition, in order to improve the electrical connection between the external lead terminals and the external electric circuit, and to effectively prevent the external lead terminals from being oxidized and corroded, the semiconductor element housing package is usually The outer surface of the external lead terminal is coated with nickel and, if necessary, gold by electrolytic plating or the like.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージは外部リード端子が鉄
−ニッケル−コバルト合金(54重量%Fe−29重量%N
i−17重量%Co)から成り、そのヤング率が1400
0kgf/mm〜15000kgf/mmと高く柔
軟性に劣るものであること、外部リード端子の外表面に
被着されているニッケルのめっき層は粒径が約0.3〜
1μmと小さく、結晶の粒界が極めて多いために転位
(個々の結晶を構成するニッケル原子の外力によってす
べりを生じた領域と生じていない領域との境界線)の移
動が悪く、硬くて脆く、変形し難いこと等から半導体素
子収納用パッケージに激しい振動が加わり、外部リード
端子がロウ付け部を支点として激しく振動した場合、こ
の振動にともなう応力によってまず硬く脆いニッケルめ
っき層に亀裂が生じ、次いでこの亀裂部分に応力が集中
してニッケルめっき層に破断が生じ、最終的に前記亀裂
部の下地の外部リード端子に応力が集中して外部リード
端子が破断してしまうという欠点を有していた。
However, in this conventional package for accommodating semiconductor elements, the external lead terminals have an iron-nickel-cobalt alloy (54 wt% Fe-29 wt% N).
i-17 wt% Co) with a Young's modulus of 1400
0kgf / mm 2 ~15000kgf / mm 2 and higher it is inferior in flexibility, plating layer of nickel is deposited on the outer surface of the external lead terminals particle size of about 0.3
Since it is as small as 1 μm and the number of crystal grain boundaries is extremely large, dislocation (boundary line between a region where slippage is caused by an external force of nickel atoms constituting each crystal and a region where no slippage is caused) is poor, and it is hard and brittle. When the external lead terminal vibrates violently around the brazing part as a fulcrum due to strong vibration applied to the semiconductor element storage package because it is difficult to deform, etc., the stress accompanying this vibration causes cracks in the hard and brittle nickel plating layer first, and then There is a drawback that stress concentrates on the crack portion and breaks in the nickel plating layer, and finally stress concentrates on the external lead terminal of the base of the crack portion and breaks the external lead terminal. .

【0006】本発明は、上記欠点に鑑み案出されたもの
で、その目的は、激しい振動が加わったとしても外部リ
ード端子に破断を生じることがなく、内部に収容する半
導体素子を長期間にわたって所定の外部電気回路に確
実、強固に電気的接続することができる半導体素子収納
用パッケージを提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to prevent the external lead terminals from being broken even when severe vibration is applied, and to keep the semiconductor element housed inside for a long period of time. It is an object of the present invention to provide a package for accommodating a semiconductor element that can be securely and firmly electrically connected to a predetermined external electric circuit.

【0007】[0007]

【課題を解決するための手段】本発明は、内部に半導体
素子を収容するための空所を有する絶縁容器の外表面に
前記半導体素子の電極が接続される配線層を被着させる
とともに該配線層に外部リード端子をロウ付けしてなる
半導体素子収納用パッケージであって、前記外部リード
端子はヤング率が7000kgf/mm乃至1300
0kgf/mmで電気抵抗が50μΩ・cm以下であ
り、かつ外表面に2μm乃至5μmの粒径のニッケルか
ら成るめっき層と金から成るめっき層とが被着されてい
ることを特徴とするものである。
According to the present invention, a wiring layer to which electrodes of the semiconductor element are connected is attached to the outer surface of an insulating container having a cavity for accommodating the semiconductor element therein, and the wiring is also provided. A package for accommodating a semiconductor device, which is obtained by brazing external lead terminals to a layer, wherein the external lead terminals have a Young's modulus of 7,000 kgf / mm 2 to 1300.
An electric resistance of 0 kgf / mm 2 or less, 50 μΩ · cm or less, and an outer surface coated with a plating layer made of nickel and a plating layer made of gold having a grain size of 2 μm to 5 μm. Is.

【0008】また本発明は、前記ニッケルから成るめっ
き層の厚みが1μm乃至10μmであることを特徴とす
るものである。
Further, the present invention is characterized in that the plating layer made of nickel has a thickness of 1 μm to 10 μm.

【0009】本発明の半導体素子収納用パッケージによ
れば、外部リード端子のヤング率を7000kgf/m
2 乃至13000kgf/mm2 の低いものとして柔
軟性に富むものとし、かつ外部リード端子の外表面に被
着されるニッケルめっき層の粒径を2μm乃至5μmの
大きなものとして転位の移動が容易で変形し易いものと
したことから半導体素子収納用パッケージに激しい振動
が加わり、外部リード端子がロウ付け部を支点として激
しく振動し、振動に伴う応力が外部リード端子に作用し
たとしてもその応力は前記外部リード端子及びニッケル
めっき層が適度に変形することによって吸収され、その
結果、外部リード端子に破断を発生するのが有効に防止
されて外部リード端子を介して内部に収容する半導体素
子を所定の外部電気回路に確実、強固に電気的接続させ
ることが可能となる。
According to the semiconductor element housing package of the present invention, the Young's modulus of the external lead terminal is 7,000 kgf / m.
It has a low m 2 to 13000 kgf / mm 2 and is highly flexible, and the nickel plating layer deposited on the outer surface of the external lead terminal has a large grain size of 2 μm to 5 μm, and dislocations can be easily moved and deformed. Since it is easy to perform, severe vibration is applied to the package for housing the semiconductor element, the external lead terminal vibrates violently around the brazing part as a fulcrum, and even if the stress due to the vibration acts on the external lead terminal, the stress is The lead terminals and the nickel plating layer are appropriately deformed to be absorbed, and as a result, the external lead terminals are effectively prevented from breaking, and the semiconductor element accommodated inside through the external lead terminals can be effectively protected from external damage. It is possible to make reliable and strong electrical connection to an electric circuit.

【0010】[0010]

【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。図1及び図2は本発明の半導体素子収納
用パッケージの一実施例を示し、1は絶縁基体、2は蓋
体である。この絶縁基体1と蓋体2とで半導体素子3を
収容するための絶縁容器4が構成される。
DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a package for housing a semiconductor device of the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute an insulating container 4 for housing the semiconductor element 3.

【0011】前記絶縁基体1はその上面に半導体素子3
を収容するための空所を形成する凹部1aが設けてあ
り、該凹部1a底面には半導体素子3がガラス、樹脂、
ロウ材等の接着材を介して接着固定される。
The insulating substrate 1 has a semiconductor element 3 on its upper surface.
Is provided with a concave portion 1a forming a void for accommodating a semiconductor element 3 on the bottom surface of the concave portion 1a.
It is adhered and fixed through an adhesive material such as a brazing material.

【0012】前記絶縁基体1は、酸化アルミニウム質焼
結体や窒化アルミニウム質焼結体、ムライト質焼結体等
の電気絶縁材料から形成され、例えば酸化アルミニウム
質焼結体から成る場合であれば、酸化アルミニウム、酸
化珪素、酸化マグネシウム、酸化カルシウム等の原料粉
末に適当な有機バインダー、溶剤等を添加混合して泥漿
物を作るとともに該泥漿物をドクターブレード法やカレ
ンダーロール法等によりシート状に成形してセラミック
グリーンシート(セラミック生シート)を得、しかる
後、前記セラミックグリーンシートに適当な打ち抜き加
工および穴あけ加工を施すとともにこれを複数枚積層
し、約1600℃の高温で焼成することによって製作さ
れる。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, or a mullite sintered body. , Aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. are mixed with an appropriate organic binder, solvent, etc. to make a sludge, and the sludge is formed into a sheet by a doctor blade method or a calendar roll method. Produced by molding to obtain a ceramic green sheet (ceramic green sheet), and then subjecting the ceramic green sheet to appropriate punching and punching, laminating a plurality of these, and firing at a high temperature of about 1600 ° C. To be done.

【0013】また前記絶縁基体1には凹部1aの周辺か
ら外周端部にかけて複数個の配線層5が被着形成されて
おり、該配線層5のうち凹部1aの周辺領域には半導体
素子3の各電極がボンディングワイヤ6を介して電気的
に接続され、また絶縁基体1の外周端部に導出する領域
には外部電気回路と接続される外部リード端子7が銀ロ
ウ等のロウ材を介してロウ付け取着されている。
Further, a plurality of wiring layers 5 are formed on the insulating substrate 1 from the periphery of the recess 1a to the outer peripheral edge portion, and the semiconductor element 3 is formed in the peripheral region of the recess 1a of the wiring layer 5. Each electrode is electrically connected via a bonding wire 6, and an external lead terminal 7 connected to an external electric circuit is provided in a region extending to the outer peripheral end of the insulating substrate 1 via a brazing material such as silver solder. It is attached by brazing.

【0014】前記配線層5は半導体素子3の各電極を外
部電気回路に接続する際の導電路として作用し、タング
ステンやモリブデン、マンガン等の金属材料によって形
成されている。
The wiring layer 5 acts as a conductive path when connecting the electrodes of the semiconductor element 3 to an external electric circuit, and is made of a metal material such as tungsten, molybdenum, or manganese.

【0015】前記配線層5は、例えば、タングステン、
モリブデン、マンガン等の高融点金属粉末に適当な有機
溶剤、溶媒を添加混合して得た金属ペーストを絶縁基体
1となるセラミックグリーンシートの表面に従来周知の
スクリーン印刷法等により予め所定パターンに印刷塗布
しておき、セラミックグリーンシートを焼成して絶縁基
体1とする際に同時に絶縁基体1の凹部1a周辺から外
周端部にかけて所定パターンに被着形成される。
The wiring layer 5 is made of, for example, tungsten,
A metal paste obtained by adding and mixing an appropriate organic solvent or solvent to a refractory metal powder such as molybdenum or manganese is printed in advance in a predetermined pattern on the surface of the ceramic green sheet to be the insulating substrate 1 by a conventionally known screen printing method or the like. When the ceramic green sheet is applied and fired to form the insulating substrate 1, the insulating substrate 1 is simultaneously formed in a predetermined pattern from the periphery of the concave portion 1a to the outer peripheral end.

【0016】なお、前記配線層5はその露出表面にニッ
ケル、金等の耐蝕性に優れ、かつロウ材等と濡れ性が良
い金属をめっき法により1μm〜20μmの厚みに被着
させておくと、配線層5の酸化腐蝕を有効に防止するこ
とができるとともに配線層5へのボンディングワイヤ6
の接続及び外部リード端子7のロウ付けを強固となすこ
とができる。従って、前記配線層5はその露出表面にニ
ッケル、金等の耐蝕性に優れ、かつロウ材等と濡れ性が
良い金属をめっき法により1μm〜20μmの厚みに被
着させておくことが好ましい。
It is to be noted that the wiring layer 5 is formed by depositing a metal such as nickel or gold having a high corrosion resistance and a good wettability with a brazing material to a thickness of 1 to 20 μm by a plating method. The oxidative corrosion of the wiring layer 5 can be effectively prevented and the bonding wire 6 to the wiring layer 5 can be effectively prevented.
Connection and brazing of the external lead terminal 7 can be made firm. Therefore, it is preferable that the exposed surface of the wiring layer 5 is coated with a metal such as nickel or gold having a high corrosion resistance and a good wettability with the brazing material to a thickness of 1 μm to 20 μm by a plating method.

【0017】また前記配線層5には外部リード端子7が
ロウ付けされており、該外部リード端子7は外部電気回
路に半田等を介して接続され、これによって半導体素子
3はその各電極がボンディングワイヤ6及び配線層5を
介して外部電気回路に接続されることとなる。
External lead terminals 7 are brazed to the wiring layer 5, and the external lead terminals 7 are connected to an external electric circuit via solder or the like, whereby the electrodes of the semiconductor element 3 are bonded. It will be connected to an external electric circuit via the wire 6 and the wiring layer 5.

【0018】前記外部リード端子7はヤング率が700
0kgf/mm2 乃至13000kgf/mm2 の金属
材料、具体的には鉄−ニッケル−コバルト合金を800
℃以上、好ましくは約900℃の温度で熱処理し軟化さ
せたものが好適に使用され、配線層5上に、銀ロウ等の
ロウ材を間に挟んで外部リード端子7を載置し、しかる
後、前記ロウ材に約800℃〜850℃の熱を印加し、
ロウ材を溶融させることによって配線層5に取着され
る。
The external lead terminal 7 has a Young's modulus of 700.
0 kgf / mm 2 to 13000kgf / mm 2 of a metallic material, in particular iron - nickel - 800 cobalt alloy
One that is heat-treated and softened at a temperature of ℃ or more, preferably about 900 ° C. is suitably used, and the external lead terminal 7 is placed on the wiring layer 5 with a brazing material such as silver brazing interposed therebetween. Then, heat of about 800 ° C. to 850 ° C. is applied to the brazing material,
It is attached to the wiring layer 5 by melting the brazing material.

【0019】前記外部リード端子7はそのヤング率が7
000kgf/mm2 乃至13000kgf/mm2
柔軟性に富むことから、半導体素子収納用パッケージに
激しい振動が加わり、外部リード端子7がロウ付け部を
支点として激しく振動し、振動に伴う応力が外部リード
端子7に作用したとしてもその応力は前記外部リード端
7が適度に変形することによって吸収され、その結果、
外部リード端子7に破断を発生するのが有効に防止され
て外部リード端子7を介して内部に収容する半導体素子
3を所定の外部電気回路に確実、強固に電気的接続させ
ることが可能となる。
The Young's modulus of the external lead terminal 7 is 7
Since it is highly flexible at 000 kgf / mm 2 to 13000 kgf / mm 2 , violent vibration is applied to the package for housing the semiconductor element, and the external lead terminals 7 vibrate violently with the brazing part as a fulcrum, and the stress associated with the vibration causes the external lead Even if it acts on the terminal 7, the stress is absorbed by the appropriate deformation of the outer lead end 7, and as a result,
The breakage of the external lead terminals 7 is effectively prevented, and the semiconductor element 3 housed inside can be securely and firmly electrically connected to a predetermined external electric circuit via the external lead terminals 7. .

【0020】なお、前記外部リード端子7はそのヤング
率が7000kgf/mm2 未満になると外部リード端
子7の剛性が不足して小さな外力印加によっても容易に
変形し、外部リード端子7の外部電気回路への電気的接
続の作業性が悪いものになるとともに外部リード端子7
を外部電気回路に半田等を介して接続した後、外部リー
ド端子7に外力が印加されると外部リード端子7が揺動
し、該揺動に伴って外部リード端子7を外部電気回路に
接続している半田等に外れが発生して外部リード端子7
の外部電気回路への電気的接続の信頼性が大きく低下し
てしまい、また13000kgf/mm2 を超えると外
部リード端子7の柔軟性が劣化し、外部振動の印加に伴
う応力によって破断が発生してしまう。従って、前記外
部リード端子7は、そのヤング率が7000kgf/m
2 乃至13000kgf/mm2 の範囲に特定され
る。
When the Young's modulus of the external lead terminal 7 is less than 7000 kgf / mm 2 , the rigidity of the external lead terminal 7 is insufficient and the external lead terminal 7 is easily deformed by applying a small external force. Workability of electrical connection to the external lead terminal 7
After connecting to the external electric circuit via solder or the like, the external lead terminal 7 swings when an external force is applied to the external lead terminal 7, and the external lead terminal 7 is connected to the external electric circuit in accordance with the swing. The external lead terminals 7
The reliability of the electrical connection to the external electric circuit will be greatly reduced, and if it exceeds 13000 kgf / mm 2 , the flexibility of the external lead terminal 7 will deteriorate and the stress due to the application of external vibration will cause breakage. Will end up. Therefore, the external lead terminal 7 has a Young's modulus of 7,000 kgf / m.
It is specified in the range of m 2 to 13000 kgf / mm 2 .

【0021】また前記外部リード端子7はその露出外表
面に粒径が2μm乃至5μmのニッケルから成るめっき
層9が被着されており、該ニッケルから成るめっき層9
によって外部リード端子7と外部電気回路との電気的接
続が良好となるとともに外部リード端子7の酸化腐蝕が
有効に防止されている。
A plating layer 9 made of nickel having a grain size of 2 μm to 5 μm is adhered to the exposed outer surface of the external lead terminal 7, and the plating layer 9 made of nickel.
As a result, the electrical connection between the external lead terminal 7 and the external electric circuit is improved, and the oxidative corrosion of the external lead terminal 7 is effectively prevented.

【0022】前記粒径が2μm乃至5μmのニッケルか
ら成るめっき層9は、電解めっき法や無電解めっき法を
採用することによって外部リード端子7の露出表面に形
成され、具体的には、電解めっき法により形成する場合
には、例えば、従来周知のワット浴、即ち、硫酸ニッケ
ル、塩化ニッケル、ホウ酸から成るめっき浴においてニ
ッケル濃度を40グラム/リットル程度まで下げたニッ
ケル濃度の低いニッケルめっき浴中に外部リード端子7
を浸漬し、次に外部リード端子7に1乃至1.5A/d
2 程度の電流密度のめっき用電力を印加することによ
って、或いは、めっき浴中に錯化剤等を添加しておき、
ニッケルの析出を制御(ニッケルのめっき速度を抑制)
することによって外部リード端子7の表面に形成され
る。
The plating layer 9 made of nickel having a grain size of 2 μm to 5 μm is formed on the exposed surface of the external lead terminal 7 by adopting an electrolytic plating method or an electroless plating method. In the case of forming by the method, for example, in a conventionally well-known Watt bath, that is, a nickel plating bath having a low nickel concentration in which the nickel concentration is lowered to about 40 g / liter in a plating bath composed of nickel sulfate, nickel chloride and boric acid. External lead terminal 7
And then 1 to 1.5 A / d on the external lead terminal 7.
by applying a plating power having a current density of about m 2 or by adding a complexing agent or the like in the plating bath,
Controls nickel deposition (suppresses nickel plating rate)
By doing so, it is formed on the surface of the external lead terminal 7.

【0023】前記ニッケルから成るめっき層9は、ニッ
ケルの粒径が2μm乃至5μmであり、粒径が大きいこ
とから転位の移動が容易で変形し易いものとなってお
り、これによって半導体素子収納用パッケージに激しい
振動が加わり、外部リード端子がロウ付け部を支点とし
て激しく振動し、振動に伴う応力がニッケルから成るめ
っき層9に作用したとしてもその応力はニッケルから成
るめっき層9を適度に変形させることによって吸収さ
れ、その結果、ニッケルから成るめっき層9に亀裂や破
断を発生することはない。
The plating layer 9 made of nickel has a nickel grain size of 2 μm to 5 μm, and since the grain size is large, dislocations are easily moved and easily deformed. Even if a strong vibration is applied to the package and the external lead terminals vibrate violently around the brazing portion as a fulcrum, and the stress due to the vibration acts on the plating layer 9 made of nickel, the stress appropriately deforms the plating layer 9 made of nickel. As a result, it is absorbed, and as a result, the plating layer 9 made of nickel does not crack or break.

【0024】なお、前記ニッケルから成るめっき層9は
その粒径が2μm未満となると結晶の粒界が多く、転位
(個々の結晶を構成するニッケル原子の外力によってす
べりを生じた領域と生じていない領域との境界線)の移
動が悪くなって、硬くて脆く、変形し難いものとなり、
外部より激しい振動が加わった際に亀裂が生じるととも
に破断が発生してしまい、また5μmを超えるとニッケ
ルから成るめっき層9に多量にピンホール(開口)が形
成されて外部リード端子7の露出外表面を完全に被覆す
ることができず、外部リード端子7に酸化腐蝕が発生し
たり、外部電気回路との電気的接続の信頼性が低下した
りしてしまう。従って、前記ニッケルから成るめっき層
9はその粒径が2μm乃至5μmの範囲に特定される。
When the grain size of the plating layer 9 made of nickel is less than 2 μm, there are many grain boundaries of crystals, and dislocations (regions where slippage occurs due to the external force of nickel atoms constituting each crystal do not occur). The movement of the boundary line between the area) becomes poor, making it hard and brittle, and difficult to deform,
When violent vibration is applied from the outside, cracks and fractures occur, and when the thickness exceeds 5 μm, a large number of pinholes (openings) are formed in the plating layer 9 made of nickel and the external lead terminals 7 are exposed. The surface cannot be completely covered, so that the external lead terminals 7 may be oxidized and corroded, or the reliability of electrical connection with an external electric circuit may be deteriorated. Therefore, the grain size of the plating layer 9 made of nickel is specified in the range of 2 μm to 5 μm.

【0025】更に、前記ニッケルから成るめっき層9
は、その厚みが1μm未満となると外部リード端子7に
対する半田等の濡れ性が低下して外部リード端子7を外
部電気回路に強固に電気的接続することが困難となる傾
向にあり、また10μmを超えるとニッケルから成るめ
っき層9中にめっきの際に発生する応力が内在し、該内
在応力によって外部リード端子7に対する密着強度が低
いものとなってしまう傾向がある。従って、前記ニッケ
ルから成るめっき層9はその厚みを1μm乃至10μm
の範囲としておくことが好ましい。
Further, the plating layer 9 made of the above nickel
If the thickness is less than 1 μm, the wettability of the solder or the like to the external lead terminals 7 tends to deteriorate, and it becomes difficult to firmly electrically connect the external lead terminals 7 to the external electric circuit. When it exceeds, the stress generated during plating is inherent in the plating layer 9 made of nickel, and the internal stress tends to reduce the adhesion strength to the external lead terminal 7. Therefore, the plating layer 9 made of nickel has a thickness of 1 μm to 10 μm.
It is preferable to set it as the range of.

【0026】また一方、前記外部リード端子7が取着さ
れている絶縁基体1はその上面に蓋体2が樹脂、ガラ
ス、ロウ材等からなる封止材を介して接合され、蓋体2
によって絶縁基体1の凹部1aを塞ぎ、凹部1a内に配
されている半導体素子3を気密に封止するようになって
いる。
On the other hand, the insulating base 1 to which the external lead terminals 7 are attached has the lid 2 bonded to the upper surface thereof via a sealing material made of resin, glass, brazing material, etc.
With this, the concave portion 1a of the insulating base 1 is closed, and the semiconductor element 3 arranged in the concave portion 1a is hermetically sealed.

【0027】前記蓋体2は酸化アルミニウム質焼結体や
ムライト質焼結体、窒化アルミニウム質焼結体等のセラ
ミックス材料、あるいは鉄−ニッケル−コバルト合金や
鉄−ニッケル合金等の金属材料から成り、例えば、酸化
アルミニウム質焼結体から成る場合には、酸化アルミニ
ウム、酸化珪素、酸化マグネシウム、酸化カルシウム等
の原料粉末を従来周知のプレス成型法を採用することに
よって板状に成形するとともにこれを約1500℃の温
度で焼成することによって形成される。
The lid 2 is made of a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, or a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. For example, in the case of an aluminum oxide sintered body, a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide or the like is formed into a plate shape by adopting a conventionally known press forming method and It is formed by firing at a temperature of about 1500 ° C.

【0028】かくして上述の半導体素子収納用パッケー
ジによれば、絶縁基体1の凹部1a底面に半導体素子3
をガラス、樹脂、ロウ材等の接着材を介し接着固定する
とともに該半導体素子3の各電極をボンディングワイヤ
6により外部リード端子7が取着されている配線層5に
電気的に接続させ、しかる後、絶縁基体1の上面に蓋体
2を樹脂やガラス、ロウ材等から成る封止材を介して接
合させ、絶縁基体1と蓋体2とから成る絶縁容器4内部
に半導体素子3を気密に収容することによって最終製品
としての半導体装置となる。
Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 3 is formed on the bottom surface of the recess 1a of the insulating substrate 1.
Is bonded and fixed through an adhesive such as glass, resin, or brazing material, and each electrode of the semiconductor element 3 is electrically connected to the wiring layer 5 to which the external lead terminal 7 is attached by the bonding wire 6. After that, the lid body 2 is bonded to the upper surface of the insulating base body 1 through a sealing material made of resin, glass, brazing material or the like, and the semiconductor element 3 is hermetically sealed in the insulating container 4 made up of the insulating base body 1 and the lid body 2. The final product is a semiconductor device by being housed in.

【0029】 なお、前記ニッケルめっき層9の上面
に、金めっき層10を被着させている。これにより、金
めっき層10によって外部リード端子7の酸化腐食がよ
り一層、有効に防止されるとともに半田等の濡れ性がよ
り一層良好なものとなり、外部リード端子7を外部電気
回路に半田等を介してより強固に電気的接続することが
可能となる。
A gold plating layer 10 is deposited on the upper surface of the nickel plating layer 9. As a result, the gold plating layer 10 further effectively prevents oxidative corrosion of the external lead terminals 7 and further improves the wettability of solder or the like, so that the external lead terminals 7 can be soldered to an external electric circuit. It is possible to make a stronger electrical connection via the.

【0030】前記金めっき層10は、電解めっき法、無
電解法等のめっき法により形成され、例えば、電解めっ
き法による場合であれば、従来周知のシアン化金カリウ
ム系のめっき浴を用い、定法に従い液温50〜80℃、
pH4〜7の作業条件で所定の時間行うことによりニッ
ケルから成るめっき層9の表面に所定厚みに被着され
る。この場合、金は極めて延性に優れた柔軟なものであ
ることから、この金めっき層10に振動にともなう破断
等が生じることはない。
The gold plating layer 10 is formed by a plating method such as an electrolytic plating method and an electroless method. For example, in the case of the electrolytic plating method, a conventionally known gold potassium cyanide-based plating bath is used. According to the standard method, the liquid temperature is 50 to 80 ° C,
The surface of the plating layer 9 made of nickel is adhered to a predetermined thickness by carrying out the work under a working condition of pH 4 to 7 for a predetermined time. In this case, since gold is a flexible material having extremely excellent ductility, the gold plating layer 10 will not be broken or the like due to vibration.

【0031】 また上述の実施例では、ヤング率が70
00kgf/mm乃至13000kgf/mmの外
部リード端子7として鉄−ニッケル−コバルト合金を8
00℃以上、好ましくは約900℃の温度で熱処理し軟
化させたものを使用する旨、説明したが、ヤング率が7
000kgf/mm乃至13000kgf/mm
金属材料であり、併せて電気抵抗が50μΩ・cm以下
の金属材料であるものがなお一層よいことから、電気抵
抗を50μΩ・cm以下とする。
Further, in the above embodiment, the Young's modulus is 70.
Iron-nickel-cobalt alloy 8 is used as the external lead terminal 7 of 00 kgf / mm 2 to 13000 kgf / mm 2.
Although it has been explained that the one heat-treated and softened at a temperature of 00 ° C. or higher, preferably about 900 ° C. is used, the Young's modulus is 7
It is even better to use a metal material of 000 kgf / mm 2 to 13000 kgf / mm 2 together with an electric resistance of 50 μΩ · cm or less, so that the electric resistance is 50 μΩ · cm or less.

【0032】[0032]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、外部リード端子のヤング率を7000kgf/
mm2 乃至13000kgf/mm2 の低いものとして
柔軟性の富むものとし、かつ外部リード端子の外表面に
被着されるニッケルめっき層の粒径を2μm乃至5μm
の大きなものとして転位の移動が容易で変形し易いもの
としたことから半導体素子収納用パッケージに激しい振
動が加わり、外部リード端子がロウ付け部を支点として
激しく振動し、振動に伴う応力が外部リード端子に作用
したとしてもその応力は前記外部リード端子及びニッケ
ルめっき層が適度に変形することによって吸収され、そ
の結果、外部リード端子に破断を発生するのが有効に防
止されて外部リード端子を介して内部に収容する半導体
素子を所定の外部電気回路に確実、強固に電気的接続さ
せることが可能となる。
According to the semiconductor element housing package of the present invention, the Young's modulus of the external lead terminals is 7,000 kgf /
mm 2 to 13000 kgf / mm 2 having a low flexibility, and the nickel plating layer deposited on the outer surface of the external lead terminal has a particle size of 2 μm to 5 μm.
Since the dislocations are easy to move and deform easily because of the large size of the package, a strong vibration is applied to the package for housing the semiconductor element, and the external lead terminals vibrate violently with the brazing part as the fulcrum, and the stress associated with the vibration causes the external lead Even if the stress is applied to the terminal, the stress is absorbed by the appropriate deformation of the external lead terminal and the nickel plating layer, and as a result, the external lead terminal is effectively prevented from breaking, and the stress is absorbed through the external lead terminal. Thus, it becomes possible to securely and firmly electrically connect the semiconductor element housed inside to a predetermined external electric circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【図2】図1に示す半導体素子収納用パッケージの要部
拡大断面図である。
FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor element storage package shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 1a・・・・凹部 2・・・・・蓋体 3・・・・・半導体素子 4・・・・・絶縁容器 5・・・・・配線層 7・・・・・外部リード端子 9・・・・・ニッケルから成るめっき層 1 ... Insulating substrate 1a ... Recess 2 ... Lid 3 ... Semiconductor element 4 ... Insulation container 5 ... Wiring layer 7: External lead terminal 9: Nickel plating layer

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 内部に半導体素子を収容するための空所
を有する絶縁容器の外表面に前記半導体素子の電極が接
続される配線層を被着させるとともに該配線層に外部リ
ード端子をロウ付けしてなる半導体素子収納用パッケー
ジであって、前記外部リード端子はヤング率が7000
kgf/mm乃至13000kgf/mm電気抵
抗が50μΩ・cm以下であり、かつ外表面に2μm乃
至5μmの粒径のニッケルから成るめっき層と金から成
るめっき層とが被着されていることを特徴とする半導体
素子収納用パッケージ。
1. A wiring layer to which electrodes of the semiconductor element are connected is attached to an outer surface of an insulating container having a space for accommodating the semiconductor element therein, and an external lead terminal is brazed to the wiring layer. The external lead terminal has a Young's modulus of 7,000.
in electrical resistance kgf / mm 2 or 13000kgf / mm 2
The resistance is 50 μΩ · cm or less , and the outer surface is composed of a plated layer of nickel having a grain size of 2 μm to 5 μm and gold.
A package for accommodating a semiconductor element, characterized in that it is coated with a plating layer .
【請求項2】 前記ニッケルから成るめっき層の厚みが
1μm乃至10μmであることを特徴とする請求項1に
記載の半導体素子収納用パッケージ。
2. The package for housing a semiconductor device according to claim 1, wherein the plating layer made of nickel has a thickness of 1 μm to 10 μm.
JP06366899A 1999-03-10 1999-03-10 Package for storing semiconductor elements Expired - Fee Related JP3488838B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06366899A JP3488838B2 (en) 1999-03-10 1999-03-10 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06366899A JP3488838B2 (en) 1999-03-10 1999-03-10 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JP2000260925A JP2000260925A (en) 2000-09-22
JP3488838B2 true JP3488838B2 (en) 2004-01-19

Family

ID=13235970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06366899A Expired - Fee Related JP3488838B2 (en) 1999-03-10 1999-03-10 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3488838B2 (en)

Also Published As

Publication number Publication date
JP2000260925A (en) 2000-09-22

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