JPH07202356A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPH07202356A
JPH07202356A JP5335233A JP33523393A JPH07202356A JP H07202356 A JPH07202356 A JP H07202356A JP 5335233 A JP5335233 A JP 5335233A JP 33523393 A JP33523393 A JP 33523393A JP H07202356 A JPH07202356 A JP H07202356A
Authority
JP
Japan
Prior art keywords
conductor
circuit
wiring conductor
circuit board
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5335233A
Other languages
Japanese (ja)
Other versions
JP3495773B2 (en
Inventor
Keiji Yamamoto
圭司 山本
Yoshihiro Hosoi
義博 細井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Toyota Motor Corp
Original Assignee
Kyocera Corp
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp, Toyota Motor Corp filed Critical Kyocera Corp
Priority to JP33523393A priority Critical patent/JP3495773B2/en
Publication of JPH07202356A publication Critical patent/JPH07202356A/en
Application granted granted Critical
Publication of JP3495773B2 publication Critical patent/JP3495773B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01025Manganese [Mn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Abstract

PURPOSE:To provide a circuit board which can join a bonding wire and a circuit conductor firmly and quickly when directly mounting an active element such as a semiconductor element on the circuit board without any package. CONSTITUTION:A wiring conductor 2 consisting of high melt-point metal made of tungsten, molybdenum, manganese, etc., is formed inside and on the surface of an insulation board 1 such as ceramic and further a circuit conductor 4 consisting of copper is deposited so that the surface of the exposed wiring conductor 2 is covered. A bonding pad 2a is formed at a part which is exposed on the outer surface of the insulation board 1, a covering layer 5 which mainly consists of nickel with a Vickers hardness of 600 or larger is deposited on the surface of the bonding pad 2a, and a bonding wire which is connected from the area on the covering layer 5 to each electrode of the semiconductor element A.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、混成集積回路装置など
に使用される回路基板に関し、より詳細には内部および
表面に高融点金属から成る配線導体を有し、外表面に銅
から成る回路導体が被着された回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board used in a hybrid integrated circuit device or the like, and more particularly to a circuit board having wiring conductors made of a refractory metal on the inside and the surface and made of copper on the outer surface. It relates to a circuit board to which a conductor is applied.

【0002】[0002]

【従来の技術】従来、半導体素子等の能動部品や抵抗
器、コンデンサ等の受動部品を多数搭載し、所定の電子
回路を構成するように成した混成集積回路装置は、通
常、内部にタングステンやモリブデン等の高融点金属か
ら成る配線導体を埋設した絶縁基体の外表面に、銅から
成る回路導体をその一部が前記配線導体を接続するよう
にして被着させた構造の回路基板を準備し、次に前記回
路基板の表面に半導体素子や抵抗器、コンデンサ等の電
子部品を搭載するとともに各々の電極端子を回路導体に
半田等の導電性接着剤を介し接合させることによって形
成されている。
2. Description of the Related Art Conventionally, a hybrid integrated circuit device in which a large number of active components such as semiconductor elements and passive components such as resistors and capacitors are mounted to form a predetermined electronic circuit is usually provided with tungsten or Prepare a circuit board having a structure in which a circuit conductor made of copper is attached to the outer surface of an insulating substrate in which a wiring conductor made of a high melting point metal such as molybdenum is embedded so that a part of the circuit conductor is connected to the wiring conductor. Next, electronic components such as semiconductor elements, resistors, and capacitors are mounted on the surface of the circuit board, and each electrode terminal is joined to the circuit conductor through a conductive adhesive such as solder.

【0003】なお、かかる従来の混成集積回路装置等に
使用される回路基板は一般にセラミックスの積層技術お
よびスクリーン印刷等の厚膜技術を採用することによっ
て製作されており、具体的には以下の方法によって製作
される。
The circuit board used in such a conventional hybrid integrated circuit device or the like is generally manufactured by adopting a ceramics lamination technique and a thick film technique such as screen printing. Specifically, the following method is used. Produced by.

【0004】すなわち、まず、アルミナ、シリカ、カル
シア、マグネシア等のセラミック原料粉末に有機結合
材、溶媒を添加混合して複数枚のセラミックグリーンシ
ートを得るとともに該各セラミックグリーンシートの上
下面にタングステン、モリブデン、マンガン等の高融点
金属粉末から成る導電ペーストを従来周知のスクリーン
印刷法等の厚膜手法を採用することによって所定パター
ンに印刷塗布する。
That is, first, an organic binder and a solvent are added to and mixed with a ceramic raw material powder such as alumina, silica, calcia, and magnesia to obtain a plurality of ceramic green sheets, and tungsten is provided on the upper and lower surfaces of each ceramic green sheet. A conductive paste made of a high melting point metal powder such as molybdenum or manganese is printed and applied in a predetermined pattern by adopting a conventionally known thick film technique such as screen printing.

【0005】次に、前記各セラミックグリーンシートを
積層し、積層体を得るとともにこれを約1500℃の温
度で焼成し、内部および表面にタングステン、モリブデ
ン等の高融点金属から成る配線導体を有する絶縁基体を
得る。
Next, the above-mentioned ceramic green sheets are laminated to obtain a laminated body and the laminated body is fired at a temperature of about 1500 ° C. Insulation having a wiring conductor made of a refractory metal such as tungsten or molybdenum inside and on the surface thereof. A substrate is obtained.

【0006】そして次に前記配線導体の露出面に銅から
成る回路導体との密着を強固にするためのニッケルメッ
キを施し、最後に、前記絶縁基体の外表面に銅粉末およ
びガラス粉末を含む銅ペーストを従来周知の厚膜手法を
採用してその一部が前記配線導体と接続するようにして
所定パターンに印刷塗布するとともにこれを微量な酸素
を有する窒素雰囲気中、約900℃の温度で焼成し、銅
粉末を絶縁基体および配線導体上に被着させることによ
って製品としての回路基板となる。
Then, the exposed surface of the wiring conductor is plated with nickel for strengthening the close contact with the circuit conductor made of copper, and finally, the outer surface of the insulating substrate is made of copper containing copper powder and glass powder. The paste is applied by printing in a predetermined pattern so that a part of the paste is connected to the wiring conductor by using a conventionally known thick film technique, and the paste is baked at a temperature of about 900 ° C. in a nitrogen atmosphere containing a slight amount of oxygen. Then, by depositing the copper powder on the insulating substrate and the wiring conductor, a circuit board as a product is obtained.

【0007】また、この従来の混成集積回路装置におい
て、回路基板の表面に搭載される半導体素子は一般に半
導体素子の各電極と電気的に接続された外部接続端子を
有する半導体素子収納用パッケージに収容されており、
該半導体素子収納用パッケージの外部接続端子を回路基
板の回路配線に半田等の導電性接着剤を介して接合する
ことにより半導体素子の各電極が回路基板の回路導体に
電気的に接続されるようになっている。
In this conventional hybrid integrated circuit device, the semiconductor element mounted on the surface of the circuit board is generally housed in a semiconductor element housing package having external connection terminals electrically connected to each electrode of the semiconductor element. Has been done,
The electrodes of the semiconductor element are electrically connected to the circuit conductor of the circuit board by joining the external connection terminals of the package for housing the semiconductor element to the circuit wiring of the circuit board via a conductive adhesive such as solder. It has become.

【0008】一方、近時の混成集積回路装置の小型化、
高密度化の要求に伴い、回路基板上に搭載される半導体
素子を半導体素子収納用パッケージ内に収容することな
く直接回路基板上に搭載し、半導体素子の電極をボンデ
ィングワイヤを介して回路導体に接続する、いわゆるベ
アチップ実装が検討されている。これによって半導体素
子収納用パッケージにより占有されていた回路基板上の
余分な空間を削減して、混成集積回路装置の小型化を図
ることが可能である。なお、ボンディングワイヤによる
接続は、通常、超音波ボンダーにより行われる。
On the other hand, the recent miniaturization of hybrid integrated circuit devices,
With the demand for higher density, the semiconductor elements mounted on the circuit board are directly mounted on the circuit board without being housed in the semiconductor element housing package, and the electrodes of the semiconductor elements are connected to the circuit conductors via the bonding wires. A so-called bare chip mounting for connection is being considered. As a result, it is possible to reduce the extra space on the circuit board occupied by the package for housing the semiconductor element and to downsize the hybrid integrated circuit device. The connection with the bonding wire is usually performed with an ultrasonic bonder.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、半導体
素子と回路導体とをボンディングワイヤを介して接続す
る場合、該回路導体を構成する銅は酸化され易い金属で
あるため、銅から成る回路導体の表面に酸化膜が形成さ
れ易く、該酸化膜の存在によって回路導体とボンディン
グワイヤとの接合が阻害されて強固な接合が得られず、
そのためボンディングワイヤと回路導体との接続が外れ
易くなり、半導体素子の電極と回路導体との電気的接続
が確実に行なわれないという課題がある。
However, when connecting a semiconductor element and a circuit conductor via a bonding wire, the copper forming the circuit conductor is a metal that is easily oxidized, and therefore the surface of the circuit conductor made of copper is An oxide film is likely to be formed on the substrate, and the presence of the oxide film hinders the bonding between the circuit conductor and the bonding wire, so that a strong bond cannot be obtained.
Therefore, there is a problem that the bonding wire and the circuit conductor are easily disconnected from each other, and the electrical connection between the electrode of the semiconductor element and the circuit conductor cannot be surely made.

【0010】そこで、回路導体との密着を強固にするた
めのニッケルメッキが施された配線導体の一部を回路導
体によって被覆せずに露出させて、該配線導体の露出部
のニッケルメッキ上にボンディングワイヤを接続するこ
とが考えられる。
Therefore, a part of the wiring conductor plated with nickel for strengthening the close contact with the circuit conductor is exposed without being covered with the circuit conductor, and is exposed on the nickel plating of the exposed portion of the wiring conductor. It is conceivable to connect bonding wires.

【0011】この場合、前記回路導体との密着を強固と
為すためのニッケルメッキ層は、回路導体を被着させる
際に約900℃の温度の高温で加熱処理される。その結
果、ニッケルメッキ層が高温で焼鈍しされ、ビッカース
硬度で200〜400程度に柔らくなる。このため、超
音波ボンダーを使用してボンディングワイヤをニッケル
メッキ層に対して接合させる際、ニッケルメッキ層が極
めて容易に変形してしまうため、摺動部に短時間で大き
な摩擦熱を発生させることができず、ボンディングワイ
ヤを強固に接続させることができないという課題があ
る。
In this case, the nickel plating layer for firmly adhering to the circuit conductor is heat-treated at a high temperature of about 900 ° C. when the circuit conductor is adhered. As a result, the nickel plating layer is annealed at a high temperature and becomes soft to a Vickers hardness of about 200 to 400. For this reason, when the bonding wire is bonded to the nickel plating layer using the ultrasonic bonder, the nickel plating layer is extremely easily deformed, so that large friction heat is generated in a short time in the sliding portion. Therefore, there is a problem that the bonding wire cannot be firmly connected.

【0012】本発明の目的は、前述の課題を解決するた
め、半導体素子等の能動素子をパッケージ無しで回路基
板上に直接搭載する場合、ボンディングワイヤと回路導
体との接合を強固にかつ短時間で実現することができる
回路基板を提供することである。
In order to solve the above problems, an object of the present invention is to mount an active element such as a semiconductor element directly on a circuit board without a package, to firmly and quickly bond a bonding wire and a circuit conductor. It is to provide a circuit board that can be realized by.

【0013】[0013]

【課題を解決するための手段】本発明は、内部に高融点
金属を含む配線導体を有する絶縁基体において、該配線
導体の一部を絶縁基体上面に露出させると共に、該露出
した配線導体表面にボンディングワイヤの熱圧着時に熱
による変形が生じない程度の硬度を有するニッケルを主
成分とする被覆層を、前記露出部に被着させたことを特
徴とする回路基板である。
According to the present invention, in an insulating substrate having a wiring conductor containing a refractory metal therein, a part of the wiring conductor is exposed on the upper surface of the insulating substrate and the exposed wiring conductor surface is formed. The circuit board is characterized in that a coating layer containing nickel as a main component and having a hardness that does not cause deformation due to heat during thermocompression bonding of the bonding wire is attached to the exposed portion.

【0014】また本発明は、前記配線導体の絶縁基体上
面に露出した部位が回路導体と接触していないことを特
徴とする。
The present invention is also characterized in that the exposed portion of the wiring conductor on the upper surface of the insulating substrate is not in contact with the circuit conductor.

【0015】[0015]

【作用】本発明に従えば、たとえばタングステン、モリ
ブデン、マンガン等の高融点金属から成る配線導体の露
出表面に、ボンディングワイヤの熱圧着時に熱による変
形が生じない程度の硬度、たとえば600以上のビッカ
ース硬度を有するニッケルを主成分とする被覆層を被覆
させることによって、たとえば超音波ボンダーを用いて
ボンディングワイヤを配線導体に接続する際、被覆層が
容易に変形しなくなるため、ボンディングワイヤとの摺
動部に短時間で大きな摩擦熱が発生可能になり、ボンデ
ィングワイヤを配線導体に極めて短時間で強固に接合さ
せることができる。
According to the present invention, the exposed surface of the wiring conductor made of a refractory metal such as tungsten, molybdenum, or manganese has a hardness such that the bonding wire is not deformed by heat during thermocompression bonding, for example, a Vickers of 600 or more. By coating a coating layer having a hardness of nickel as a main component, when the bonding wire is connected to a wiring conductor using, for example, an ultrasonic bonder, the coating layer does not easily deform, so that sliding with the bonding wire occurs. A large amount of frictional heat can be generated in the portion in a short time, and the bonding wire can be firmly bonded to the wiring conductor in an extremely short time.

【0016】また、配線導体の絶縁基体上面に露出した
部位が回路導体と接触していないことによって、配線導
体表面に被覆層をたとえばニッケルメッキで被着させる
際に、回路導体に影響を与えることなく配線導体のみに
被覆層を被着させることが可能となる。
Further, the exposed portion of the wiring conductor on the upper surface of the insulating substrate is not in contact with the circuit conductor, so that the circuit conductor is affected when the coating layer is applied to the surface of the wiring conductor by, for example, nickel plating. It is possible to apply the coating layer only to the wiring conductors.

【0017】[0017]

【実施例】図1は、本発明に係る回路基板の一実施例を
示す断面図である。絶縁基体1の内部および表面に高融
点金属から成る配線導体2が形成されており、さらに露
出した配線導体2の表面を覆うように銅から成る回路導
体4が被着されている。
1 is a sectional view showing an embodiment of a circuit board according to the present invention. A wiring conductor 2 made of a refractory metal is formed inside and on the surface of the insulating substrate 1, and a circuit conductor 4 made of copper is deposited so as to cover the exposed surface of the wiring conductor 2.

【0018】絶縁基体1は、酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体、ガラス−セラミック質焼結体等の電気
絶縁材料から成り、その上面に半導体素子Aや抵抗、コ
ンデンサ等の受動部品Bが搭載される。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, and a glass-ceramic sintered body. A semiconductor element A and passive components B such as resistors and capacitors are mounted on the upper surface thereof.

【0019】まず絶縁基体1の製造方法の一例について
説明すると、絶縁基体1がたとえば酸化アルミニウム質
焼結体から成る場合、1)先ず酸化アルミニウム、酸化
珪素、酸化カルシウム、酸化マグネシウム等のセラミッ
ク原料粉末に適当な有機バインダや溶剤を添加混合して
泥漿状と為し、2)これを周知のドクターブレード法や
カレンダーロール法等のシート成形技術を用いて、複数
枚のセラミックグリーンシートを製造し、3)得られた
セラミックグリーンシートを適当な形状で打抜き加工を
施し、打抜かれたシートを複数枚積層してセラミックグ
リーンシート積層体を作成し、4)最後にセラミックグ
リーンシート積層体を還元雰囲気中約1600℃の温度
で焼成する、という工程を経て絶縁基体1が製造され
る。
First, an example of a method of manufacturing the insulating base 1 will be described. When the insulating base 1 is made of, for example, an aluminum oxide sintered body, 1) First, a ceramic raw material powder of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide or the like. To form a slurry by adding and mixing an appropriate organic binder or solvent with 2), using a sheet forming technique such as the well-known doctor blade method or calender roll method to produce a plurality of ceramic green sheets, 3) The obtained ceramic green sheets are punched in an appropriate shape, and a plurality of punched sheets are laminated to form a ceramic green sheet laminate. 4) Finally, the ceramic green sheet laminate is placed in a reducing atmosphere. The insulating substrate 1 is manufactured through a process of firing at a temperature of about 1600 ° C.

【0020】次に絶縁基体1上に配線導体2を形成する
方法について説明すると、a)先ずタングステン、モリ
ブデン、マンガン等の高融点金属粉末に、適当な有機バ
インダや溶剤を添加して混合することによって、金属ペ
ーストを作成し、b)たとえばスクリーン印刷法等の厚
膜手法を用いて、絶縁基体1と成るセラミックグリーン
シートの上下面および孔内に金属ペーストを塗布して、
所定の導体パターンになるように印刷し、c)次に前述
した工程3、4を経て、グリーンシートとともに焼成す
ることによって、絶縁基体1の内部および上面に配線導
体2が形成される。
Next, the method of forming the wiring conductor 2 on the insulating substrate 1 will be described. A) First, a suitable organic binder or solvent is added to and mixed with a refractory metal powder such as tungsten, molybdenum or manganese. To prepare a metal paste, and b) apply the metal paste to the upper and lower surfaces and the holes of the ceramic green sheet to be the insulating substrate 1 by using a thick film method such as a screen printing method,
The wiring conductor 2 is formed inside and on the upper surface of the insulating substrate 1 by printing so as to form a predetermined conductor pattern, and then through the steps 3 and 4 described above and baking together with the green sheet.

【0021】配線導体2の外表面には、電解メッキ、無
電解メッキ等のメッキ法によってニッケルから成る密着
金属層3が被着されており、この密着金属層3の存在に
よって後述する回路導体4との密着性が強固になる。
An adhesion metal layer 3 made of nickel is deposited on the outer surface of the wiring conductor 2 by a plating method such as electrolytic plating or electroless plating. The existence of the adhesion metal layer 3 causes the circuit conductor 4 to be described later. The adhesion to and becomes stronger.

【0022】なお、密着金属層3に、ホウ素を0.1〜
5.0重量%またはリンを2.0〜15.0重量%程度
含有させることが好ましく、これによって密着金属層3
表面に酸化膜が形成されるのが抑制され、密着金属層3
と回路導体4との密着性がより良好になる。
Boron is added to the adhesion metal layer 3 in an amount of 0.1 to 0.1%.
It is preferable to contain 5.0% by weight or about 2.0 to 15.0% by weight of phosphorus, whereby the adhesion metal layer 3
Formation of an oxide film on the surface is suppressed, and the adhesion metal layer 3
And the circuit conductor 4 have better adhesion.

【0023】また、密着金属層3の厚みが0.1μm未
満であると、回路導体4の組成原子が密着金属層3の中
を拡散して配線導体2に到達して、配線導体2と回路導
体4との密着性が劣る傾向にあり、一方、密着金属層3
の厚みが10μmを越えると、密着金属層3に内部応力
によるクラックが発生し、配線導体2と回路導体4との
密着性が劣化する傾向にある。したがって、密着金属層
3の厚みは0.1〜10.0μmの範囲が好ましい。
When the thickness of the adhesion metal layer 3 is less than 0.1 μm, the composition atoms of the circuit conductor 4 diffuse into the adhesion metal layer 3 and reach the wiring conductor 2, and the wiring conductor 2 and the circuit. The adhesion with the conductor 4 tends to be poor, while the adhesion metal layer 3
If the thickness exceeds 10 μm, cracks are generated in the adhesive metal layer 3 due to internal stress, and the adhesiveness between the wiring conductor 2 and the circuit conductor 4 tends to deteriorate. Therefore, the thickness of the adhesion metal layer 3 is preferably in the range of 0.1 to 10.0 μm.

【0024】配線導体2が露出する外表面の一部には、
銅から成る回路導体4が被着されており、回路導体4と
受動部品Bの各電極端子とは半田を介して接続される。
On a part of the outer surface where the wiring conductor 2 is exposed,
A circuit conductor 4 made of copper is adhered, and the circuit conductor 4 and each electrode terminal of the passive component B are connected via solder.

【0025】次に回路導体4の被着方法について説明す
ると、a)まず銅の粉末に、たとえば酸化鉛、酸化ホウ
素、酸化珪素、酸化アルミニウム、酸化ナトリウム、酸
化カリウム、酸化カルシウムまたは酸化亜鉛等から成る
ガラス粉末と、適当な有機バインダや溶剤とを添加混合
することによって銅ペーストを作成し、b)銅ペースト
の一部と配線導体2とが接触するように、絶縁基体1の
外表面に銅ペーストを印刷塗布し、c)銅ペーストが塗
布された絶縁基体1を、微量な酸素を有する窒素雰囲気
中約900℃の温度で焼成することによって、絶縁基体
1の外表面に回路導体4が被着される。
Next, the method of depositing the circuit conductor 4 will be described. A) First, copper powder, for example, lead oxide, boron oxide, silicon oxide, aluminum oxide, sodium oxide, potassium oxide, calcium oxide or zinc oxide, etc. A copper paste is prepared by adding and mixing the glass powder to be formed and an appropriate organic binder or solvent, and b) copper is formed on the outer surface of the insulating substrate 1 so that a part of the copper paste and the wiring conductor 2 come into contact with each other. The paste is printed and applied, and c) the insulating substrate 1 coated with the copper paste is fired at a temperature of about 900 ° C. in a nitrogen atmosphere having a slight amount of oxygen, so that the circuit conductor 4 is coated on the outer surface of the insulating substrate 1. Be worn.

【0026】なお、回路導体4に含まれるガラスの添加
量が0.2重量%未満であると、回路導体4を絶縁基体
1に強固に被着させるのが困難となる傾向にあり、一
方、ガラスの添加量が8.0重量%を越えると回路導体
4の半田濡れ性が劣化し、回路導体4と部品との半田付
けが困難となる傾向にある。したがって、回路導体4に
添加含有されるガラスの添加量は、0.2〜8.0重量
%の範囲が好ましい。
When the amount of glass contained in the circuit conductor 4 is less than 0.2% by weight, it tends to be difficult to firmly adhere the circuit conductor 4 to the insulating substrate 1. On the other hand, If the amount of glass added exceeds 8.0% by weight, the solder wettability of the circuit conductor 4 is deteriorated, and it tends to be difficult to solder the circuit conductor 4 and components. Therefore, the amount of glass added to the circuit conductor 4 is preferably in the range of 0.2 to 8.0% by weight.

【0027】配線導体2が絶縁基体1の外表面に露出し
た部分にボンディングパッド2aが形成されており、ボ
ンディングパッド2aの部分は回路導体4による被覆が
無く、さらにボンディングパッド2aの表面に、ビッカ
ース硬度で600以上のニッケルを主成分とする金属か
ら成る被覆層5が被着されており、この被覆層5の上か
ら半導体素子Aの各電極と接続するボンディングワイヤ
が接合される。
A bonding pad 2a is formed on the exposed portion of the wiring conductor 2 on the outer surface of the insulating substrate 1. The portion of the bonding pad 2a is not covered with the circuit conductor 4, and the surface of the bonding pad 2a is Vickers. A coating layer 5 made of a metal whose main component is nickel and having a hardness of 600 or more is deposited, and bonding wires for connecting to the respective electrodes of the semiconductor element A are bonded onto the coating layer 5.

【0028】ボンディングパッド2aの表面を、ビッカ
ース硬度で600以上の硬質なニッケルを主成分とする
金属から成る被覆層5で被着することによって、たとえ
ば超音波ボンダーを使用してボンディングパッド2aに
ボンディングワイヤを接続する際に、ボンディングワイ
ヤとの摺動部に大きな摩擦熱が発生することになり、短
時間のうちに強固な接続が可能となる。
By bonding the surface of the bonding pad 2a with a coating layer 5 made of a metal having a Vickers hardness of 600 or more and having a hard nickel content as a main component, the bonding pad 2a is bonded to the bonding pad 2a using, for example, an ultrasonic bonder. When connecting the wires, a large amount of frictional heat is generated in the sliding portion with the bonding wires, so that a strong connection can be made in a short time.

【0029】なお、前記被覆層5は、ニッケルにホウ素
を0.1〜5.0重量%またはリンを2.0〜15.0
重量%含有させるとともに所定の温度で加熱処理するこ
とによってビッカース硬度が600以上の硬質となって
おり、同時にニッケル中にホウ素またはリンを含有させ
ることにより被覆層5表面に酸化膜が形成されるのが抑
制され、被覆層5とボンディングワイヤとの接合が極め
て強固なものとなる。
The coating layer 5 has a nickel content of 0.1 to 5.0 wt% boron or a phosphorus content of 2.0 to 15.0.
The Vickers hardness is hardened to 600 or more by heat treatment at a predetermined temperature together with the content by weight, and at the same time, an oxide film is formed on the surface of the coating layer 5 by including boron or phosphorus in nickel. Is suppressed, and the bond between the coating layer 5 and the bonding wire becomes extremely strong.

【0030】また、被覆層5の厚みが0.5μm未満で
は、強度が低下して、軟らかい密着金属層3の影響を受
けやすくなり、たとえば超音波ボンダーの摺動によって
被覆層5が容易に破壊変形されてしまい、ボンディング
ワイヤ接続が困難になる傾向があり、一方、被覆層5の
厚みが10μmを越えると、被覆層5に内部応力による
クラックが発生してしまう。したがってビッカース硬度
が600以上のニッケルを主成分とする被覆層5の厚み
は、0.5〜10.0μmの範囲が好ましい。
If the thickness of the coating layer 5 is less than 0.5 μm, the strength of the coating layer 5 is lowered and the coating layer 5 is easily affected by the soft adhesive metal layer 3. For example, the coating layer 5 is easily broken by sliding the ultrasonic bonder. When the coating layer 5 has a thickness of more than 10 μm, cracks are generated in the coating layer 5 due to internal stress. Therefore, the thickness of the coating layer 5 containing nickel having a Vickers hardness of 600 or more as a main component is preferably in the range of 0.5 to 10.0 μm.

【0031】被覆層5の形成方法の一例について説明す
ると、ボンディングパッド2aの露出面に、周知の電解
メッキ法や無電解メッキ法を用いてニッケルメッキ層を
所望厚みに被着することによって被覆層5が形成され
る。次に、被覆層5がホウ素を含む場合には約200℃
〜300℃の温度で約10分間加熱処理することによっ
て、またリンを含む場合は約400℃〜500℃の温度
で約10分間加熱処理することによって、被覆層5に含
有されるホウ素またはリンとニッケルとの合金が形成さ
れ、その結果、被覆層5のビッカース硬度を600以上
となすことができる。
An example of a method of forming the coating layer 5 will be described. The coating layer is formed by depositing a nickel plating layer to a desired thickness on the exposed surface of the bonding pad 2a using a well-known electrolytic plating method or electroless plating method. 5 is formed. Next, when the coating layer 5 contains boron, the temperature is about 200 ° C.
The boron or phosphorus contained in the coating layer 5 by heat treatment at a temperature of ˜300 ° C. for about 10 minutes, and when phosphorus is included, at about 400 ° C. to 500 ° C. for about 10 minutes. An alloy with nickel is formed, and as a result, the Vickers hardness of the coating layer 5 can be 600 or more.

【0032】また、ボンディングパッド2aに被覆層5
を被着させる際、銅から成る回路導体4は、ニッケルメ
ッキ液やニッケルメッキ時に通常使用されるアルカリ処
理液、酸処理液に対して侵食され易く、これらの液に侵
食されると絶縁基体1への被着強度が著しく低下し絶縁
基体1より剥離しやすいものとなってしまう。したがっ
て、ボンディングパッド2aに被覆層5を被着させる工
程において、銅から成る回路導体4を保護するため、た
とえばエポキシ樹脂から成るマスキング材で被覆してお
くことが好ましい。
Further, the coating layer 5 is formed on the bonding pad 2a.
When depositing, the circuit conductor 4 made of copper is easily corroded by a nickel plating solution or an alkaline treatment solution or an acid treatment solution usually used at the time of nickel plating. The adhesion strength to the substrate is significantly reduced, and it becomes easier to peel off from the insulating substrate 1. Therefore, in the step of applying the covering layer 5 to the bonding pad 2a, it is preferable to cover the circuit conductor 4 made of copper with a masking material made of, for example, an epoxy resin.

【0033】さらに、回路導体4を完全に被覆保護する
ためには、回路導体4が少しでも露出しないように回路
導体4の周辺にある絶縁基体1表面をも被覆する必要が
ある。たとえば銅から成る回路導体4とボンディングパ
ッド2aとが接触している場合、回路導体4と接触して
いるボンディングパッドの一部もマスキング材で覆われ
ることになる。この場合、ボンディングパッド2a上に
おいて、該ボンディングパッド2aに被着されたニッケ
ルから成る密着金属層3の触媒作用によって、エポキシ
樹脂から成るマスキング材が分解変形して剥離してしま
う。すると、メッキ液等がマスキング材の割れ目から浸
入して、ボンディングパッド2aに接触している回路導
体4にメッキ液等が到達して回路導体4を侵食してしま
う。したがってボンディングパッド2aは回路導体4に
接触しないように配置しておくことが好ましい。
Further, in order to completely cover and protect the circuit conductor 4, it is necessary to cover the surface of the insulating substrate 1 around the circuit conductor 4 so that the circuit conductor 4 is not exposed at all. For example, when the circuit conductor 4 made of copper is in contact with the bonding pad 2a, a part of the bonding pad in contact with the circuit conductor 4 is also covered with the masking material. In this case, on the bonding pad 2a, the masking material made of epoxy resin is decomposed and peeled off due to the catalytic action of the adhesion metal layer 3 made of nickel adhered to the bonding pad 2a. Then, the plating liquid or the like penetrates through the cracks in the masking material, and the plating liquid or the like reaches the circuit conductor 4 in contact with the bonding pad 2a and corrodes the circuit conductor 4. Therefore, it is preferable to arrange the bonding pad 2a so as not to contact the circuit conductor 4.

【0034】こうして得られた回路基板の表面に、半導
体素子Aや抵抗、コンデンサ等の受動部品Bが載置さ
れ、半導体素子Aの各電極と配線導体2とがボンディン
グワイヤを介して電気的に接続され、一方、抵抗やコン
デンサ等の受動部品Bの電極と回路導体4とが半田など
を介して電気的に接続されることによって、小型で高信
頼性の混成集積回路装置を実現することができる。
On the surface of the thus obtained circuit board, the semiconductor element A and the passive component B such as a resistor and a capacitor are placed, and each electrode of the semiconductor element A and the wiring conductor 2 are electrically connected via a bonding wire. On the other hand, the electrodes of the passive component B such as a resistor and a capacitor are electrically connected to the circuit conductor 4 via solder or the like, thereby realizing a compact and highly reliable hybrid integrated circuit device. it can.

【0035】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれ
ば、種々の変更は可能である。たとえば上述の実施例で
はボンディングパッド2aを絶縁基体1上面と同じ面に
配置したが、たとえば図2に示すように、絶縁基体1に
凹部Cを設け、該凹部Cの周辺にボンディングパッド2
aを配置することも可能である。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the bonding pad 2a is arranged on the same surface as the upper surface of the insulating base 1. However, for example, as shown in FIG. 2, the insulating base 1 is provided with a recess C, and the bonding pad 2 is provided around the recess C.
It is also possible to arrange a.

【0036】[0036]

【発明の効果】本発明によれば、たとえば超音波ボンダ
ーを用いてボンディングワイヤを配線導体に接続する
際、被覆層が容易に変形しなくなるため、ボンディング
ワイヤとの摺動部に短時間で大きな摩擦熱が発生可能に
なり、ボンディングワイヤを配線導体に極めて短時間で
強固に接合させることができる。
According to the present invention, when the bonding wire is connected to the wiring conductor by using, for example, an ultrasonic bonder, the coating layer is not easily deformed. Friction heat can be generated, and the bonding wire can be firmly bonded to the wiring conductor in an extremely short time.

【0037】また、配線導体表面に被覆層を被着させる
際に、回路導体の侵食を防止することができる。
Further, it is possible to prevent erosion of the circuit conductor when the coating layer is applied to the surface of the wiring conductor.

【0038】したがって、半導体素子等の能動素子をパ
ッケージ無しで回路基板上に直接搭載する場合、ボンデ
ィングワイヤと回路導体との接合が確実になり、小型で
高信頼性の混成集積回路装置を実現することができる。
Therefore, when an active element such as a semiconductor element is directly mounted on a circuit board without a package, bonding between the bonding wire and the circuit conductor is ensured, and a compact and highly reliable hybrid integrated circuit device is realized. be able to.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る回路基板の一実施例を示す断面図
である。
FIG. 1 is a sectional view showing an embodiment of a circuit board according to the present invention.

【図2】本発明に係る回路基板の他の実施例を示す断面
図である。
FIG. 2 is a sectional view showing another embodiment of the circuit board according to the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁基体 2 配線導体 2a ボンディングパッド 3 密着金属層 4 回路導体 5 被覆層 A 半導体素子 B 受動部品 C 凹部 1 Insulating Base 2 Wiring Conductor 2a Bonding Pad 3 Adhesive Metal Layer 4 Circuit Conductor 5 Covering Layer A Semiconductor Element B Passive Component C Recess

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 内部に高融点金属を含む配線導体を有す
る絶縁基体において、該配線導体の一部を絶縁基体上面
に露出させると共に、該露出した配線導体表面にボンデ
ィングワイヤの熱圧着時に熱による変形が生じない程度
の硬度を有するニッケルを主成分とする被覆層を、前記
露出部に被着させたことを特徴とする回路基板。
1. In an insulating substrate having a wiring conductor containing a refractory metal inside, a part of the wiring conductor is exposed on the upper surface of the insulating substrate, and the exposed wiring conductor surface is exposed to heat during thermocompression bonding. A circuit board, characterized in that a coating layer containing nickel as a main component and having a hardness that does not cause deformation is deposited on the exposed portion.
【請求項2】 前記配線導体の絶縁基体上面に露出した
部位が回路導体と接触していないことを特徴とする請求
項1記載の回路基板。
2. The circuit board according to claim 1, wherein a portion of the wiring conductor exposed on the upper surface of the insulating substrate is not in contact with the circuit conductor.
JP33523393A 1993-12-28 1993-12-28 Circuit board Expired - Fee Related JP3495773B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33523393A JP3495773B2 (en) 1993-12-28 1993-12-28 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33523393A JP3495773B2 (en) 1993-12-28 1993-12-28 Circuit board

Publications (2)

Publication Number Publication Date
JPH07202356A true JPH07202356A (en) 1995-08-04
JP3495773B2 JP3495773B2 (en) 2004-02-09

Family

ID=18286239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33523393A Expired - Fee Related JP3495773B2 (en) 1993-12-28 1993-12-28 Circuit board

Country Status (1)

Country Link
JP (1) JP3495773B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0798851A1 (en) * 1996-03-29 1997-10-01 Tokin Corporation Electronic component
WO1997044819A1 (en) * 1996-05-18 1997-11-27 Robert Bosch Gmbh Process and device for fastening bonding wires to bond lands of a hybrid circuit
JP2004281426A (en) * 2002-11-22 2004-10-07 Kyocera Corp Glass ceramic wiring board
CN1309070C (en) * 2003-01-30 2007-04-04 恩益禧电子股份有限公司 Semiconductor device and its mfg. method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0798851A1 (en) * 1996-03-29 1997-10-01 Tokin Corporation Electronic component
US6376912B1 (en) 1996-03-29 2002-04-23 Tokin Corporation Common mode choke coil of the conductor/insulator stacked type that uses a high machinability substrate and benzocyclobutene as the insulator
WO1997044819A1 (en) * 1996-05-18 1997-11-27 Robert Bosch Gmbh Process and device for fastening bonding wires to bond lands of a hybrid circuit
JP2004281426A (en) * 2002-11-22 2004-10-07 Kyocera Corp Glass ceramic wiring board
CN1309070C (en) * 2003-01-30 2007-04-04 恩益禧电子股份有限公司 Semiconductor device and its mfg. method

Also Published As

Publication number Publication date
JP3495773B2 (en) 2004-02-09

Similar Documents

Publication Publication Date Title
JP3347578B2 (en) Wiring board
JP3495773B2 (en) Circuit board
JP2000286353A (en) Semiconductor device housing package
JP4688314B2 (en) Wiring board manufacturing method
JP3645744B2 (en) Ceramic wiring board
JP2001185838A (en) Ceramic wiring board
JP3420469B2 (en) Wiring board
JP2738600B2 (en) Circuit board
JP4683768B2 (en) Wiring board
JP4364033B2 (en) Wiring board with lead pins
JPH0794839A (en) Circuit board
JP3583018B2 (en) Ceramic wiring board
JP2746813B2 (en) Package for storing semiconductor elements
JP4109391B2 (en) Wiring board
JP2842707B2 (en) Circuit board
JP2690643B2 (en) Wiring board
JPS60107845A (en) Circuit substrate for semiconductor
JP4557461B2 (en) Wiring board
JP3311952B2 (en) Wiring board
JP2001203440A (en) Wiring substrate
JPH04369288A (en) Circuit board
JP2001339014A (en) Wiring board
JPH08125080A (en) Semiconductor device and manufacture thereof
JP2000244087A (en) Wiring board
JP2002016185A (en) Wiring board

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071121

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081121

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091121

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees