JP2002016185A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2002016185A
JP2002016185A JP2000192746A JP2000192746A JP2002016185A JP 2002016185 A JP2002016185 A JP 2002016185A JP 2000192746 A JP2000192746 A JP 2000192746A JP 2000192746 A JP2000192746 A JP 2000192746A JP 2002016185 A JP2002016185 A JP 2002016185A
Authority
JP
Japan
Prior art keywords
layer
wiring
thickness
gold
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000192746A
Other languages
Japanese (ja)
Inventor
Takuya Ouchi
卓也 大内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000192746A priority Critical patent/JP2002016185A/en
Publication of JP2002016185A publication Critical patent/JP2002016185A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16251Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a part of a nickel layer moves and disperses on a gold layer surface to form a nickel oxide there, resulting in a decreased joint strength of solder to a connection pad. SOLUTION: There are provided an insulating base body 1, a wiring layer 2 formed inside and/or on the surface of the insulating base body 1, a connection pad 3 which electrically connects to the wiring layer 2 while jointed to an external electric circuit through a lead-less solder 9. On the surface of the connection pad 3, a nickel layer 10 of thickness 3.0 μm or more, a copper layer 11 of thickness 2-5 μm, and a gold layer 12 of thickness 0.05-0.3 μm are sequentially coated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を収容
する半導体素子収納用パッケージ等に使用される配線基
板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a package for accommodating a semiconductor element for accommodating a semiconductor element.

【0002】[0002]

【従来の技術】従来、配線基板、例えば半導体素子を収
容するための半導体素子収納用パッケージに使用される
配線基板は、一般に酸化アルミニウム質焼結体から成
り、上面に半導体素子を搭載する搭載部を有する絶縁基
体と、搭載部から絶縁基体の下面に導出するタングステ
ンやモリブデン、マンガン等の高融点金属粉末から成る
配線層と、配線層と電気的に接続し、かつ外部電気回路
に錫−鉛半田等の半田を介して接合される接続パッドと
から構成されており、絶縁基体の搭載部に半導体素子を
搭載するとともに半導体素子の各電極を配線層に金バン
プ等の導電接合材を介して機械的、電気的に接続し、し
かる後、絶縁基体上面に金属から成る蓋体を接合し、絶
縁基体と蓋体とから成る容器内部に半導体素子を気密に
封止することによって製品としての半導体装置となる。
2. Description of the Related Art Conventionally, a wiring board, for example, a wiring board used for a semiconductor element housing package for housing a semiconductor element is generally made of an aluminum oxide sintered body, and a mounting portion for mounting the semiconductor element on an upper surface thereof. A wiring layer made of a refractory metal powder such as tungsten, molybdenum, or manganese derived from the mounting portion to the lower surface of the insulating base; and a tin-lead electrically connected to the wiring layer and connected to an external electric circuit. And a connection pad joined via solder such as solder.The semiconductor element is mounted on the mounting portion of the insulating base and each electrode of the semiconductor element is connected to the wiring layer via a conductive bonding material such as a gold bump. By connecting them mechanically and electrically, a metal cover is then joined to the upper surface of the insulating base, and the semiconductor element is hermetically sealed inside a container consisting of the insulating base and the cover. A semiconductor device as a product.

【0003】かかる半導体装置は、絶縁基体の下面に配
線層と電気的に接続して形成された接続パッドを外部電
気回路基板の配線導体に半田を介し接続することによっ
て外部電気回路基板上に実装され、同時に容器内部に収
容される半導体素子の各電極が所定の外部電気回路に接
続されることとなる。
Such a semiconductor device is mounted on an external electric circuit board by connecting a connection pad formed on the lower surface of an insulating base and electrically connected to a wiring layer to a wiring conductor of the external electric circuit board via solder. At the same time, each electrode of the semiconductor element housed in the container is connected to a predetermined external electric circuit.

【0004】また上述の半導体素子収納用パッケージ等
に用いられる配線基板は、タングステン等の高融点金属
粉末から成る配線層の酸化腐食を有効に防止するため
に、また半田の濡れ性、接合性を良好とするために、配
線層の露出表面には一般に耐食性に優れ、かつ半田の濡
れ性、接合性に優れる金層がめっき法等により被着され
ている。
The wiring board used in the above-mentioned package for accommodating a semiconductor element or the like has a solder wettability and a joint property in order to effectively prevent oxidative corrosion of a wiring layer made of a high melting point metal powder such as tungsten. In order to improve the quality, a gold layer which is generally excellent in corrosion resistance and excellent in solder wettability and bonding property is applied to the exposed surface of the wiring layer by plating or the like.

【0005】しかしながら、タングステン等の高融点金
属粉末から成る配線層は金層に対する被着強度が低く、
配線層に金層を直接被着させた後、金層にわずかな外力
が印加されても金層が配線層から容易に剥離してしま
い、その結果、配線層の長期間にわたる酸化腐食の防止
が不可となるとともに配線層と金バンプ等の導電接合材
との接続並びに配線層と外部電気回路基板の配線導体と
の接続が破れ、半導体素子の外部電気回路基板への電気
的接続の信頼性が低くなるという欠点を有していた。
[0005] However, the wiring layer made of a refractory metal powder such as tungsten has a low adhesion strength to the gold layer.
After the gold layer is directly applied to the wiring layer, even if a small external force is applied to the gold layer, the gold layer easily peels off from the wiring layer, thereby preventing the wiring layer from being oxidized and corroded for a long time. And the connection between the wiring layer and the conductive bonding material such as a gold bump and the connection between the wiring layer and the wiring conductor of the external electric circuit board are broken, and the reliability of the electrical connection of the semiconductor element to the external electric circuit board is broken. Has a drawback that it becomes low.

【0006】そこで上記欠点を解消するために従来はタ
ングステン等の高融点金属粉末からなる配線層と金層と
の間に、両者に対して強固に被着接合するニッケルから
なる金属層を介在させることが行われている。
In order to solve the above-mentioned drawbacks, conventionally, a metal layer made of nickel, which is firmly adhered and bonded to both, is interposed between a wiring layer made of a high melting point metal powder such as tungsten and a gold layer. That is being done.

【0007】かかるニッケルからなる金属層をタングス
テン等の高融点金属粉末からなる配線層と金層との間に
介在させた配線基板は、ニッケルからなる金属層によっ
て金層が配線層上に強固に被着し、その結果、金層に外
力が印加されても金層が配線層より剥がれることはな
く、これによって配線層の酸化腐食を長期間にわたって
防止することができるとともに配線層と外部電気回路基
板の配線導体との接続を高信頼性のものすることができ
る。
In a wiring board in which such a metal layer made of nickel is interposed between a wiring layer made of a high melting point metal powder such as tungsten and a gold layer, the gold layer is firmly formed on the wiring layer by the metal layer made of nickel. As a result, even if an external force is applied to the gold layer, the gold layer does not peel off from the wiring layer, which can prevent oxidative corrosion of the wiring layer for a long period of time, and can prevent the wiring layer from being exposed to the external electric circuit. The connection with the wiring conductor of the substrate can be made highly reliable.

【0008】なお、この場合、金層はその厚みが厚い
と、配線層を外部電気回路基板の配線導体に接合する半
田中の錫等の成分との間で脆い金属間化合物を大量に生
成し、外部電気回路基板の配線導体に対する接続信頼性
が低いものとなってしまうことから、通常、約0.5μ
m以下の薄いものに形成されている。
In this case, if the thickness of the gold layer is large, a large amount of brittle intermetallic compound is generated between the gold layer and a component such as tin in the solder for joining the wiring layer to the wiring conductor of the external electric circuit board. Since the connection reliability of the external electric circuit board with respect to the wiring conductor becomes low, it is usually about 0.5 μm.
m or less.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、近時、
低融点ロウ材として人体に対し有害な鉛を含有しない錫
−銀系、錫−金系等の鉛非含有半田(鉛フリー半田)が
多用されつつあり、この鉛非含有半田のロウ付け温度
(約260℃〜300℃)が錫−鉛半田(ロウ付け温度
約200℃)に比べて高いことから、このロウ付け時の
熱によりニッケル層の一部が金層の表面に移動拡散し、
これが酸化されて金層表面に鉛非含有半田に対して接合
性の悪い酸化ニッケルが多量に形成されて、接続パッド
に対する低融点ロウ材の接合性が劣化し、半導体素子の
電極を外部電気回路基板の配線導体との電気的接続の信
頼性が低下してしまい、半導体素子に電気信号を確実、
且つ正確に出し入れすることができなくなるという問題
があった。
However, recently,
Lead-free solder (lead-free solder) such as tin-silver or tin-gold based, which does not contain lead harmful to the human body, is being widely used as a low melting point brazing material. (About 260 ° C. to 300 ° C.) is higher than the tin-lead solder (brazing temperature about 200 ° C.), so that part of the nickel layer moves and diffuses to the surface of the gold layer due to the heat at the time of brazing,
This is oxidized to form a large amount of nickel oxide on the surface of the gold layer, which has poor bonding property to lead-free solder. The reliability of the electrical connection with the wiring conductors of the board is reduced, and the electrical signals are reliably transmitted to the semiconductor element.
In addition, there has been a problem that it is not possible to take in and out correctly.

【0010】またニッケルの金層表面への移動拡散を防
ぐために金層の厚みを厚くすると、低融点ロウ材の錫等
の成分と金との間で脆い金属間化合物が大量に生成し、
低融点ロウ材の接合部の信頼性が劣化してしまう。
When the thickness of the gold layer is increased in order to prevent the migration and diffusion of nickel to the surface of the gold layer, a large amount of brittle intermetallic compound is generated between the component such as tin of the low melting point brazing material and gold,
The reliability of the joint of the low melting point brazing material is degraded.

【0011】本発明は上記欠点に鑑み案出されたもの
で、その目的は接続パッドを外部電気回路基板の配線導
体に鉛非含有の半田を介して強固に接合することがで
き、接続パッドおよび配線層を介して半導体素子に電気
信号を確実、且つ正確に出し入れすることができる配線
基板を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to connect a connection pad to a wiring conductor of an external electric circuit board firmly via lead-free solder. It is an object of the present invention to provide a wiring board capable of reliably and accurately sending and receiving electric signals to and from a semiconductor element via a wiring layer.

【0012】[0012]

【課題を解決するための手段】本発明の配線基板は、絶
縁基体と、該絶縁基体の内部および/または表面に形成
された配線層と、該配線層と電気的に接続し、かつ外部
電気回路に鉛非含有半田を介して接合される接続パッド
とから成る配線基板であって、前記接続パッドはその表
面に厚さが3.0μm以上のニッケル層と、厚さが2μ
m乃至5μmの銅層と、厚さが0.05μm乃至0.3
μmの金層が順次被着されていることを特徴とするもの
である。
A wiring board according to the present invention comprises an insulating base, a wiring layer formed inside and / or on the surface of the insulating base, an electrical connection with the wiring layer, and an external electrical connection. A wiring board comprising a connection pad joined to a circuit via a lead-free solder, wherein the connection pad has a nickel layer having a thickness of 3.0 μm or more on its surface and a nickel layer having a thickness of 2 μm.
m to 5 μm copper layer and thickness of 0.05 μm to 0.3
A gold layer of μm is sequentially applied.

【0013】本発明の配線基板によれば、接続パッドの
表面に、厚さが3.0μm以上のニッケル層、厚さが2
μm乃至5μmの銅層、厚さが0.05μm乃至0.3
μmの金層を順次被着させ、ニッケル層と金層との間に
厚さが2μm乃至5μmの銅層を介在させたことから、
ニッケル層に金層を強固に接着させることができるとと
もに、鉛非含有半田を介して配線層を外部電気回路基板
の配線導体に接合する際に比較的高い熱が加わったとし
てもニッケル層の一部が金層の表面に移動拡散すること
が有効に防止され、その結果、配線層と外部電気回路基
板の配線導体とを鉛非含有半田を介して確実、強固に電
気的接続することができる。
According to the wiring board of the present invention, a nickel layer having a thickness of 3.0 μm or more and a thickness of
μm to 5 μm copper layer, thickness 0.05 μm to 0.3
μm gold layer was sequentially deposited and a copper layer having a thickness of 2 μm to 5 μm was interposed between the nickel layer and the gold layer.
The gold layer can be firmly adhered to the nickel layer, and even if relatively high heat is applied when the wiring layer is bonded to the wiring conductor of the external electric circuit board via the lead-free solder, the nickel layer remains The part is effectively prevented from moving and diffusing to the surface of the gold layer, and as a result, the wiring layer and the wiring conductor of the external electric circuit board can be reliably and firmly electrically connected to each other via the lead-free solder. .

【0014】また同時に本発明の配線基板によれば、金
層の厚さが0.05μm乃至0.3μmと薄いことか
ら、鉛非含有半田中の錫等と金との間で脆い金属間化合
物が大量に生成することはなく、接合部の信頼性を優れ
たものとすることができる。
At the same time, according to the wiring board of the present invention, since the thickness of the gold layer is as thin as 0.05 μm to 0.3 μm, a brittle intermetallic compound is formed between tin and gold in the lead-free solder. Is not generated in large quantities, and the reliability of the joint can be improved.

【0015】[0015]

【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。図1は本発明の配線基板を半導体素子を
収容する半導体素子収納用パッケージに適用した場合の
実施の形態の一例を示す断面図であり、1は絶縁基体、
2は配線層、3は接続パッドである。この絶縁基体1と
配線層2と接続パッド3とで半導体素子4を搭載収容す
るための配線基板5が構成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment in which the wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element.
2 is a wiring layer and 3 is a connection pad. The insulating substrate 1, the wiring layer 2, and the connection pads 3 constitute a wiring board 5 for mounting and housing the semiconductor element 4.

【0016】前記絶縁基体1は、酸化アルミニウム質焼
結体、窒化アルミニウム質焼結体、ムライト質焼結体、
炭化珪素質焼結体等の電気絶縁材料から成り、その上面
に半導体素子4を搭載収容するための凹部1aを有し、
該凹部1a内に半導体素子4が収容される。
The insulating substrate 1 is made of an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body, and has a concave portion 1a for mounting and housing the semiconductor element 4 on its upper surface,
The semiconductor element 4 is accommodated in the recess 1a.

【0017】前記絶縁基体1は、例えば、酸化アルミニ
ウム質焼結体から成る場合には、酸化アルミニウム、酸
化珪素、酸化カルシウム、酸化マグネシウム等の原料粉
末に適当な有機バインダー、溶剤を添加混合して泥漿状
のセラミックスラリーとなすとともに該セラミックスラ
リーを従来周知のドクターブレード法やカレンダーロー
ル法等のシート成形技術を採用してシート状となすこと
によってセラミックグリーンシートを得、しかる後、前
記セラミックグリーンシートを切断加工や打ち抜き加工
により適当な形状とするとともにこれを複数枚積層し、
最後に前記積層されたセラミックグリーンシートを還元
雰囲気中、約1600℃の温度で焼成することによって
製作される。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder and a solvent are added to a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide. A ceramic green sheet is obtained by forming a slurry-like ceramic slurry and forming the ceramic slurry into a sheet by employing a sheet forming technique such as a conventionally known doctor blade method or a calendar roll method. Into a suitable shape by cutting or punching and laminating a plurality of this,
Finally, the laminated ceramic green sheets are manufactured by firing at a temperature of about 1600 ° C. in a reducing atmosphere.

【0018】また前記絶縁基体1は、その凹部1a底面
から下面にかけて多数の配線層2が被着形成されてお
り、これら配線層2の凹部1a底面に露出した部位には
半導体素子4の各電極が金バンプ等の導電性接合材6を
介して電気的に接続され、また絶縁基体1下面に導出さ
れた部位には外部接続用の接続パッド3が電気的に接続
するようにして形成されている。
The insulating substrate 1 has a large number of wiring layers 2 formed thereon from the bottom surface to the lower surface of the concave portion 1a. Are electrically connected via a conductive bonding material 6 such as a gold bump, and a connection pad 3 for external connection is formed at a portion led out to the lower surface of the insulating base 1 so as to be electrically connected. I have.

【0019】前記配線層2及び接続パッド3は収容され
る半導体素子4の各電極を外部電気回路基板7の配線導
体8に電気的に接続する作用をなし、例えば、タングス
テン、モリブデン、マンガン等の高融点金属粉末から成
り、タングステン等の高融点金属粉末に適当な有機バイ
ンダーや溶剤を添加混合して得た金属ペーストを絶縁基
体1となるセラミックグリーンシートに予め従来周知の
スクリーン印刷法により所定パターンに印刷塗布してお
くことによって、絶縁基体1の凹部1a底面から下面に
かけて被着形成される。なお、前記接続パッド3と外部
電気回路基板7の配線導体8との電気的接続は、接続パ
ッド3と配線導体8とを鉛非含有半田9を介して接合す
ることにより行われる。
The wiring layer 2 and the connection pads 3 serve to electrically connect the respective electrodes of the semiconductor element 4 to be accommodated to the wiring conductors 8 of the external electric circuit board 7. For example, tungsten, molybdenum, manganese, etc. A metal paste made of a high melting point metal powder, obtained by adding a suitable organic binder or solvent to a high melting point metal powder such as tungsten, is mixed in a predetermined pattern on a ceramic green sheet serving as an insulating substrate 1 by a conventionally well-known screen printing method. Is formed on the insulating substrate 1 from the bottom surface to the lower surface of the concave portion 1a. The electrical connection between the connection pad 3 and the wiring conductor 8 of the external electric circuit board 7 is performed by joining the connection pad 3 and the wiring conductor 8 via a lead-free solder 9.

【0020】また前記接続パッド3はその表面に、図2
に示すように、厚さが3.0μm以上のニッケル層1
0、厚さが2μm乃至5μmの銅層11、厚さが0.0
5μm乃至0.3μmの金層12が順次被着されてい
る。
The connection pad 3 is provided on its surface as shown in FIG.
As shown in the figure, the nickel layer 1 having a thickness of 3.0 μm or more
0, a copper layer 11 having a thickness of 2 μm to 5 μm, and a thickness of 0.0
A gold layer 12 of 5 μm to 0.3 μm is sequentially applied.

【0021】前記ニッケル層10は、配線層2及び銅層
11のいずれとも密着性に優れることから、配線層2の
表面に銅層11を強固に接合させるための下地層として
作用する。
Since the nickel layer 10 has excellent adhesion to both the wiring layer 2 and the copper layer 11, the nickel layer 10 functions as an underlayer for firmly bonding the copper layer 11 to the surface of the wiring layer 2.

【0022】前記ニッケル層10は、無電解めっき法ま
たは電解めっき法によって形成され、例えば、無電解め
っき法により形成される場合であれば、硫酸ニッケル2
0〜40グラム/リットル、コハク酸ナトリウム40〜
60グラム/リットル、ホウ酸25〜35グラム/リッ
トル、塩化アンモニウム25〜35グラム/リットル、
ジメチルアミンボラン2.5〜4.5グラム/リットル
等から成る無電解ニッケルめっき液を準備するととも
に、接続パッド3の露出面を脱脂、酸処理した後、触媒
剤を含有する溶液に浸漬して活性処理をし、しかる後、
接続パッド3の露出面を60〜65℃に設定された前記
無電解ニッケルめっき液中に約30分間以上浸漬させる
ことによって接続パッド3の露出面に3μm以上の所定
厚みに被着される。
The nickel layer 10 is formed by electroless plating or electrolytic plating. For example, if the nickel layer 10 is formed by electroless plating, nickel sulfate 2
0-40 g / l, sodium succinate 40-
60 g / l, boric acid 25-35 g / l, ammonium chloride 25-35 g / l,
Prepare an electroless nickel plating solution consisting of dimethylamine borane 2.5 to 4.5 g / liter, etc., degrease and acid-treat the exposed surface of the connection pad 3, and then immerse it in a solution containing a catalyst agent. Activate and then
By immersing the exposed surface of the connection pad 3 in the electroless nickel plating solution set at 60 to 65 ° C. for about 30 minutes or more, the exposed surface of the connection pad 3 is adhered to a predetermined thickness of 3 μm or more.

【0023】前記ニッケル層10は、その厚みが3μm
未満となると、配線層2を完全に被覆することができ
ず、銅層11を配線層2の表面に強固に被着させること
ができなくなってしまう。従って、前記ニッケル層10
はその厚さを3μm以上とすることに特定される。
The nickel layer 10 has a thickness of 3 μm
If it is less than the above, the wiring layer 2 cannot be completely covered, and the copper layer 11 cannot be firmly adhered to the surface of the wiring layer 2. Therefore, the nickel layer 10
Is specified to have a thickness of 3 μm or more.

【0024】また前記ニッケル層10はその表面に銅層
11が2μm乃至5μmの厚みに被着されており、該銅
層11はニッケル層10に金層12を強固に被着させる
とともにニッケル層10の一部が金層12の表面に移動
拡散するのを有効に防止する作用をなし、これによって
金層12の表面に鉛非含有半田に対し接合性の悪い酸化
ニッケルが形成されることはなく、接続パッド3を外部
電気回路基板7の配線導体8に鉛非含有半田9を介して
確実に電気的接続することが可能となる。
On the surface of the nickel layer 10, a copper layer 11 having a thickness of 2 μm to 5 μm is adhered. The copper layer 11 allows the gold layer 12 to be firmly adhered to the nickel layer 10 and the nickel layer 10 to be adhered. Does not effectively move and diffuse to the surface of the gold layer 12, thereby preventing nickel oxide having poor bondability to the lead-free solder from being formed on the surface of the gold layer 12. In addition, it is possible to reliably electrically connect the connection pad 3 to the wiring conductor 8 of the external electric circuit board 7 via the lead-free solder 9.

【0025】前記銅層11は、電解めっき法や無電解め
っき法により形成され、例えば、硫酸銅10g/リット
ル、EDTA−2Na30g/リットル、ホルムアルデ
ヒド(37%液)3cc/リットル、および若干のビピ
リジルおよびポリエチレングリコール等から成る無電解
銅めっき液を準備するとともに、前記ニッケル層10の
露出面を脱脂、酸処理した後、ニッケル層10の露出面
を前記無電解銅めっき液中に約10〜30分間浸漬させ
ることによってニッケル層10の露出面に2乃至5μm
の所定厚みに被着される。
The copper layer 11 is formed by an electrolytic plating method or an electroless plating method. For example, copper sulfate 10 g / l, EDTA-2Na 30 g / l, formaldehyde (37% solution) 3 cc / l, and some bipyridyl and After preparing an electroless copper plating solution composed of polyethylene glycol or the like, degrease and acid-treat the exposed surface of the nickel layer 10, the exposed surface of the nickel layer 10 is immersed in the electroless copper plating solution for about 10 to 30 minutes. 2 to 5 μm on the exposed surface of the nickel layer 10 by immersion.
To a predetermined thickness.

【0026】なお、前記銅層11は、その厚みが2μm
未満と薄い場合、ニッケル層10の一部が金層12に移
動拡散するのを有効に防止することができず、また5μ
mを越える厚いものとなると、めっき法によって形成す
る際に銅層11の内部に大きな応力が内在し、この応力
によって接続パッド3の絶縁基体1および配線層2に対
する被着の信頼性が低下してしまう。従って、前記銅層
11はその厚さが2μm乃至5μmの範囲に特定され
る。また、前記銅層11は、無電解めっき法により形成
する場合、一度に3μmを超えて厚く被着させるとめっ
き層の内在応力が大きくなり、銅層11と接続パッド3
の間の被着の信頼性や、接続パッド3と絶縁基体1およ
び配線層2との間の被着の信頼性が低下してしまう危険
性があるため、まず3μm以下の厚みで1次銅層を被着
させ、次に、この1次銅層を約700℃〜900℃の温
度で熱処理して銅層の内在応力を緩和し、その後1次銅
層の上に2次銅層を所定の厚さにまで被着させるように
して形成することが好ましい。
The copper layer 11 has a thickness of 2 μm.
If the thickness is too small, it is not possible to effectively prevent a part of the nickel layer 10 from moving and diffusing into the gold layer 12,
When the thickness is more than m, a large stress is present inside the copper layer 11 when formed by the plating method, and this stress reduces the reliability of adhesion of the connection pad 3 to the insulating base 1 and the wiring layer 2. Would. Therefore, the thickness of the copper layer 11 is specified in the range of 2 μm to 5 μm. Further, when the copper layer 11 is formed by an electroless plating method, if the copper layer 11 is deposited thicker than 3 μm at a time, the internal stress of the plating layer increases, and the copper layer 11 and the connection pad 3
Of the connection pad 3 and the reliability of the connection between the connection pad 3 and the insulating base 1 and the wiring layer 2 may be reduced. Depositing a layer and then heat treating the primary copper layer at a temperature of about 700 ° C. to 900 ° C. to relieve the intrinsic stress of the copper layer, and then deposit a secondary copper layer on the primary copper layer It is preferable to form it so as to adhere to the thickness.

【0027】更に前記銅層11はその表面に金層12が
0.05μm乃至0.3μmの厚みに被着されている。
Further, the copper layer 11 is provided with a gold layer 12 having a thickness of 0.05 μm to 0.3 μm on its surface.

【0028】前記金層12は接続パッド3(実際には接
続パッド3と該接続パッド3の表面に被着されているニ
ッケル層10及び銅層11)の酸化腐蝕を有効に防止す
るとともに接続パッド3に対する鉛非含有半田9の接合
性を向上させる作用をなし、電解めっき法や無電解めっ
き法により形成され、例えば、水酸化カリウム20〜4
0グラム/リットル、エチレンジアミン四酢酸30〜5
0グラム/リットル、リン酸二水素カリウム15〜45
グラム/リットル、シアン化カリウム0.01〜0.1
グラム/リットル、シアン化金カリウム1〜4グラム/
リットル等から成る金めっき液(液温:85〜95℃)
を準備し、前記銅層11の露出面を脱脂、酸処理した
後、銅層11の露出面を前記無電解金めっき液中に約
5.5〜15分間浸漬させることによって銅層11の露
出面に0.05乃至0.3μmの厚みに被着される。
The gold layer 12 effectively prevents oxidative corrosion of the connection pads 3 (actually, the connection pads 3 and the nickel layer 10 and the copper layer 11 deposited on the surface of the connection pads 3), and the connection pads 3 3 is formed by an electrolytic plating method or an electroless plating method, for example, potassium hydroxide 20-4.
0 g / liter, ethylenediaminetetraacetic acid 30-5
0 g / liter, potassium dihydrogen phosphate 15-45
Grams / liter, potassium cyanide 0.01-0.1
G / l, 1-4 g of potassium gold cyanide /
Liter gold plating solution (liquid temperature: 85-95 ° C)
After the exposed surface of the copper layer 11 is degreased and acid-treated, the exposed surface of the copper layer 11 is immersed in the electroless gold plating solution for about 5.5 to 15 minutes to expose the copper layer 11. It is applied to the surface to a thickness of 0.05 to 0.3 μm.

【0029】前記金層12はその厚みが0.05μm乃
至0.3μmと薄いことから、接続パッド3を外部電気
回路基板7の配線導体8に鉛非含有半田9を介して接合
したとき、鉛非含有半田9中の錫等の成分と金との間で
脆い金属間化合物が大量に生成することはなく、接続パ
ッド3と配線導体8との電気的接続の信頼性を優れたも
のとすることができる。
Since the thickness of the gold layer 12 is as thin as 0.05 μm to 0.3 μm, when the connection pad 3 is joined to the wiring conductor 8 of the external electric circuit board 7 via the lead-free solder 9, A large amount of brittle intermetallic compound is not generated between the component such as tin in the non-containing solder 9 and gold, and the reliability of the electrical connection between the connection pad 3 and the wiring conductor 8 is improved. be able to.

【0030】なお、前記金層12はその厚さが0.05
μm未満となると、接続パッド3(実際には接続パッド
3と該接続パッド3の表面に被着されているニッケル層
10及び銅層11)の酸化腐蝕を有効に防止することが
できず、また、0.3μmを超えて厚くすると鉛非含有
半田9中の錫等の成分との間で生成する脆い金属間化合
物量が多くなり、接続パッド3の配線導体8に対する電
気的接続の信頼性が低下してしまう。従って、前記金層
12はその厚さが0.05μm乃至0.3μmの範囲に
特定される。
The gold layer 12 has a thickness of 0.05.
When the thickness is less than μm, the oxidation corrosion of the connection pads 3 (actually, the connection layers 3 and the nickel layer 10 and the copper layer 11 deposited on the surface of the connection pads 3) cannot be effectively prevented, and When the thickness exceeds 0.3 μm, the amount of brittle intermetallic compounds generated with components such as tin in the lead-free solder 9 increases, and the reliability of the electrical connection of the connection pad 3 to the wiring conductor 8 increases. Will drop. Therefore, the thickness of the gold layer 12 is specified in the range of 0.05 μm to 0.3 μm.

【0031】かくして本発明の配線基板によれば、絶縁
基体1の凹部1a底面に半導体素子3をガラスや樹脂、
ロウ材等の接着剤を介して接着固定するとともにこの半
導体素子3の各電極を配線層2に導電性接合材6を介し
て電気的に接続し、しかる後、絶縁基体1の上面に金属
やセラミックスから成る蓋体13をガラスや樹脂、ロウ
材等の封止材を介して接合させ、絶縁基体1と蓋体13
とから成る容器内部に半導体素子3を気密に収容するこ
とによって製品としての半導体装置が完成する。
Thus, according to the wiring substrate of the present invention, the semiconductor element 3 is formed on the bottom surface of the concave portion 1a of the insulating base 1 by glass or resin,
The electrodes of the semiconductor element 3 are bonded and fixed via an adhesive such as a brazing material, and are electrically connected to the wiring layer 2 via a conductive bonding material 6. The lid 13 made of ceramics is joined via a sealing material such as glass, resin, brazing material or the like, and the insulating base 1 and the lid 13 are joined together.
A semiconductor device as a product is completed by housing the semiconductor element 3 in an airtight manner inside the container consisting of

【0032】なお、本発明の配線基板は上述の実施例に
限定されるものではなく、本発明の要旨を逸脱しない範
囲であれば種々の変更は可能であり、例えば、上述の実
施例では本発明の配線基板を半導体素子を収容する半導
体素子収納用パッケージに適用したが、混成集積回路基
板等の他の用途に適用してもよい。
The wiring board of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Although the wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element, it may be applied to other uses such as a hybrid integrated circuit board.

【0033】[0033]

【発明の効果】本発明の配線基板によれば、接続パッド
の表面に、厚さが3.0μm以上のニッケル層、厚さが
2μm乃至5μmの銅層、厚さが0.05μm乃至0.
3μmの金層を順次被着させ、ニッケル層と金層との間
に厚さが2μm〜5μmの銅層を介在させたことから、
ニッケル層に金層を強固に接着させることができるとと
もに、鉛非含有半田を介して配線層を外部電気回路基板
の配線導体に接合する際に比較的高い熱が加わったとし
てもニッケル層の一部が金層の表面に移動拡散すること
が有効に防止され、その結果、配線層と外部電気回路基
板の配線導体とを鉛非含有半田を介して確実、強固に電
気的接続することができる。
According to the wiring board of the present invention, a nickel layer having a thickness of 3.0 μm or more, a copper layer having a thickness of 2 μm to 5 μm, and a thickness of 0.05 μm to 0.
Since a 3 μm gold layer was sequentially deposited and a copper layer having a thickness of 2 μm to 5 μm was interposed between the nickel layer and the gold layer,
The gold layer can be firmly adhered to the nickel layer, and even if relatively high heat is applied when the wiring layer is bonded to the wiring conductor of the external electric circuit board via the lead-free solder, the nickel layer remains The part is effectively prevented from moving and diffusing to the surface of the gold layer, and as a result, the wiring layer and the wiring conductor of the external electric circuit board can be reliably and firmly electrically connected to each other via the lead-free solder. .

【0034】また同時に本発明の配線基板によれば、金
層の厚さが0.05μm乃至0.3μmと薄いことか
ら、鉛非含有半田中の錫等と金との間で脆い金属間化合
物が大量に生成することはなく、接合部の信頼性を優れ
たものとすることができる。
At the same time, according to the wiring board of the present invention, since the thickness of the gold layer is as thin as 0.05 μm to 0.3 μm, a brittle intermetallic compound is formed between tin and gold in the lead-free solder. Is not generated in large quantities, and the reliability of the joint can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。
FIG. 1 is a sectional view showing an embodiment in which a wiring board of the present invention is applied to a package for housing a semiconductor element.

【図2】図1の要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of FIG.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 1a・・・凹部 2・・・・配線層 3・・・・接続パッド 4・・・・半導体素子 5・・・・配線基板 6・・・・導電性接合材 7・・・・外部電気回路基板 8・・・・配線導体 9・・・・鉛非含有半田 10・・・ニッケル層 11・・・銅層 12・・・金層 13・・・蓋体 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Depression 2 ... Wiring layer 3 ... Connection pad 4 ... Semiconductor element 5 ... Wiring board 6 ... Conductive bonding material 7 ···································································································································································································································································· lid · lid ·

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基体と、該絶縁基体の内部および/ま
たは表面に形成された配線層と、該配線層と電気的に接
続し、かつ外部電気回路に鉛非含有半田を介して接合さ
れる接続パッドとから成る配線基板であって、前記接続
パッドはその表面に厚さが3.0μm以上のニッケル層
と、厚さが2μm乃至5μmの銅層と、厚さが0.05
μm乃至0.3μmの金層が順次被着されていることを
特徴とする配線基板。
An insulating substrate, a wiring layer formed inside and / or on the surface of the insulating substrate, electrically connected to the wiring layer, and joined to an external electric circuit via a lead-free solder. A connection pad comprising: a nickel layer having a thickness of 3.0 μm or more; a copper layer having a thickness of 2 to 5 μm;
A wiring substrate, comprising a gold layer having a thickness of from 0.3 μm to 0.3 μm.
JP2000192746A 2000-06-27 2000-06-27 Wiring board Pending JP2002016185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000192746A JP2002016185A (en) 2000-06-27 2000-06-27 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000192746A JP2002016185A (en) 2000-06-27 2000-06-27 Wiring board

Publications (1)

Publication Number Publication Date
JP2002016185A true JP2002016185A (en) 2002-01-18

Family

ID=18691833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000192746A Pending JP2002016185A (en) 2000-06-27 2000-06-27 Wiring board

Country Status (1)

Country Link
JP (1) JP2002016185A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005034597A1 (en) * 2003-10-03 2005-04-14 Shinko Electric Industries Co., Ltd. Pad structure of wiring board and wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005034597A1 (en) * 2003-10-03 2005-04-14 Shinko Electric Industries Co., Ltd. Pad structure of wiring board and wiring board
JPWO2005034597A1 (en) * 2003-10-03 2006-12-21 新光電気工業株式会社 Wiring board pad structure and wiring board
JP4619292B2 (en) * 2003-10-03 2011-01-26 新光電気工業株式会社 Wiring board pad structure and wiring board

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