JP2003115655A - Wiring substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a peel occurs between a wiring layer and a copper plated layer and blister occurs to the copper plated layer. SOLUTION: A wiring substrate is adhered by a wiring layer 2 to which the electrode of an electronic part 3 is connected through a connection member 5 formed of a low melt point brazing filler metal. A copper-boron plated layer 6, a copper plated layer 7, an alloy layer 8 of at least one kind of palladium, platinum, rhodium and ruthenium and phosphorus, and a gold plated layer 9 are adhered, in the order, to the surface of a region with which the electrode of at least the electronic part 3 of the wiring layer 2 is joined through the connection member 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a semiconductor element housing package for housing a semiconductor element, a hybrid integrated circuit board and the like.

[0002]

2. Description of the Related Art Conventionally, a wiring board used for a package for accommodating semiconductor elements, a hybrid integrated circuit board, or the like generally has an insulating base made of an electrically insulating material such as an aluminum oxide sintered body or an aluminum nitride sintered body. A wiring layer made of a metal material such as tungsten, molybdenum, manganese or the like deposited on the surface and inside of the insulating base, and on the surface of the insulating base, an electronic component such as a semiconductor element, a capacitive element, or a resistor. And each electrode of the electronic component is electrically connected to the wiring layer via a low melting point brazing material such as tin-lead solder or tin-silver solder.

Such a wiring board is formed on the external electric circuit board by connecting a predetermined portion of the wiring layer to the wiring conductor of the external electric circuit board through a low melting point brazing material such as tin-lead solder or tin-silver solder. Each electrode of the electronic component mounted and simultaneously mounted on the wiring board is also electrically connected to a predetermined external electric circuit.

In addition, the wiring board usually has a copper plating layer and a gold plating layer sequentially deposited on the exposed surface of the wiring layer, and the copper plating layer lowers the electrical resistance of the wiring layer and lowers the wiring layer. The melting point brazing material is bonded well, and the gold plating layer effectively prevents oxidative corrosion of the wiring layer and the copper plating layer.

[0005]

However, in the above-mentioned conventional wiring board, the average grain size of the crystal grains of copper forming the copper plating layer is generally about 1 μm, and metals such as tungsten, molybdenum and manganese are included. It is larger than the uneven diameter (recess: approximately 1 μm) on the surface of the wiring layer made of a material. Therefore, even if a copper plating layer is deposited on the surface of the wiring layer, the copper plating layer does not sufficiently enter into the concave portion of the surface of the wiring layer, and many voids are formed between the wiring layer surface and the copper plating layer, As a result, the adhesion strength between the copper plating layer and the wiring layer is weakened, and the copper plating layer is easily separated from the wiring layer by the application of an external force, or enters into the void between the wiring layer surface and the copper plating layer. The gas has a drawback in that it greatly expands due to heat or the like when connecting an electrode of an electronic component to a wiring layer via a low melting point brazing material, causing blistering or the like in the copper plating layer.

Further, when heat or the like is applied to the wiring layer to bond the electrode of the electronic component through the low melting point brazing material, the copper of the copper plating layer is moved and diffused to the surface of the gold plating layer to form copper. There are also problems that the oxide layer is formed, the wettability of the low melting point brazing material with respect to the wiring layer is deteriorated, and the contact electric resistance is significantly increased.

The present invention has been devised in view of the above-mentioned conventional drawbacks, and its purpose is to effectively prevent the occurrence of peeling between the wiring layer and the copper plating layer and blister in the copper plating layer. Then, by providing a copper plating layer and a gold plating layer firmly on the wiring layer, an electrode of an electronic component can be firmly attached and connected to the wiring layer via a low melting point brazing material. It is in.

[0008]

A wiring board of the present invention is a wiring board formed by depositing a wiring layer on an insulating substrate to which electrodes of electronic parts are connected via a low melting point brazing material. A copper-boron plating layer having a boron content of 0.3% by weight or more, a copper plating layer, and palladium on the surface of a region of the wiring layer where at least the electrode of the electronic component is bonded via the low melting point brazing material. , An alloy layer of at least one of platinum, rhodium, and ruthenium and phosphorus, and a gold plating layer are sequentially deposited.

The wiring board of the present invention is characterized in that the thickness of the copper-boron plating layer is 0.03 μm or more.

Furthermore, the present invention is characterized in that the average grain size of the copper crystal grains forming the copper-boron plating layer is 0.02 μm or less.

Furthermore, the present invention is characterized in that the phosphorus content of the alloy layer of at least one of palladium, platinum, rhodium and ruthenium and phosphorus is in the range of 0.2% by weight to 2% by weight. It is a thing.

According to the wiring board of the present invention, at least the electrode of the electronic component is connected to the surface of the wiring layer through the low melting point brazing material, and the content of boron is 0.3% by weight or more. Even if there are many irregularities on the surface of the wiring layer because the copper-boron plating layer having a small crystal grain size of less than 0.3 μm is deposited, the copper-boron crystals are well admitted into the depressions. The wiring layer and the copper-boron plating layer are firmly adhered without forming a void between them, and on the copper-boron plating layer, a copper plating layer having good adhesion to each, and palladium, platinum, At least one of rhodium and ruthenium
Since the alloy layer of the seed and phosphorus and the gold plating layer are successively deposited, the copper plating layer, the alloy layer and the gold plating layer can be firmly deposited on the wiring layer, and the wiring is formed by the copper plating layer. The electric resistance of the layer can be made small, and furthermore, the gold plating layer effectively prevents the oxidation corrosion of the wiring layer, and the electrode of the electronic component is securely and firmly electrically connected to the wiring layer through the low melting point brazing material. Can be connected.

At the same time, an alloy layer of at least one of palladium, platinum, rhodium, and ruthenium formed between the copper-plated layer and the gold-plated layer and phosphorus, particularly the copper layer of the copper-plated layer by the action of the phosphorus component. Diffusion to the surface of the gold plating layer is extremely effectively prevented, and even if heat etc. when joining the electrode of the electronic component to the wiring layer via the low melting point brazing material acts on the surface of the gold plating layer. A layer is rarely formed, which makes it possible to maintain good bondability of the low melting point brazing material to the wiring layer.

[0014]

DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment in which the wiring board of the present invention is applied to a package for accommodating semiconductor elements, 1 is an insulating substrate, and 2 is a wiring layer. The insulating substrate 1 and the wiring layer 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.

The insulating substrate 1 is an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body, and has a mounting portion for mounting the semiconductor element 3 on its upper surface, and the wiring layer 2 exposed on the surface of the mounting portion is provided with the semiconductor element 3 of the semiconductor element 3. The electrodes are connected via a connecting member 5 made of a low melting point brazing material such as solder.

When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, an appropriate organic binder and solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. A sheet-shaped ceramic green sheet (ceramic green sheet) is obtained by forming the slurry into a slurry and adopting the sheet-forming technology such as the doctor blade method and the calendar roll method which are well known in the art. Produced by cutting and punching the green sheets to form an appropriate shape, stacking a plurality of these, and finally firing the stacked ceramic green sheets in a reducing atmosphere at a temperature of about 1600 ° C. To be done.

A large number of wiring layers 2 are formed on the insulating substrate 1 from the mounting portion on the upper surface to the lower surface, and the electrodes of the semiconductor element 3 are formed on the exposed portions of the mounting portion of the wiring layer 2. Are electrically connected via a connecting member 5 made of a low melting point brazing material such as tin-lead solder, and the wiring conductor of the external electric circuit board is connected to the lower surface of the insulating substrate 1 by solder or the like. It is electrically connected through the melting point brazing material.

The wiring layer 2 is connected to the semiconductor element 3
Functioning to connect the electrodes of the to an external electrical circuit, for example,
It is formed of a metal material containing at least one of tungsten, molybdenum and manganese such as tungsten, molybdenum, molybdenum / manganese, tungsten / copper, molybdenum / copper, and tungsten / molybdenum / copper.

For the wiring layer 2, a metal paste obtained by adding and mixing a suitable organic binder or solvent to a metal powder such as tungsten is formed in a predetermined pattern on a ceramic green sheet to be the insulating substrate 1 in advance by a conventionally known screen printing method. By printing and coating on, the insulating substrate 1 is adhered and formed at a predetermined position.

As shown in FIG. 2, the wiring layer 2 has a copper-boron plating layer 6, at least in a region where electrodes of the semiconductor element 3 are connected via a connecting member 5 made of a low melting point brazing material.
Copper plating layer 7, alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus, gold plating layer 9
Are being applied in sequence.

The copper-boron plating layer 6 comprises the wiring layer 2, a copper plating layer 7, an alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus, and a gold plating layer 9.
Acts as a base metal layer for depositing with good adhesion.

The copper-boron plating layer 6 may be formed, for example, by subjecting the surface of the wiring layer 2 to palladium activation, and then using the wiring layer 2 with a boron-based compound containing a boron-based compound such as dimethylamineborane as a reducing agent. The surface of the wiring layer 2 is adhered to a predetermined thickness by immersing it in an electrolytic copper plating solution for a predetermined time. In this case, the copper-boron plating layer 6 effectively suppresses grain growth of crystal grains by the action of the boron component contained by eutectoid deposition, and the average grain size of the copper-boron crystal grains is For example, it becomes as small as 0.3 μm or less,
As a result, even if there are a large number of irregularities on the surface of the wiring layer 2, copper-boron crystals satisfactorily enter the concave portions and form voids between the wiring layer 2 and the copper-boron plating layer 6. Can be firmly adhered to each other.

The copper-boron plating layer 6 is made of copper-
In order to reduce the average grain size of boron crystal grains to 0.3 μm or less, the content of boron must be 0.3% by weight or more, and the content of boron should be 0.3% by weight or more. As a result, the grain size of the copper-boron crystal grains is 0.
The thickness is 3 μm or less, and even if the surface of the wiring layer 2 has irregularities, the wiring layer 2 enters into the recesses well and adheres firmly to the wiring layer 2.

In the copper-boron plating layer 6, if the average grain size of copper-boron crystal grains is set to 0.02 μm or less, the wiring layer 2 having the copper-boron plating layer 6 having irregularities on its surface is formed.
This makes it possible to adhere more firmly. Therefore, the copper-boron plating layer 6 preferably has an average grain size of copper-boron crystal grains of 0.02 μm or less, and more preferably 0.01 μm or less.

The average particle size of the copper-boron plating layer 6 is set to 0.02 μm or less by setting the boron content in the copper-boron plating layer 6 to about 0.5% by weight or more. 0.5 considering characteristics such as electrical conductivity
It is preferably in the range of 4% by weight to 4% by weight.

Further, if the thickness of the copper-boron plating layer 6 is less than 0.03 μm, it is difficult to completely cover the entire surface of the wiring layer 2, and the copper plating layer 7, palladium, platinum, and It tends to be difficult to firmly adhere the alloy layer 8 of at least one of rhodium and ruthenium and phosphorus, and the gold plating layer 9 to the wiring layer 2.
Therefore, the copper-boron plating layer 6 has a thickness of 0.
It is preferably set to 03 μm or more.

Furthermore, on the surface of the copper-boron plating layer 6, the copper-boron plating layer 6 and palladium described later,
A copper plating layer 7 having excellent adhesion to any of the alloy layers 8 of at least one of platinum, rhodium and ruthenium and phosphorus is adhered and formed.

The copper plating layer 7 firmly adheres to the wiring layer 2 an alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium and ruthenium and has a low melting point such as solder for the wiring layer 2. This serves to firmly adhere the brazing material and reduce the electric resistance of the wiring layer 2.

The copper plating layer 7 is formed by, for example, immersing the wiring layer 2 on which the copper-boron plating layer 6 is deposited in an electroless copper plating solution using formalin as a reducing agent for a predetermined time. The surface of the boron plating layer 6 is formed to have a predetermined thickness. In this case, when an electroless copper plating solution using formalin as a reducing agent is used, the plating solution has an autocatalytic action, so that the surface of the copper-boron plating layer 6 is not subjected to activation treatment and the copper plating layer 7 is formed. To a predetermined thickness,
In addition, it becomes possible to adhere the copper-boron plating layer 6 with high bonding strength.

Since the copper plating layer 7 is formed of formalin or the like containing no eutectoid component and has a high purity, the bondability of the wiring layer 2 to the low melting point brazing material such as solder is greatly improved. At the same time, the electric resistance becomes a very small value, and it becomes possible to effectively prevent the occurrence of attenuation in the electric signal or the like propagating through the wiring layer 2.

On the surface of the copper plating layer 7, at least one of palladium, platinum, rhodium and ruthenium, which has excellent adhesion to the copper plating layer 7 and any of the gold plating layers 9 described later, is provided. An alloy layer 8 of seed and phosphorus is deposited.

The alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus is used for connecting the electrode of the semiconductor element 3 to the wiring layer 2 through a low melting point brazing material such as tin-lead solder. It acts to prevent the copper of the copper plating layer 7 from moving and diffusing to the surface of the gold plating layer 9 described later by the heat acting on the.

The alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus can be formed by a thin film forming technique such as a plating method, a vapor deposition method, an ion plating method and a sputtering method. When it is composed of palladium-phosphorus, a wiring layer is formed in an electroless palladium-phosphorus plating solution containing a palladium compound such as palladium chloride and a phosphorus-based reducing agent such as sodium hypophosphite and sodium phosphite as main components. By dipping the exposed surface of No. 2 (the copper plating layer 7 is adhered) for a predetermined time, it can be adhered and formed to a predetermined thickness.

On the copper plating layer 7, palladium-
When the phosphorus alloy layer 8 is adhered and formed, the migration and diffusion of copper can be very effectively prevented by the action of the phosphorus component contained, and for example, the thickness of the gold plating layer 9 described later can be 0.0
The copper of the copper plating layer 7 moves to the surface of the gold plating layer 9 even when it is made extremely thin as less than 5 μm or when brazing is performed at a relatively high temperature using a so-called lead-free solder such as tin-silver solder. Therefore, the bondability and contact resistance of the low melting point brazing material to the wiring layer 2 can be maintained well without forming an oxide layer. Further, at least one of palladium, platinum, rhodium and ruthenium and phosphorus When the phosphorus content of the alloy layer 8 is less than 0.2% by weight, when a low melting point brazing material such as tin-silver solder which is brazed at a relatively high temperature is used, the copper of the copper plating layer 7 is plated with gold. It tends to be difficult to effectively prevent the migration and diffusion into the layer 9, and when it exceeds 2% by weight, the catalytically inactive phosphorus component increases and the formation rate by the plating method becomes slow, resulting in mass productivity. It becomes low and practicality is impaired Or it is, tend to be or become liable to crack such as an internal stress is increased. Therefore, the alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium, and ruthenium preferably has a phosphorus content in the range of 0.2% by weight to 2% by weight.

Further, the above-mentioned palladium, platinum, rhodium,
When the thickness of the alloy layer 8 of at least one kind of ruthenium and phosphorus is less than 0.05 μm, it becomes difficult to prevent the copper of the copper plating layer 7 from migrating and diffusing to the surface of the gold plating layer 9 and 3 μm. If it exceeds, the internal stress generated and remaining at the time of formation becomes large, which may make it difficult to firmly adhere to the copper plating layer 7. Therefore, the alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium, and ruthenium has a thickness of 0.05 μm to
The thickness is preferably in the range of 3 μm, and when the thickness of the gold plating layer 9 to be described later is very thin, less than 0.05 μm, the thickness of 0.3 μm or more in order to prevent oxidative corrosion of the copper plating layer 7. It is preferable that

Furthermore, a gold plating layer 9 is deposited on the surface of the alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium and ruthenium.

The gold plating layer 9 prevents the wiring layer 2, the copper-boron plating layer 6 and the copper plating layer 7 from being oxidized and corroded, and improves the bondability of the low melting point brazing material to the wiring layer 2. Act.

The gold plating layer 9 is formed by, for example, adding palladium, platinum, rhodium, or ruthenium in an electroless gold plating solution containing, as a main component, potassium gold cyanide which is a gold compound and ethylenediaminetetraacetic acid which is a complexing agent. The wiring layer 2 on which the alloy layer 8 of at least one of the above and phosphorus is deposited is dipped for a predetermined time so that the surface of the alloy layer 8 is deposited to a predetermined thickness.

Further, the gold plating layer 9 has a thickness of 0.
If the thickness exceeds 8 μm, when the electrode of the semiconductor element 3 is connected to the wiring layer 2 via the connecting member 5 made of a low melting point brazing material such as solder, the low melting point brazing material 5 becomes brittle between tin and gold. There is a risk that the intermetallic compound is generated and the reliability of the connection of the semiconductor element 3 to the wiring layer 2 is significantly reduced. Therefore, the gold plating layer 9 has a thickness of 0.8 μm.
It is preferably set to m or less.

On the other hand, the insulating base 1 on which the semiconductor element 3 is mounted is joined to the upper surface of the lid 10 via a sealing material made of resin, glass, brazing material or the like.
The semiconductor element 3 is hermetically sealed inside by the insulating base 1.

The lid 10 is made of a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, or a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. For example, in the case of an aluminum oxide sintered body, a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide or the like is formed into a bowl shape by adopting a conventionally known press forming method and It is formed by firing at a temperature of about 1500 ° C.

Thus, according to the semiconductor element housing package to which the wiring board of the present invention is applied, the electrode of the semiconductor element 3 is soldered to the wiring layer 2 exposed on the surface of the mounting portion on the upper surface of the insulating substrate 1 to form a low melting point solder. Electrically and mechanically via a connecting member 5 made of a material, and thereafter, the lid 10 is joined to the upper surface of the insulating base 1 via a sealing material made of resin, glass, brazing material, etc. A semiconductor device as a final product is completed by hermetically accommodating the semiconductor element 3 inside a container composed of the base 1 and the lid 10.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, the wiring board of the present invention can be used as a semiconductor element. It may be applied to a wiring board for a hybrid integrated circuit on which electronic parts such as a capacitor and a resistor are mounted.

[0044]

According to the wiring board of the present invention, at least the electrode of the electronic component is connected to the surface of the wiring layer through the low melting point brazing material, and the content of boron is 0.3% by weight or more.
Even if there are many irregularities on the surface of the wiring layer because the copper-boron plating layer having a small crystal grain size of boron of 0.3 μm or less is deposited, the copper-boron crystals are well formed in the depressions. The wiring layer and the copper-boron plated layer are firmly adhered without forming a void between them, and the copper-boron plated layer and the copper plated layer having good adhesion to each other,
Since the alloy layer of at least one of palladium, platinum, rhodium, and ruthenium and phosphorus and the gold plating layer are sequentially deposited, the wiring layer can be firmly deposited with the copper plating layer and the gold plating layer. Along with the copper plating layer can reduce the electrical resistance of the wiring layer,
Further, it becomes possible to securely and firmly electrically connect the electrode of the electronic component to the wiring layer through the low melting point brazing material while effectively preventing the oxidation corrosion of the wiring layer by the gold plating layer.

At the same time, an alloy layer of at least one of palladium, platinum, rhodium, and ruthenium formed between the copper plating layer and the gold plating layer and phosphorus, particularly the copper of the copper plating layer by the action of the phosphorus component. Diffusion to the surface of the gold plating layer is extremely effectively prevented, and even if heat etc. when joining the electrode of the electronic component to the wiring layer via the low melting point brazing material acts on the surface of the gold plating layer. A layer is rarely formed, which makes it possible to maintain good bondability of the low melting point brazing material to the wiring layer.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an embodiment in which a wiring board of the present invention is applied to a semiconductor element housing package.

FIG. 2 is a cross-sectional view of an essential part of the wiring board shown in FIG.

[Explanation of symbols]

1 ... Insulating substrate 2 ... Wiring layer 3 ... Semiconductor element 4 ... Wiring substrate 5 ... Connection member 6 ... Copper-boron plating layer 7 ... Copper plating layer 8 ...- Alloy layer of at least one of palladium, platinum, rhodium and ruthenium and phosphorus 9-Gold plating layer 10-lid

Claims (4)

[Claims] 1. A wiring board comprising an insulating base and a wiring layer formed by depositing a wiring layer on which electrodes of an electronic component are connected via a low melting point brazing material, wherein at least an electrode of the electronic component is low in the wiring layer. A copper-boron plating layer having a boron content of 0.3% by weight or more, a copper plating layer, and at least one of palladium, platinum, rhodium, and ruthenium on the surface of the region to be joined via the melting point brazing material. A wiring board, wherein an alloy layer with phosphorus and a gold plating layer are sequentially deposited. 2. The thickness of the copper-boron plating layer is 0.03.
The wiring board according to claim 1, wherein the wiring board has a thickness of at least μm. 3. The wiring board according to claim 1, wherein the average grain size of the crystal grains of copper forming the copper-boron plating layer is 0.02 μm or less. 4. The phosphorus content of the alloy layer of phosphorus with at least one of palladium, platinum, rhodium and ruthenium is in the range of 0.2% by weight to 2% by weight. The wiring board described.