JP2003115655A - Wiring substrate - Google Patents
Wiring substrateInfo
- Publication number
- JP2003115655A JP2003115655A JP2001310161A JP2001310161A JP2003115655A JP 2003115655 A JP2003115655 A JP 2003115655A JP 2001310161 A JP2001310161 A JP 2001310161A JP 2001310161 A JP2001310161 A JP 2001310161A JP 2003115655 A JP2003115655 A JP 2003115655A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- copper
- plating layer
- wiring
- boron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子を収容
するための半導体素子収納用パッケージや混成集積回路
基板等に用いられる配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a semiconductor element housing package for housing a semiconductor element, a hybrid integrated circuit board and the like.
【0002】[0002]
【従来の技術】従来、半導体素子収納用パッケージや混
成集積回路基板等に用いられる配線基板は、一般に、酸
化アルミニウム質焼結体や窒化アルミニウム質焼結体等
の電気絶縁材料から成る絶縁基体と、該絶縁基体の表面
および内部に被着されたタングステン、モリブデン、マ
ンガン等の金属材料から成る配線層とにより形成されて
おり、絶縁基体の表面に半導体素子や容量素子、抵抗器
等の電子部品を搭載するとともに該電子部品の各電極を
配線層に錫−鉛半田、錫−銀系半田等の低融点ロウ材を
介して電気的に接続するようになっている。2. Description of the Related Art Conventionally, a wiring board used for a package for accommodating semiconductor elements, a hybrid integrated circuit board, or the like generally has an insulating base made of an electrically insulating material such as an aluminum oxide sintered body or an aluminum nitride sintered body. A wiring layer made of a metal material such as tungsten, molybdenum, manganese or the like deposited on the surface and inside of the insulating base, and on the surface of the insulating base, an electronic component such as a semiconductor element, a capacitive element, or a resistor. And each electrode of the electronic component is electrically connected to the wiring layer via a low melting point brazing material such as tin-lead solder or tin-silver solder.
【0003】かかる配線基板は、配線層の所定部位を外
部電気回路基板の配線導体に錫−鉛半田、錫−銀系半田
等の低融点ロウ材を介し接続することによって外部電気
回路基板上に実装され、同時に配線基板に搭載されてい
る電子部品の各電極も所定の外部電気回路に電気的に接
続されることとなる。Such a wiring board is formed on the external electric circuit board by connecting a predetermined portion of the wiring layer to the wiring conductor of the external electric circuit board through a low melting point brazing material such as tin-lead solder or tin-silver solder. Each electrode of the electronic component mounted and simultaneously mounted on the wiring board is also electrically connected to a predetermined external electric circuit.
【0004】また前記配線基板は、通常、配線層の露出
表面に銅めっき層および金めっき層が順次被着されてお
り、該銅めっき層によって配線層の電気抵抗を低く、か
つ配線層に対する低融点ロウ材の接合を良好としてお
り、また金めっき層によって配線層及び銅めっき層の酸
化腐食を有効に防止している。In addition, the wiring board usually has a copper plating layer and a gold plating layer sequentially deposited on the exposed surface of the wiring layer, and the copper plating layer lowers the electrical resistance of the wiring layer and lowers the wiring layer. The melting point brazing material is bonded well, and the gold plating layer effectively prevents oxidative corrosion of the wiring layer and the copper plating layer.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の配線基板においては、銅めっき層を形成している銅
の結晶粒の平均粒径が一般に約1μmであり、タングス
テン、モリブデン、マンガン等の金属材料から成る配線
層表面の凹凸径(凹部:約1μm)に比べて大きい。そ
のため配線層表面に銅めっき層を被着させても銅めっき
層は配線層表面の凹部内に十分入り込まずに配線層表面
と銅めっき層との間に多数の空隙部が形成されてしま
い、その結果、銅めっき層と配線層との密着強度が弱く
なり、外力印加によって銅めっき層が配線層より容易に
剥離したり、配線層表面と銅めっき層との間の空隙部に
入り込んでいる気体が配線層に電子部品の電極を低融点
ロウ材を介して接続する際の熱等によって大きく膨張
し、銅めっき層にフクレ等が発生してしまうという欠点
があった。However, in the above-mentioned conventional wiring board, the average grain size of the crystal grains of copper forming the copper plating layer is generally about 1 μm, and metals such as tungsten, molybdenum and manganese are included. It is larger than the uneven diameter (recess: approximately 1 μm) on the surface of the wiring layer made of a material. Therefore, even if a copper plating layer is deposited on the surface of the wiring layer, the copper plating layer does not sufficiently enter into the concave portion of the surface of the wiring layer, and many voids are formed between the wiring layer surface and the copper plating layer, As a result, the adhesion strength between the copper plating layer and the wiring layer is weakened, and the copper plating layer is easily separated from the wiring layer by the application of an external force, or enters into the void between the wiring layer surface and the copper plating layer. The gas has a drawback in that it greatly expands due to heat or the like when connecting an electrode of an electronic component to a wiring layer via a low melting point brazing material, causing blistering or the like in the copper plating layer.
【0006】また、前記配線層に、電子部品の電極を低
融点ロウ材を介して接合する際の熱等が作用すると、銅
めっき層の銅が金めっき層の表面に移動拡散して銅の酸
化物層を形成してしまい、配線層に対する低融点ロウ材
の濡れ性が劣化したり、接触電気抵抗が著しく増大して
しまったりするという問題もあった。Further, when heat or the like is applied to the wiring layer to bond the electrode of the electronic component through the low melting point brazing material, the copper of the copper plating layer is moved and diffused to the surface of the gold plating layer to form copper. There are also problems that the oxide layer is formed, the wettability of the low melting point brazing material with respect to the wiring layer is deteriorated, and the contact electric resistance is significantly increased.
【0007】本発明は上記従来の欠点に鑑み案出された
もので、その目的は配線層と銅めっき層との間に剥離が
発生したり銅めっき層にフクレ等が生じるのを有効に防
止し、配線層に銅めっき層及び金めっき層を強固に被着
させることによって配線層に電子部品の電極を低融点ロ
ウ材を介して強固に取着接続することができる配線基板
を提供することにある。The present invention has been devised in view of the above-mentioned conventional drawbacks, and its purpose is to effectively prevent the occurrence of peeling between the wiring layer and the copper plating layer and blister in the copper plating layer. Then, by providing a copper plating layer and a gold plating layer firmly on the wiring layer, an electrode of an electronic component can be firmly attached and connected to the wiring layer via a low melting point brazing material. It is in.
【0008】[0008]
【課題を解決するための手段】本発明の配線基板は、絶
縁基体に電子部品の電極が低融点ロウ材を介して接続さ
れる配線層を被着形成して成る配線基板であって、前記
配線層のうち少なくとも電子部品の電極が低融点ロウ材
を介して接合される領域の表面に、ホウ素の含有量が
0.3重量%以上の銅−ホウ素めっき層と、銅めっき層
と、パラジウム、白金、ロジウム、ルテニウムの少なく
とも1種とリンとの合金層と、金めっき層とを順次被着
させたことを特徴とするものである。A wiring board of the present invention is a wiring board formed by depositing a wiring layer on an insulating substrate to which electrodes of electronic parts are connected via a low melting point brazing material. A copper-boron plating layer having a boron content of 0.3% by weight or more, a copper plating layer, and palladium on the surface of a region of the wiring layer where at least the electrode of the electronic component is bonded via the low melting point brazing material. , An alloy layer of at least one of platinum, rhodium, and ruthenium and phosphorus, and a gold plating layer are sequentially deposited.
【0009】また本発明の配線基板は、前記銅−ホウ素
めっき層の厚みが0.03μm以上であることを特徴と
するものである。The wiring board of the present invention is characterized in that the thickness of the copper-boron plating layer is 0.03 μm or more.
【0010】更に本発明は、前記銅−ホウ素めっき層を
形成する銅の結晶粒の平均粒径が0.02μm以下であ
ることを特徴とするものである。Furthermore, the present invention is characterized in that the average grain size of the copper crystal grains forming the copper-boron plating layer is 0.02 μm or less.
【0011】また更に本発明は、前記パラジウム、白
金、ロジウム、ルテニウムの少なくとも1種とリンとの
合金層のリン含有量が0.2重量%〜2重量%の範囲で
あることを特徴とするものである。Furthermore, the present invention is characterized in that the phosphorus content of the alloy layer of at least one of palladium, platinum, rhodium and ruthenium and phosphorus is in the range of 0.2% by weight to 2% by weight. It is a thing.
【0012】本発明の配線基板によれば、少なくとも電
子部品の電極が低融点ロウ材を介して接続される配線層
の表面に、ホウ素の含有量が0.3重量%以上で銅−ホ
ウ素の結晶粒径が0.3μm未満と小さい銅−ホウ素め
っき層を被着させたことから配線層の表面に多数の凹凸
があったとしても、この凹部内に銅−ホウ素の結晶が良
好に入り込んで配線層と銅−ホウ素めっき層とが間に空
隙部を形成することなく強固に被着し、また銅−ホウ素
めっき層上に、各々の密着性が良好な銅めっき層と、パ
ラジウム、白金、ロジウム、ルテニウムの少なくとも1
種とリンとの合金層と、金めっき層とを順次被着させた
ことから配線層に銅めっき層、合金層および金めっき層
を強固に被着させることができるとともに前記銅めっき
層によって配線層の電気抵抗を小さなものとなすことが
でき、更に金めっき層によって配線層の酸化腐食を有効
に防止しつつ配線層に電子部品の電極を低融点ロウ材を
介して確実、強固に電気的接続することができる。According to the wiring board of the present invention, at least the electrode of the electronic component is connected to the surface of the wiring layer through the low melting point brazing material, and the content of boron is 0.3% by weight or more. Even if there are many irregularities on the surface of the wiring layer because the copper-boron plating layer having a small crystal grain size of less than 0.3 μm is deposited, the copper-boron crystals are well admitted into the depressions. The wiring layer and the copper-boron plating layer are firmly adhered without forming a void between them, and on the copper-boron plating layer, a copper plating layer having good adhesion to each, and palladium, platinum, At least one of rhodium and ruthenium
Since the alloy layer of the seed and phosphorus and the gold plating layer are successively deposited, the copper plating layer, the alloy layer and the gold plating layer can be firmly deposited on the wiring layer, and the wiring is formed by the copper plating layer. The electric resistance of the layer can be made small, and furthermore, the gold plating layer effectively prevents the oxidation corrosion of the wiring layer, and the electrode of the electronic component is securely and firmly electrically connected to the wiring layer through the low melting point brazing material. Can be connected.
【0013】また同時に、前記銅めっき層と金めっき層
との間に形成したパラジウム、白金、ロジウム、ルテニ
ウムの少なくとも1種とリンとの合金層、特にリン成分
の作用により銅めっき層の銅の金めっき層表面への拡散
が極めて効果的に防止され、配線層に電子部品の電極を
低融点ロウ材を介して接合する際の熱等が作用したとし
ても金めっき層表面に銅の酸化物層が形成されることは
ほとんどなく、これによって配線層に対する低融点ロウ
材の接合性を良好なものに維持することができる。At the same time, an alloy layer of at least one of palladium, platinum, rhodium, and ruthenium formed between the copper-plated layer and the gold-plated layer and phosphorus, particularly the copper layer of the copper-plated layer by the action of the phosphorus component. Diffusion to the surface of the gold plating layer is extremely effectively prevented, and even if heat etc. when joining the electrode of the electronic component to the wiring layer via the low melting point brazing material acts on the surface of the gold plating layer. A layer is rarely formed, which makes it possible to maintain good bondability of the low melting point brazing material to the wiring layer.
【0014】[0014]
【発明の実施の形態】次に本発明を添付図面に基づいて
詳細に説明する。図1は、本発明の配線基板を半導体素
子収納用パッケージに適用した場合の一実施例を示す断
面図であり、1は絶縁基体、2は配線層である。この絶
縁基体1と配線層2とで半導体素子3を搭載するための
配線基板4が構成される。DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment in which the wiring board of the present invention is applied to a package for accommodating semiconductor elements, 1 is an insulating substrate, and 2 is a wiring layer. The insulating substrate 1 and the wiring layer 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.
【0015】前記絶縁基体1は、酸化アルミニウム質焼
結体、ムライト質焼結体、窒化アルミニウム質焼結体、
炭化珪素質焼結体、ガラスセラミック焼結体等の電気絶
縁材料から成り、その上面に半導体素子3を搭載する搭
載部を有し、該搭載部表面に露出した配線層2に半導体
素子3の電極が半田等の低融点ロウ材からなる接続部材
5を介して接続される。The insulating substrate 1 is an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body, and has a mounting portion for mounting the semiconductor element 3 on its upper surface, and the wiring layer 2 exposed on the surface of the mounting portion is provided with the semiconductor element 3 of the semiconductor element 3. The electrodes are connected via a connecting member 5 made of a low melting point brazing material such as solder.
【0016】前記絶縁基体1は、例えば、酸化アルミニ
ウム質焼結体から成る場合には、酸化アルミニウム、酸
化珪素、酸化カルシウム、酸化マグネシウム等の原料粉
末に適当な有機バインダー、溶剤を添加混合して泥漿状
のセラミックスラリーとなすとともに該セラミックスラ
リーを従来周知のドクターブレード法やカレンダーロー
ル法等のシート成形技術を採用してシート状のセラミッ
クグリーンシート(セラミック生シート)を得、しかる
後、前記セラミックグリーンシートに切断加工や打ち抜
き加工等を施して適当な形状とするとともにこれを複数
枚積層し、最後に前記積層されたセラミックグリーンシ
ートを還元雰囲気中、約1600℃の温度で焼成するこ
とによって製作される。When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, an appropriate organic binder and solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. A sheet-shaped ceramic green sheet (ceramic green sheet) is obtained by forming the slurry into a slurry and adopting the sheet-forming technology such as the doctor blade method and the calendar roll method which are well known in the art. Produced by cutting and punching the green sheets to form an appropriate shape, stacking a plurality of these, and finally firing the stacked ceramic green sheets in a reducing atmosphere at a temperature of about 1600 ° C. To be done.
【0017】また前記絶縁基体1は、その上面の搭載部
から下面にかけて多数の配線層2が被着形成されてお
り、該配線層2の搭載部に露出した部位には半導体素子
3の各電極が錫−鉛半田等の低融点ロウ材から成る接続
部材5を介して電気的に接続され、また絶縁基体1の下
面に導出された部位には外部電気回路基板の配線導体が
半田等の低融点ロウ材を介して電気的に接続される。A large number of wiring layers 2 are formed on the insulating substrate 1 from the mounting portion on the upper surface to the lower surface, and the electrodes of the semiconductor element 3 are formed on the exposed portions of the mounting portion of the wiring layer 2. Are electrically connected via a connecting member 5 made of a low melting point brazing material such as tin-lead solder, and the wiring conductor of the external electric circuit board is connected to the lower surface of the insulating substrate 1 by solder or the like. It is electrically connected through the melting point brazing material.
【0018】前記配線層2は、接続される半導体素子3
の電極を外部電気回路に接続する作用をなし、例えば、
タングステンやモリブデン、モリブデン/マンガン、タ
ングステン/銅、モリブデン/銅、タングステン/モリ
ブデン/銅、等のタングステン、モリブデン、マンガン
の少なくとも1種を主成分とする金属材料により形成さ
れている。The wiring layer 2 is connected to the semiconductor element 3
Functioning to connect the electrodes of the to an external electrical circuit, for example,
It is formed of a metal material containing at least one of tungsten, molybdenum and manganese such as tungsten, molybdenum, molybdenum / manganese, tungsten / copper, molybdenum / copper, and tungsten / molybdenum / copper.
【0019】前記配線層2は、タングステン等の金属粉
末に適当な有機バインダーや溶剤を添加混合して得た金
属ペーストを絶縁基体1となるセラミックグリーンシー
トに予め従来周知のスクリーン印刷法により所定パター
ンに印刷塗布しておくことによって、絶縁基体1の所定
位置に被着形成される。For the wiring layer 2, a metal paste obtained by adding and mixing a suitable organic binder or solvent to a metal powder such as tungsten is formed in a predetermined pattern on a ceramic green sheet to be the insulating substrate 1 in advance by a conventionally known screen printing method. By printing and coating on, the insulating substrate 1 is adhered and formed at a predetermined position.
【0020】前記配線層2は、図2に示す如く、少なく
とも半導体素子3の電極が低融点ロウ材から成る接続部
材5を介して接続される領域に銅−ホウ素めっき層6、
銅めっき層7、パラジウム、白金、ロジウム、ルテニウ
ムの少なくとも1種とリンとの合金層8、金めっき層9
が順次被着されている。As shown in FIG. 2, the wiring layer 2 has a copper-boron plating layer 6, at least in a region where electrodes of the semiconductor element 3 are connected via a connecting member 5 made of a low melting point brazing material.
Copper plating layer 7, alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus, gold plating layer 9
Are being applied in sequence.
【0021】前記銅−ホウ素めっき層6は、配線層2に
銅めっき層7、パラジウム、白金、ロジウム、ルテニウ
ムの少なくとも1種とリンとの合金層8、金めっき層9
を密着性良く被着させる下地金属層として作用する。The copper-boron plating layer 6 comprises the wiring layer 2, a copper plating layer 7, an alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus, and a gold plating layer 9.
Acts as a base metal layer for depositing with good adhesion.
【0022】前記銅−ホウ素めっき層6は、例えば、配
線層2の表面にパラジウム活性を施した後、この配線層
2を、ジメチルアミンボラン等のホウ素系化合物を還元
剤として用いたホウ素系無電解銅めっき液中に所定時間
浸漬することによって配線層2の表面に所定厚みに被着
される。この場合、前記銅−ホウ素めっき層6は被着時
に共析して含有されるホウ素成分の作用により結晶粒の
粒成長が効果的に抑制されて銅―ホウ素の結晶粒の平均
粒径は、例えば、0.3μm以下の小さなものとなり、
その結果、配線層2表面に多数の凹凸があったとして
も、この凹部内に銅−ホウ素の結晶が良好に入り込んで
配線層2と銅−ホウ素めっき層6とは間に空隙部を形成
することなく強固に密着させることができる。The copper-boron plating layer 6 may be formed, for example, by subjecting the surface of the wiring layer 2 to palladium activation, and then using the wiring layer 2 with a boron-based compound containing a boron-based compound such as dimethylamineborane as a reducing agent. The surface of the wiring layer 2 is adhered to a predetermined thickness by immersing it in an electrolytic copper plating solution for a predetermined time. In this case, the copper-boron plating layer 6 effectively suppresses grain growth of crystal grains by the action of the boron component contained by eutectoid deposition, and the average grain size of the copper-boron crystal grains is For example, it becomes as small as 0.3 μm or less,
As a result, even if there are a large number of irregularities on the surface of the wiring layer 2, copper-boron crystals satisfactorily enter the concave portions and form voids between the wiring layer 2 and the copper-boron plating layer 6. Can be firmly adhered to each other.
【0023】なお、前記銅−ホウ素めっき層6は、銅−
ホウ素の結晶粒の平均粒径を0.3μm以下の小さなも
のとするにはホウ素の含有量を0.3重量%以上として
おく必要があり、ホウ素の含有量を0.3重量%以上と
しておくことによって銅−ホウ素の結晶粒の粒径は0.
3μm以下となり、配線層2の表面に凹凸を有するとし
ても凹部内に良好に入り込んで配線層2に強固に被着す
る。The copper-boron plating layer 6 is made of copper-
In order to reduce the average grain size of boron crystal grains to 0.3 μm or less, the content of boron must be 0.3% by weight or more, and the content of boron should be 0.3% by weight or more. As a result, the grain size of the copper-boron crystal grains is 0.
The thickness is 3 μm or less, and even if the surface of the wiring layer 2 has irregularities, the wiring layer 2 enters into the recesses well and adheres firmly to the wiring layer 2.
【0024】また前記銅−ホウ素めっき層6は、銅−ホ
ウ素の結晶粒の平均粒径を0.02μm以下としておく
と銅−ホウ素めっき層6を表面に凹凸を有する配線層2
により一層強固に被着させることができる。従って、前
記銅−ホウ素めっき層6は、銅−ホウ素の結晶粒の平均
粒径を0.02μm以下としておくことが好ましく、よ
り好適には0.01μm以下としておくのがよい。In the copper-boron plating layer 6, if the average grain size of copper-boron crystal grains is set to 0.02 μm or less, the wiring layer 2 having the copper-boron plating layer 6 having irregularities on its surface is formed.
This makes it possible to adhere more firmly. Therefore, the copper-boron plating layer 6 preferably has an average grain size of copper-boron crystal grains of 0.02 μm or less, and more preferably 0.01 μm or less.
【0025】前記銅−ホウ素めっき層6の平均粒径を
0.02μm以下とするには、銅−ホウ素めっき層6中
のホウ素含有率を0.5重量%程度以上とすることによ
って行なわれ、電気伝導性等の特性を考慮すれば0.5
重量%〜4重量%の範囲とすることが好ましい。The average particle size of the copper-boron plating layer 6 is set to 0.02 μm or less by setting the boron content in the copper-boron plating layer 6 to about 0.5% by weight or more. 0.5 considering characteristics such as electrical conductivity
It is preferably in the range of 4% by weight to 4% by weight.
【0026】更に前記銅−ホウ素めっき層6は、その厚
みが0.03μm未満の薄いものとなると配線層2の表
面全体を完全に覆うことが難しく、後述する銅めっき層
7、パラジウム、白金、ロジウム、ルテニウムの少なく
とも1種とリンとの合金層8、および金めっき層9を配
線層2に強固に被着させるのが困難となる傾向にある。
従って、前記銅−ホウ素めっき層6は、その厚みを0.
03μm以上としておくことが好ましい。Further, if the thickness of the copper-boron plating layer 6 is less than 0.03 μm, it is difficult to completely cover the entire surface of the wiring layer 2, and the copper plating layer 7, palladium, platinum, and It tends to be difficult to firmly adhere the alloy layer 8 of at least one of rhodium and ruthenium and phosphorus, and the gold plating layer 9 to the wiring layer 2.
Therefore, the copper-boron plating layer 6 has a thickness of 0.
It is preferably set to 03 μm or more.
【0027】また更に、前記銅−ホウ素めっき層6の表
面には該銅−ホウ素めっき層6と後述するパラジウム、
白金、ロジウム、ルテニウムの少なくとも1種とリンと
の合金層8のいずれに対しても密着性が優れた銅めっき
層7が被着形成されている。Furthermore, on the surface of the copper-boron plating layer 6, the copper-boron plating layer 6 and palladium described later,
A copper plating layer 7 having excellent adhesion to any of the alloy layers 8 of at least one of platinum, rhodium and ruthenium and phosphorus is adhered and formed.
【0028】前記銅めっき層7は、配線層2にパラジウ
ム、白金、ロジウム、ルテニウムの少なくとも1種とリ
ンとの合金層8を強固に被着させ、かつ配線層2に対し
半田等の低融点ロウ材を強固に被着させるとともに配線
層2の電気抵抗を下げる作用をなす。The copper plating layer 7 firmly adheres to the wiring layer 2 an alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium and ruthenium and has a low melting point such as solder for the wiring layer 2. This serves to firmly adhere the brazing material and reduce the electric resistance of the wiring layer 2.
【0029】前記銅めっき層7は、例えば、銅−ホウ素
めっき層6を被着させた配線層2を、ホルマリンを還元
剤として用いた無電解銅めっき液中に所定時間浸漬する
ことによって銅−ホウ素めっき層6の表面に所定厚みに
被着形成される。この場合、ホルマリンを還元剤として
用いた無電解銅めっき液を用いると、このめっき液が自
己触媒作用を有するため銅−ホウ素めっき層6の表面に
活性処理を施すことなく、銅めっき層7を所定厚みに、
かつ銅−ホウ素めっき層6に対し接合強度を大として被
着させることが可能となる。The copper plating layer 7 is formed by, for example, immersing the wiring layer 2 on which the copper-boron plating layer 6 is deposited in an electroless copper plating solution using formalin as a reducing agent for a predetermined time. The surface of the boron plating layer 6 is formed to have a predetermined thickness. In this case, when an electroless copper plating solution using formalin as a reducing agent is used, the plating solution has an autocatalytic action, so that the surface of the copper-boron plating layer 6 is not subjected to activation treatment and the copper plating layer 7 is formed. To a predetermined thickness,
In addition, it becomes possible to adhere the copper-boron plating layer 6 with high bonding strength.
【0030】なお、前記銅めっき層7は、共析成分を含
有しないホルマリン等を用いて形成され高純度であるこ
とから配線層2の半田等の低融点ロウ材に対する接合性
が大きく改善されるとともに電気抵抗が極めて小さい値
となり、配線層2を伝搬する電気信号等に減衰が発生す
るのを有効に防止することが可能となる。Since the copper plating layer 7 is formed of formalin or the like containing no eutectoid component and has a high purity, the bondability of the wiring layer 2 to the low melting point brazing material such as solder is greatly improved. At the same time, the electric resistance becomes a very small value, and it becomes possible to effectively prevent the occurrence of attenuation in the electric signal or the like propagating through the wiring layer 2.
【0031】また、前記銅めっき層7はその表面に、該
銅めっき層7と、後述する金めっき層9のいずれに対し
ても密着性が優れた、パラジウム、白金、ロジウム、ル
テニウムの少なくとも1種とリンとの合金層8が被着形
成されている。On the surface of the copper plating layer 7, at least one of palladium, platinum, rhodium and ruthenium, which has excellent adhesion to the copper plating layer 7 and any of the gold plating layers 9 described later, is provided. An alloy layer 8 of seed and phosphorus is deposited.
【0032】前記パラジウム、白金、ロジウム、ルテニ
ウムの少なくとも1種とリンとの合金層8は、錫−鉛半
田等の低融点ロウ材を介して半導体素子3の電極を配線
層2に接続する際に作用する熱により銅めっき層7の銅
が後述する金めっき層9の表面に移動拡散することを阻
止する作用をなす。The alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus is used for connecting the electrode of the semiconductor element 3 to the wiring layer 2 through a low melting point brazing material such as tin-lead solder. It acts to prevent the copper of the copper plating layer 7 from moving and diffusing to the surface of the gold plating layer 9 described later by the heat acting on the.
【0033】前記パラジウム、白金、ロジウム、ルテニ
ウムの少なくとも1種とリンとの合金層8は、めっき法
や蒸着法、イオンプレーティング法、スパッタリング法
等の薄膜形成技術により形成することができ、例えばパ
ラジウム−リンから成る場合であれば、塩化パラジウム
等のパラジウム化合物と、次亜リン酸ナトリウム、亜リ
ン酸ナトリウム等のリン系還元剤を主成分とする無電解
パラジウム−リンめっき液中に配線層2の露出表面(銅
めっき層7が被着)を所定時間浸漬することにより、所
定厚みに被着形成することができる。The alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and phosphorus can be formed by a thin film forming technique such as a plating method, a vapor deposition method, an ion plating method and a sputtering method. When it is composed of palladium-phosphorus, a wiring layer is formed in an electroless palladium-phosphorus plating solution containing a palladium compound such as palladium chloride and a phosphorus-based reducing agent such as sodium hypophosphite and sodium phosphite as main components. By dipping the exposed surface of No. 2 (the copper plating layer 7 is adhered) for a predetermined time, it can be adhered and formed to a predetermined thickness.
【0034】なお、前記銅めっき層7上にパラジウム−
リン合金層8を被着形成した場合、含有するリン成分の
作用により銅の移動拡散を極めて効果的に阻止すること
ができ、例えば、後述する金めっき層9の厚みを0.0
5μm未満と極めて薄いものとした場合や、錫−銀系半
田等のいわゆる鉛フリー半田を用いて比較的高温でロウ
付けした場合でも、銅めっき層7の銅が金めっき層9の
表面に移動して酸化物層を作ることはなく、配線層2に
対する低融点ロウ材の接合性や接触抵抗を良好に維持す
ることができるまた、前記パラジウム、白金、ロジウ
ム、ルテニウムの少なくとも1種とリンとの合金層8の
リン含有量が0.2重量%未満となると、錫−銀系半田
等の比較的高温でロウ付けする低融点ロウ材を使用する
場合、銅めっき層7の銅が金めっき層9に移動拡散する
のを有効に阻止することが困難となる傾向にあり、また
2重量%を超えると触媒不活性なリン成分が増大してめ
っき法による形成速度が遅くなり、量産性が低いものと
なって実用性が損なわれてしまったり、内部応力が増大
してクラック等を生じ易くなったりする傾向がある。従
って、前記パラジウム、白金、ロジウム、ルテニウムの
少なくとも1種とリンとの合金層8は、リンの含有量を
0.2重量%〜2重量%の範囲としておくことが好まし
い。On the copper plating layer 7, palladium-
When the phosphorus alloy layer 8 is adhered and formed, the migration and diffusion of copper can be very effectively prevented by the action of the phosphorus component contained, and for example, the thickness of the gold plating layer 9 described later can be 0.0
The copper of the copper plating layer 7 moves to the surface of the gold plating layer 9 even when it is made extremely thin as less than 5 μm or when brazing is performed at a relatively high temperature using a so-called lead-free solder such as tin-silver solder. Therefore, the bondability and contact resistance of the low melting point brazing material to the wiring layer 2 can be maintained well without forming an oxide layer. Further, at least one of palladium, platinum, rhodium and ruthenium and phosphorus When the phosphorus content of the alloy layer 8 is less than 0.2% by weight, when a low melting point brazing material such as tin-silver solder which is brazed at a relatively high temperature is used, the copper of the copper plating layer 7 is plated with gold. It tends to be difficult to effectively prevent the migration and diffusion into the layer 9, and when it exceeds 2% by weight, the catalytically inactive phosphorus component increases and the formation rate by the plating method becomes slow, resulting in mass productivity. It becomes low and practicality is impaired Or it is, tend to be or become liable to crack such as an internal stress is increased. Therefore, the alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium, and ruthenium preferably has a phosphorus content in the range of 0.2% by weight to 2% by weight.
【0035】更に、前記パラジウム、白金、ロジウム、
ルテニウムの少なくとも1種とリンとの合金層8は、そ
の厚みが0.05μm未満となると銅めっき層7の銅が
金めっき層9の表面に移動拡散するのを阻止することが
困難となり、3μmを超えると形成時に発生して残留す
る内部応力が大きくなって銅めっき層7に対して強固に
被着することが困難となるおそれがある。従って、前記
パラジウム、白金、ロジウム、ルテニウムの少なくとも
1種とリンとの合金層8は、その厚みを0.05μm〜
3μmの範囲とすることが好ましく、また後述する金め
っき層9の厚みを0.05μm未満と非常に薄いものと
する場合には、銅めっき層7の酸化腐食を防ぐために
0.3μm以上の厚みとすることが好ましい。Further, the above-mentioned palladium, platinum, rhodium,
When the thickness of the alloy layer 8 of at least one kind of ruthenium and phosphorus is less than 0.05 μm, it becomes difficult to prevent the copper of the copper plating layer 7 from migrating and diffusing to the surface of the gold plating layer 9 and 3 μm. If it exceeds, the internal stress generated and remaining at the time of formation becomes large, which may make it difficult to firmly adhere to the copper plating layer 7. Therefore, the alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium, and ruthenium has a thickness of 0.05 μm to
The thickness is preferably in the range of 3 μm, and when the thickness of the gold plating layer 9 to be described later is very thin, less than 0.05 μm, the thickness of 0.3 μm or more in order to prevent oxidative corrosion of the copper plating layer 7. It is preferable that
【0036】また更に、前記パラジウム、白金、ロジウ
ム、ルテニウムの少なくとも1種とリンとの合金層8の
表面には金めっき層9が被着形成されている。Furthermore, a gold plating layer 9 is deposited on the surface of the alloy layer 8 of phosphorus with at least one of palladium, platinum, rhodium and ruthenium.
【0037】前記金めっき層9は、配線層2、銅−ホウ
素めっき層6および銅めっき層7の酸化腐食を防止する
とともに、配線層2に対する低融点ロウ材の接合性を良
好なものとする作用をなす。The gold plating layer 9 prevents the wiring layer 2, the copper-boron plating layer 6 and the copper plating layer 7 from being oxidized and corroded, and improves the bondability of the low melting point brazing material to the wiring layer 2. Act.
【0038】前記金めっき層9は、例えば、金化合物で
あるシアン化金カリウムおよび錯化剤であるエチレンジ
アミン四酢酸を主成分とする無電解金めっき液中に、前
記パラジウム、白金、ロジウム、ルテニウムの少なくと
も1種とリンとの合金層8が被着されている配線層2を
所定時間浸漬させることによって前記合金層8の表面に
所定厚みに被着される。The gold plating layer 9 is formed by, for example, adding palladium, platinum, rhodium, or ruthenium in an electroless gold plating solution containing, as a main component, potassium gold cyanide which is a gold compound and ethylenediaminetetraacetic acid which is a complexing agent. The wiring layer 2 on which the alloy layer 8 of at least one of the above and phosphorus is deposited is dipped for a predetermined time so that the surface of the alloy layer 8 is deposited to a predetermined thickness.
【0039】更に前記金めっき層9は、その厚みが0.
8μmを超えて厚くすると、半導体素子3の電極を配線
層2に半田等の低融点ロウ材からなる接続部材5を介し
て接続したとき、低融点ロウ材5の錫と金との間で脆い
金属間化合物が生成され、半導体素子3の配線層2に対
する接続の信頼性が大きく低下してしまう危険性があ
る。従って、前記金めっき層9は、その厚さを0.8μ
m以下としておくことが好ましい。Further, the gold plating layer 9 has a thickness of 0.
If the thickness exceeds 8 μm, when the electrode of the semiconductor element 3 is connected to the wiring layer 2 via the connecting member 5 made of a low melting point brazing material such as solder, the low melting point brazing material 5 becomes brittle between tin and gold. There is a risk that the intermetallic compound is generated and the reliability of the connection of the semiconductor element 3 to the wiring layer 2 is significantly reduced. Therefore, the gold plating layer 9 has a thickness of 0.8 μm.
It is preferably set to m or less.
【0040】また一方、前記半導体素子3が搭載された
絶縁基体1は、その上面に蓋体10が樹脂、ガラス、ロ
ウ材等からなる封止材を介して接合され、この蓋体10
と絶縁基体1とによって半導体素子3を内部に気密に封
止するようになっている。On the other hand, the insulating base 1 on which the semiconductor element 3 is mounted is joined to the upper surface of the lid 10 via a sealing material made of resin, glass, brazing material or the like.
The semiconductor element 3 is hermetically sealed inside by the insulating base 1.
【0041】前記蓋体10は酸化アルミニウム質焼結体
やムライト質焼結体、窒化アルミニウム質焼結体等のセ
ラミックス材料、あるいは鉄−ニッケル−コバルト合金
や鉄−ニッケル合金等の金属材料から成り、例えば、酸
化アルミニウム質焼結体から成る場合には、酸化アルミ
ニウム、酸化珪素、酸化マグネシウム、酸化カルシウム
等の原料粉末を従来周知のプレス成形法を採用すること
によって椀状に成形するとともにこれを約1500℃の
温度で焼成することによって形成される。The lid 10 is made of a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, or a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. For example, in the case of an aluminum oxide sintered body, a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide or the like is formed into a bowl shape by adopting a conventionally known press forming method and It is formed by firing at a temperature of about 1500 ° C.
【0042】かくして上述の本発明の配線基板を適用し
た半導体素子収納用パッケージによれば、絶縁基体1上
面の搭載部表面に露出した配線層2に半導体素子3の電
極を半田等の低融点ロウ材から成る接続部材5を介して
電気的、機械的に接続し、しかる後、絶縁基体1の上面
に蓋体10を樹脂やガラス、ロウ材等から成る封止材を
介して接合させ、絶縁基体1と蓋体10とから成る容器
内部に半導体素子3を気密に収容することによって最終
製品としての半導体装置が完成する。Thus, according to the semiconductor element housing package to which the wiring board of the present invention is applied, the electrode of the semiconductor element 3 is soldered to the wiring layer 2 exposed on the surface of the mounting portion on the upper surface of the insulating substrate 1 to form a low melting point solder. Electrically and mechanically via a connecting member 5 made of a material, and thereafter, the lid 10 is joined to the upper surface of the insulating base 1 via a sealing material made of resin, glass, brazing material, etc. A semiconductor device as a final product is completed by hermetically accommodating the semiconductor element 3 inside a container composed of the base 1 and the lid 10.
【0043】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、本発明の配線基板
を、半導体素子、容量素子、抵抗器等の電子部品を搭載
する混成集積回路用の配線基板に適用してもよい。The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, the wiring board of the present invention can be used as a semiconductor element. It may be applied to a wiring board for a hybrid integrated circuit on which electronic parts such as a capacitor and a resistor are mounted.
【0044】[0044]
【発明の効果】本発明の配線基板によれば、少なくとも
電子部品の電極が低融点ロウ材を介して接続される配線
層の表面に、ホウ素の含有量が0.3重量%以上で銅−
ホウ素の結晶粒径が0.3μm以下と小さい銅−ホウ素
めっき層を被着させたことから配線層の表面に多数の凹
凸があったとしても、この凹部内に銅−ホウ素の結晶が
良好に入り込んで配線層と銅−ホウ素めっき層とが間に
空隙部を形成することなく強固に被着し、また銅−ホウ
素めっき層上に、各々の密着性が良好な銅めっき層と、
パラジウム、白金、ロジウム、ルテニウムの少なくとも
1種とリンとの合金層と、金めっき層とを順次被着させ
たことから配線層に銅めっき層および金めっき層を強固
に被着させることができるとともに前記銅めっき層によ
って配線層の電気抵抗を小さなものとなすことができ、
更に金めっき層によって配線層の酸化腐食を有効に防止
しつつ配線層に電子部品の電極を低融点ロウ材を介して
確実、強固に電気的接続することが可能となる。According to the wiring board of the present invention, at least the electrode of the electronic component is connected to the surface of the wiring layer through the low melting point brazing material, and the content of boron is 0.3% by weight or more.
Even if there are many irregularities on the surface of the wiring layer because the copper-boron plating layer having a small crystal grain size of boron of 0.3 μm or less is deposited, the copper-boron crystals are well formed in the depressions. The wiring layer and the copper-boron plated layer are firmly adhered without forming a void between them, and the copper-boron plated layer and the copper plated layer having good adhesion to each other,
Since the alloy layer of at least one of palladium, platinum, rhodium, and ruthenium and phosphorus and the gold plating layer are sequentially deposited, the wiring layer can be firmly deposited with the copper plating layer and the gold plating layer. Along with the copper plating layer can reduce the electrical resistance of the wiring layer,
Further, it becomes possible to securely and firmly electrically connect the electrode of the electronic component to the wiring layer through the low melting point brazing material while effectively preventing the oxidation corrosion of the wiring layer by the gold plating layer.
【0045】また同時に、前記銅めっき層と金めっき層
との間に形成したパラジウム、白金、ロジウム、ルテニ
ウムの少なくとも1種とリンとの合金層、特にリン成分
の作用により銅めっき層の銅の金めっき層表面への拡散
が極めて効果的に防止され、配線層に電子部品の電極を
低融点ロウ材を介して接合する際の熱等が作用したとし
ても金めっき層表面に銅の酸化物層が形成されることは
ほとんどなく、これによって配線層に対する低融点ロウ
材の接合性を良好なものに維持することができる。At the same time, an alloy layer of at least one of palladium, platinum, rhodium, and ruthenium formed between the copper plating layer and the gold plating layer and phosphorus, particularly the copper of the copper plating layer by the action of the phosphorus component. Diffusion to the surface of the gold plating layer is extremely effectively prevented, and even if heat etc. when joining the electrode of the electronic component to the wiring layer via the low melting point brazing material acts on the surface of the gold plating layer. A layer is rarely formed, which makes it possible to maintain good bondability of the low melting point brazing material to the wiring layer.
【図1】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment in which a wiring board of the present invention is applied to a semiconductor element housing package.
【図2】図1に示す配線基板の要部断面図である。FIG. 2 is a cross-sectional view of an essential part of the wiring board shown in FIG.
1・・・・絶縁基体
2・・・・配線層
3・・・・半導体素子
4・・・・配線基板
5・・・・接続部材
6・・・・銅−ホウ素めっき層
7・・・・銅めっき層
8・・・・パラジウム、白金、ロジウム、ルテニウムの
少なくとも1種とリンとの合金層
9・・・・金めっき層
10・・・蓋体1 ... Insulating substrate 2 ... Wiring layer 3 ... Semiconductor element 4 ... Wiring substrate 5 ... Connection member 6 ... Copper-boron plating layer 7 ... Copper plating layer 8 ...- Alloy layer of at least one of palladium, platinum, rhodium and ruthenium and phosphorus 9-Gold plating layer 10-lid
Claims (4)
を介して接続される配線層を被着形成して成る配線基板
であって、前記配線層のうち少なくとも電子部品の電極
が低融点ロウ材を介して接合される領域の表面に、ホウ
素の含有量が0.3重量%以上の銅−ホウ素めっき層
と、銅めっき層と、パラジウム、白金、ロジウム、ルテ
ニウムの少なくとも1種とリンとの合金層と、金めっき
層とを順次被着させたことを特徴とする配線基板。1. A wiring board comprising an insulating base and a wiring layer formed by depositing a wiring layer on which electrodes of an electronic component are connected via a low melting point brazing material, wherein at least an electrode of the electronic component is low in the wiring layer. A copper-boron plating layer having a boron content of 0.3% by weight or more, a copper plating layer, and at least one of palladium, platinum, rhodium, and ruthenium on the surface of the region to be joined via the melting point brazing material. A wiring board, wherein an alloy layer with phosphorus and a gold plating layer are sequentially deposited.
μm以上であることを特徴とする請求項1に記載の配線
基板。2. The thickness of the copper-boron plating layer is 0.03.
The wiring board according to claim 1, wherein the wiring board has a thickness of at least μm.
晶粒の平均粒径が0.02μm以下であることを特徴と
する請求項1に記載の配線基板。3. The wiring board according to claim 1, wherein the average grain size of the crystal grains of copper forming the copper-boron plating layer is 0.02 μm or less.
ウムの少なくとも1種とリンとの合金層のリン含有量が
0.2重量%〜2重量%の範囲であることを特徴とする
請求項1に記載の配線基板。4. The phosphorus content of the alloy layer of phosphorus with at least one of palladium, platinum, rhodium and ruthenium is in the range of 0.2% by weight to 2% by weight. The wiring board described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001310161A JP3898482B2 (en) | 2001-10-05 | 2001-10-05 | Wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001310161A JP3898482B2 (en) | 2001-10-05 | 2001-10-05 | Wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2003115655A true JP2003115655A (en) | 2003-04-18 |
JP3898482B2 JP3898482B2 (en) | 2007-03-28 |
Family
ID=19129184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001310161A Expired - Fee Related JP3898482B2 (en) | 2001-10-05 | 2001-10-05 | Wiring board |
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Country | Link |
---|---|
JP (1) | JP3898482B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006339219A (en) * | 2005-05-31 | 2006-12-14 | Toppan Printing Co Ltd | Wiring board |
CN111226315A (en) * | 2017-10-27 | 2020-06-02 | 三菱综合材料株式会社 | Joined body, insulated circuit board with heat sink, and heat sink |
-
2001
- 2001-10-05 JP JP2001310161A patent/JP3898482B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006339219A (en) * | 2005-05-31 | 2006-12-14 | Toppan Printing Co Ltd | Wiring board |
JP4639964B2 (en) * | 2005-05-31 | 2011-02-23 | 凸版印刷株式会社 | Wiring board manufacturing method |
CN111226315A (en) * | 2017-10-27 | 2020-06-02 | 三菱综合材料株式会社 | Joined body, insulated circuit board with heat sink, and heat sink |
CN111226315B (en) * | 2017-10-27 | 2023-06-06 | 三菱综合材料株式会社 | Joint body, insulating circuit substrate with radiator and radiator |
Also Published As
Publication number | Publication date |
---|---|
JP3898482B2 (en) | 2007-03-28 |
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