JP2002076595A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2002076595A
JP2002076595A JP2000253701A JP2000253701A JP2002076595A JP 2002076595 A JP2002076595 A JP 2002076595A JP 2000253701 A JP2000253701 A JP 2000253701A JP 2000253701 A JP2000253701 A JP 2000253701A JP 2002076595 A JP2002076595 A JP 2002076595A
Authority
JP
Japan
Prior art keywords
plating layer
boron
nickel
layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000253701A
Other languages
Japanese (ja)
Inventor
Hiroshi Tsukamoto
弘志 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000253701A priority Critical patent/JP2002076595A/en
Publication of JP2002076595A publication Critical patent/JP2002076595A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Landscapes

  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a spot formed on a gold plating layer applied to a wiring layer which damages the appearance. SOLUTION: The wiring board has a wiring layer 2 connected with the electrode of an electronic component 3 through solder 5 wherein a nickel-boron plating layer 6, a palladium-boron plating layer 7 and a gold plating layer 8 are formed sequentially on the surface of a region of the wiring layer 2 being connected at least with the electronic component 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子や容量
素子、抵抗器等の電子部品が搭載される配線基板に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which electronic components such as a semiconductor element, a capacitor, and a resistor are mounted.

【0002】[0002]

【従来の技術】従来、半導体素子や容量素子、抵抗器等
の電子部品が搭載される配線基板は、一般に、酸化アル
ミニウム質焼結体から成る絶縁基体と、該絶縁基体の上
面から下面かけて形成されたにタングステン、モリブデ
ン等の高融点金属材料から成る複数個の配線層とから構
成されており、絶縁基体の上面に半導体素子や容量素
子、抵抗器等の電子部品を搭載するとともに該電子部品
の各電極を配線層に半田を介して電気的に接続するよう
になっている。
2. Description of the Related Art Conventionally, a wiring board on which electronic components such as a semiconductor element, a capacitor element, and a resistor are mounted generally includes an insulating base made of an aluminum oxide sintered body and an upper surface to a lower surface of the insulating base. And a plurality of wiring layers made of a refractory metal material such as tungsten or molybdenum. The electronic component such as a semiconductor element, a capacitor, and a resistor is mounted on the upper surface of the insulating base, Each electrode of the component is electrically connected to a wiring layer via solder.

【0003】かかる配線基板は、配線層の絶縁基体下面
に導出されている部位を外部電気回路基板の配線導体に
半田等を介し接続することによって外部電気回路基板上
に実装され、同時に配線基板に搭載されている電子部品
の各電極が所定の外部電気回路に電気的に接続されるこ
ととなる。
[0003] Such a wiring board is mounted on the external electric circuit board by connecting a portion of the wiring layer extending to the lower surface of the insulating base to a wiring conductor of the external electric circuit board via solder or the like, and at the same time, is mounted on the wiring board. Each electrode of the mounted electronic component is electrically connected to a predetermined external electric circuit.

【0004】また、上述の配線基板は配線層の少なくと
も電子部品が半田を介して接続される領域にニッケル−
リン合金またはニッケル−ホウ素合金から成るニッケル
めっき層と金めっき層が順次被着されており、該ニッケ
ルめっき層によってタングステン等の高融点金属材料か
ら成る配線層に対する半田の接合を良好とし、金めっき
層によってニッケルめっき層表面にニッケルの酸化物が
形成されて半田接合性等が劣化するのを防止している。
The above-mentioned wiring board has a nickel layer at least in an area of the wiring layer where electronic components are connected via solder.
A nickel plating layer made of a phosphorus alloy or a nickel-boron alloy and a gold plating layer are sequentially applied, and the nickel plating layer improves the bonding of solder to a wiring layer made of a high melting point metal material such as tungsten, and The layer prevents the formation of a nickel oxide on the surface of the nickel plating layer to prevent the deterioration of the solder bonding property and the like.

【0005】なお、前記ニッケルめっき層の表面に無電
解法により金めっき層を被着させる場合、ニッケルが金
の析出被着に対して触媒不活性で、自己触媒法による金
めっき層の被着が不可であることから、通常、置換めっ
き法、つまり、ニッケルを酸化溶出させるとともに、金
を還元析出させる方法が用いられている。
When a gold plating layer is deposited on the surface of the nickel plating layer by an electroless method, nickel is catalytically inactive against deposition and deposition of gold, and deposition of the gold plating layer by an autocatalytic method. Therefore, a displacement plating method, that is, a method in which nickel is oxidized and eluted and gold is reduced and precipitated is usually used.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、この従
来の配線基板において、配線層上の電子部品が半田を介
して接続される領域にニッケル−リン合金からなるニッ
ケルめっき層を被着させた場合、ニッケル−リン合金の
リン成分が不活性であること及びタングステンやモリブ
デン等の高融点金属材料から成る配線層の表面が粗面で
あること等から配線層の表面全面にニッケル−リン合金
から成るニッケルめっき層を均一に被着させることがで
きず、多数のピンホール(小穴)やボイド(小空隙)を
有したものとなり、その結果、ピンホールやボイド内に
めっき液が残留し易く、ピンホールやボイド内にめっき
液が残留しているとこれが電子部品を配線層に半田を介
して接続させる際の熱によって金めっき層上にしみ出
し、斑点状のしみを形成して外観不良を生じるという欠
点を有する。
However, in this conventional wiring board, when a nickel plating layer made of a nickel-phosphorus alloy is applied to a region on the wiring layer where electronic components are connected via solder, Since the phosphorus component of the nickel-phosphorus alloy is inactive and the surface of the wiring layer made of a refractory metal material such as tungsten or molybdenum is rough, the nickel made of the nickel-phosphorus alloy is formed on the entire surface of the wiring layer. The plating layer cannot be uniformly deposited, and has many pinholes (small holes) and voids (small voids). As a result, the plating solution easily remains in the pinholes and voids, and If the plating solution remains in the voids, it will seep out onto the gold plating layer due to the heat generated when connecting the electronic component to the wiring layer via solder, causing spot-like spots. Has the disadvantage that the form results in a poor appearance with.

【0007】また配線層上にニッケル−ホウ素合金から
成るニッケルめっき層を被着させた場合、ニッケル−ホ
ウ素合金が酸化し易く、耐食性に劣ることから、置換め
っき法により金めっき層を被着させる際、金の還元析出
に必要な量以上のニッケルが酸化して酸化層を形成して
しまい、金めっき層をニッケルめっき層の表面に強固に
被着させることができなくなってしまうという欠点を有
していた。
When a nickel plating layer made of a nickel-boron alloy is deposited on the wiring layer, the nickel-boron alloy is easily oxidized and has poor corrosion resistance. Therefore, a gold plating layer is deposited by a displacement plating method. In this case, there is a disadvantage that nickel in an amount more than necessary for the reductive precipitation of gold is oxidized to form an oxide layer, and the gold plating layer cannot be firmly adhered to the surface of the nickel plating layer. Was.

【0008】本発明は上記欠点に鑑み案出されたもので
その目的は、斑点状のしみの発生による外観不良や金め
っき層とニッケルめっき層との間に剥離やフクレが発生
するのを有効に防止し、配線層に電子部品を半田を介し
て強固に取着することができる配線基板を提供すること
にある。
The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to effectively prevent poor appearance due to occurrence of spot-like spots and occurrence of peeling or blistering between a gold plating layer and a nickel plating layer. Another object of the present invention is to provide a wiring board which can securely attach an electronic component to a wiring layer via solder.

【0009】[0009]

【課題を解決するための手段】本発明は、電子部品の電
極が半田を介して接続される配線層を有する配線基板で
あって、前記配線層のうち少なくとも電子部品の電極が
半田を介して接続される領域の表面に、ニッケル−ホウ
素めっき層、パラジウム−ホウ素めっき層、金めっき層
を順次被着させたことを特徴とするものである。
SUMMARY OF THE INVENTION The present invention provides a wiring board having a wiring layer to which electrodes of an electronic component are connected via solder, wherein at least the electrode of the electronic component of the wiring layer is connected via solder. A nickel-boron plating layer, a palladium-boron plating layer, and a gold plating layer are sequentially deposited on the surface of a region to be connected.

【0010】また本発明は、前記パラジウム−ホウ素め
っき層の厚さが0.05μm〜2μmであることを特徴
とするものである。
In the present invention, the thickness of the palladium-boron plating layer is 0.05 μm to 2 μm.

【0011】更に本発明は、前記ニッケル−ホウ素めっ
き層のホウ素含有量が0.05重量%〜3重量%である
ことを特徴とするものである。
Further, the present invention is characterized in that the nickel-boron plating layer has a boron content of 0.05% by weight to 3% by weight.

【0012】また更に本発明は、前記パラジウム−ホウ
素めっき層のホウ素含有量が2重量%以下であることを
特徴とするものである。
Further, the present invention is characterized in that the palladium-boron plating layer has a boron content of 2% by weight or less.

【0013】本発明の配線基板によれば、配線層のうち
少なくとも電子部品の電極が半田を介して接続される領
域の表面に、ニッケル−ホウ素めっき層、パラジウム−
ホウ素めっき層、金めっき層を順次被着させ、配線層の
表面に直接、触媒活性の強いホウ素を含有するニッケル
−ホウ素めっき層を被着させたことから配線層にニッケ
ル−ホウ素めっき層をピンホールやボイド等を生じるこ
となく表面を極めて平滑として均一厚みに、かつ強固に
被着させることができ、またニッケル−ホウ素めっき層
上に、該ニッケル−ホウ素めっき層及び金めっき層のい
ずれとも密着性が良好であるパラジウム−ホウ素めっき
層を被着させたことからニッケル−ホウ素めっき層上に
金めっき層を強固に被着させることができ、さらにパラ
ジウム−ホウ素めっき層上に耐蝕性に優れ、かつ半田と
の濡れ性に優れる金めっき層を被着させたことからニッ
ケル−ホウ素めっき層及びパラジウム−ホウ素めっき層
が酸化腐蝕するのを有効に防止することができるととも
に半田を強固に接合させることができ、その結果、配線
基板の配線層に斑点状のしみやフクレが発生するのを有
効に防止することができるとともに配線層に電子部品の
電極を半田を介して極めて強固に接続することができ
る。
According to the wiring board of the present invention, the nickel-boron plating layer and the palladium plating layer are formed on at least the surface of the region of the wiring layer where the electrodes of the electronic components are connected via solder.
A boron-plated layer and a gold-plated layer were sequentially deposited, and a nickel-boron-plated layer containing boron having strong catalytic activity was directly deposited on the surface of the wiring layer. The surface is extremely smooth without any holes or voids, and can be adhered to the nickel-boron plating layer with both the nickel-boron plating layer and the gold plating layer. Since the palladium-boron plating layer having good properties is adhered, the gold plating layer can be firmly adhered on the nickel-boron plating layer, and further, the palladium-boron plating layer has excellent corrosion resistance, The nickel-boron plating layer and the palladium-boron plating layer are oxidized and corroded because the gold plating layer having excellent wettability with solder is applied. It is possible to effectively prevent the solder and to firmly join the solder, and as a result, it is possible to effectively prevent spot-like spots and blisters from being generated on the wiring layer of the wiring board, and to prevent the wiring layer from being damaged. The electrodes of the component can be connected very firmly via solder.

【0014】 〔発明の詳細な説明〕次に、本発明を添付図面に基づき
詳細に説明する。図1は、本発明の配線基板を半導体素
子を収容する半導体素子収納用パッケージに適用した場
合の一実施例を示し、1は絶縁基体、2は配線層であ
る。この絶縁基体1と配線層2とで半導体素子3を搭載
するための配線基板4が形成される。
[Detailed Description of the Invention] Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment in which the wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element, wherein 1 is an insulating base and 2 is a wiring layer. The insulating substrate 1 and the wiring layer 2 form a wiring board 4 on which the semiconductor element 3 is mounted.

【0015】前記絶縁基体1は、酸化アルミニウム質焼
結体、窒化アルミニウム質焼結体、ムライト質焼結体、
炭化珪素質焼結体、ガラスセラミック焼結体等の電気絶
縁材料から成り、その上面に半導体素子3を搭載する搭
載部を有し、該搭載部表面に露出した配線層2に半導体
素子3の電極が半田ボール5を介して接続される。
The insulating substrate 1 is made of an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body, and has a mounting portion for mounting the semiconductor element 3 on the upper surface thereof. The electrodes are connected via solder balls 5.

【0016】前記絶縁基体1は、例えば、酸化アルミニ
ウム質焼結体から成る場合には、酸化アルミニウム、酸
化珪素、酸化カルシウム、酸化マグネシウム等の原料粉
末に適当な有機バインダー、溶剤を添加混合して泥漿状
のセラミックスラリーとなすとともに該セラミックスラ
リーを従来周知のドクターブレード法やカレンダーロー
ル法等のシート成形技術を採用しシート状となすことに
よってセラミックグリーンシート(セラミック生シー
ト)を得、しかる後、前記セラミックグリーンシートを
切断加工や打ち抜き加工により適当な形状とするととも
にこれを複数枚積層し、最後に前記積層されたセラミッ
クグリーンシートを還元雰囲気中、約1600℃の温度
で焼成することによって製作される。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder and a solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. A ceramic green sheet (green ceramic sheet) is obtained by forming the slurry into a slurry and forming the ceramic slurry into a sheet by employing a sheet forming technique such as a doctor blade method or a calender roll method which is well known in the art. The ceramic green sheet is manufactured by cutting and punching into an appropriate shape, laminating a plurality of the sheets, and finally firing the laminated ceramic green sheet at a temperature of about 1600 ° C. in a reducing atmosphere. You.

【0017】また前記絶縁基体1は、その上面の搭載部
から下面にかけて多数の配線層2が被着形成されてお
り、該配線層2の搭載部に露出した部位には半導体素子
3の各電極が半田ボール5を介して電気的に接続され、
また絶縁基体1の下面に導出された部位には外部電気回
路基板の配線導体が半田等を介して電気的に接続され
る。
The insulating substrate 1 has a large number of wiring layers 2 formed thereon from the mounting portion on the upper surface to the lower surface thereof. Each electrode of the semiconductor element 3 is exposed at the portion exposed on the mounting portion of the wiring layer 2. Are electrically connected via the solder balls 5,
Further, a wiring conductor of an external electric circuit board is electrically connected to a portion led out to the lower surface of the insulating base 1 via solder or the like.

【0018】前記配線層2は、搭載される半導体素子3
の各電極を外部電気回路に接続する作用をなし、例え
ば、タングステン、モリブデン、マンガン等の高融点金
属粉末から成り、タングステン等の高融点金属粉末に適
当な有機バインダーや溶剤を添加混合して得た金属ペー
ストを絶縁基体1となるセラミックグリーンシートに予
め従来周知のスクリーン印刷法により所定パターンに印
刷塗布しておくことによって絶縁基体1の搭載部から下
面にかけて被着される。
The wiring layer 2 has a semiconductor element 3 mounted thereon.
A function of connecting each electrode to an external electric circuit, for example, made of a refractory metal powder such as tungsten, molybdenum, and manganese, and obtained by adding a suitable organic binder or solvent to the refractory metal powder such as tungsten and mixing. The metal paste is applied in a predetermined pattern to a ceramic green sheet serving as the insulating base 1 in advance by a conventionally known screen printing method, so that the paste is applied from the mounting portion of the insulating base 1 to the lower surface.

【0019】前記配線層2は図2に示すように、少なく
とも半導体素子3の電極が半田ボール5を介して接続さ
れる領域に、ニッケル−ホウ素めっき層6、パラジウム
−ホウ素めっき層7及び金めっき層8が順次被着されて
いる。
As shown in FIG. 2, the wiring layer 2 has a nickel-boron plating layer 6, a palladium-boron plating layer 7, and a gold plating at least in a region where electrodes of the semiconductor element 3 are connected via solder balls 5. Layers 8 are applied sequentially.

【0020】前記ニッケル−ホウ素めっき層6は、配線
層2にパラジウム−ホウ素めっき層7および金めっき層
8を密着性良く被着させる下地金属層として作用する。
The nickel-boron plating layer 6 functions as a base metal layer that adheres the palladium-boron plating layer 7 and the gold plating layer 8 to the wiring layer 2 with good adhesion.

【0021】前記ニッケル−ホウ素めっき層6は、硫酸
ニッケル等のニッケル化合物とホウ素系還元剤、例えば
水素化ホウ素ナトリウムやジメチルアミンボラン等を含
む無電解ニッケルめっき浴を用いた無電解めっき法によ
り配線層2の表面に所定厚みに被着される。この場合、
前記ニッケル−ホウ素めっき層6はその内部に触媒活性
の強いホウ素を含有することから配線層2の表面が粗面
であるとしてもニッケル−ホウ素めっき層6にピンホー
ルやボイド等が形成されることはなく、同時に表面を極
めて平滑として均一厚みに、かつ強固に被着させること
ができる。
The nickel-boron plating layer 6 is formed by electroless plating using an electroless nickel plating bath containing a nickel compound such as nickel sulfate and a boron-based reducing agent such as sodium borohydride and dimethylamine borane. A predetermined thickness is applied to the surface of the layer 2. in this case,
Since the nickel-boron plating layer 6 contains boron having strong catalytic activity therein, pinholes and voids are formed in the nickel-boron plating layer 6 even if the surface of the wiring layer 2 is rough. However, at the same time, the surface can be made extremely smooth and a uniform thickness can be firmly applied.

【0022】なお、前記ニッケル−ホウ素めっき層6
は、ホウ素の含有量が0.05重量%未満の少ないもの
となるとニッケル−ホウ素めっき層6の耐蝕性が劣化し
て酸化し易くなる傾向にあり、また3重量%を超えると
電気抵抗が上昇し、配線基板としての特性が劣化してし
まう傾向にある。従って、前記ニッケル−ホウ素めっき
層6は、そのホウ素の含有量を0.05重量%〜3重量
%の範囲としておくことが好ましい。
The nickel-boron plating layer 6
When the content of boron is less than 0.05% by weight, the corrosion resistance of the nickel-boron plating layer 6 tends to deteriorate and it tends to be oxidized, and when it exceeds 3% by weight, the electric resistance increases. However, the characteristics as a wiring substrate tend to deteriorate. Therefore, the nickel-boron plating layer 6 preferably has a boron content in the range of 0.05% by weight to 3% by weight.

【0023】また前記ニッケル−ホウ素めっき層6は、
その厚さが1μm未満と薄いものになるとニッケル−ホ
ウ素めっき層6を粗面な配線層2に表面を極めて平滑と
して均一厚みに被着させるのが困難となってしまう傾向
にあり、また8μmを超えると内部応力が大きくなって
配線層2にニッケル−ホウ素めっき層6を強固に被着さ
せることが困難となってしまう。従って、前記ニッケル
−ホウ素めっき層6は、その厚さを1μm〜8μmの範
囲としておくことが好ましい。
The nickel-boron plating layer 6 is
If the thickness is as thin as less than 1 μm, it becomes difficult to apply the nickel-boron plating layer 6 to the rough wiring layer 2 with a very smooth surface and to apply a uniform thickness. If it exceeds, the internal stress increases, and it becomes difficult to firmly apply the nickel-boron plating layer 6 to the wiring layer 2. Therefore, it is preferable that the nickel-boron plating layer 6 has a thickness in the range of 1 μm to 8 μm.

【0024】さらに前記ニッケル−ホウ素めっき層6上
には、パラジウム−ホウ素めっき層7が所定厚みに被着
されており、該パラジウム−ホウ素めっき層7はニッケ
ル−ホウ素めっき層6に金めっき層8を強固に被着接合
させる作用をなす。
Further, on the nickel-boron plating layer 6, a palladium-boron plating layer 7 is adhered to a predetermined thickness, and the palladium-boron plating layer 7 is formed on the nickel-boron plating layer 6 by a gold plating layer 8. Has a function to firmly adhere and bond.

【0025】前記パラジウム−ホウ素めっき層7は、塩
化パラジウム等のパラジウム化合物とホウ素系還元剤、
例えばジメチルアミンボラン、トリメチルアミンボラン
等を含む無電解パラジウムめっき浴を用いた無電解めっ
き法によりニッケル−ホウ素めっき層6上に被着され
る。この場合、下地のニッケル−ホウ素めっき層6は表
面が極めて平滑であること、パラジウム−ホウ素めっき
層7はめっき液中のパラジウム化合物が還元剤で還元析
出される自己触媒反応によりニッケル−ホウ素めっき層
6上に被着され、ニッケル−ホウ素めっき層7を酸化さ
せることがないことから、パラジウム−ホウ素めっき層
7をニッケル−ホウ素めっき層6表面にピンホールやボ
イド等を形成することなく均一厚みに、かつ強固に被着
させることができる。
The palladium-boron plating layer 7 comprises a palladium compound such as palladium chloride and a boron-based reducing agent,
For example, it is deposited on the nickel-boron plating layer 6 by an electroless plating method using an electroless palladium plating bath containing dimethylamine borane, trimethylamine borane, or the like. In this case, the underlying nickel-boron plating layer 6 has an extremely smooth surface, and the palladium-boron plating layer 7 has a nickel-boron plating layer formed by an autocatalytic reaction in which a palladium compound in the plating solution is reduced and precipitated with a reducing agent. Since the nickel-boron plating layer 7 is not oxidized on the nickel-boron plating layer 6, the palladium-boron plating layer 7 has a uniform thickness without forming pinholes or voids on the surface of the nickel-boron plating layer 6. , And can be firmly adhered.

【0026】なお、前記パラジウム−ホウ素めっき層7
は、ホウ素の含有率が2重量%を超えると、金との密着
の悪いホウ素成分が増大して後述する金めっき層の密着
性が劣化する傾向にある。従って、前記パラジウム−ホ
ウ素めっき層7は、ホウ素の含有率2重量%以下の範囲
としておくことが好ましい。
The palladium-boron plating layer 7
When the boron content exceeds 2% by weight, the amount of boron component having poor adhesion to gold increases, and the adhesion of a gold plating layer described later tends to deteriorate. Therefore, it is preferable that the palladium-boron plating layer 7 has a boron content of 2% by weight or less.

【0027】また前記パラジウム−ホウ素めっき層7
は、その厚みが0.05μm未満と薄いものとなった場
合、ニッケル−ホウ素めっき層6を完全に被覆すること
ができず、金めっき層8の被着強度が弱くなってしまう
傾向にあり、また2μmを超えると内部応力が大きくな
ってニッケル−ホウ素めっき層6への被着強度が低いも
のとなってしまう傾向がある。従って、前記パラジウム
−リンめっき層7は、その厚さを0.05μm〜2μm
の範囲としておくことが好ましい。
The palladium-boron plating layer 7
When the thickness is as thin as less than 0.05 μm, the nickel-boron plating layer 6 cannot be completely covered, and the adhesion strength of the gold plating layer 8 tends to be weak, If it exceeds 2 μm, the internal stress tends to increase, and the adhesion strength to the nickel-boron plating layer 6 tends to be low. Therefore, the palladium-phosphorus plating layer 7 has a thickness of 0.05 μm to 2 μm.
Is preferably set in the range.

【0028】更に前記パラジウム−ホウ素めっき層7の
表面には金めっき層8が所定厚みに被着されており、該
金めっき層8はニッケル−ホウ素めっき層6及びパラジ
ウム−ホウ素めっき層7が酸化腐蝕するのを有効に防止
することができるとともに半田を配線層2に強固に接合
させる作用をなす。
Further, on the surface of the palladium-boron plating layer 7, a gold plating layer 8 is applied to a predetermined thickness, and the gold plating layer 8 is formed by oxidizing the nickel-boron plating layer 6 and the palladium-boron plating layer 7. Corrosion can be effectively prevented, and has the effect of firmly joining the solder to the wiring layer 2.

【0029】前記金めっき層8は、例えば、従来周知の
シアン化金カリウム等の金化合物とエチレンジアミン四
酢酸(ナトリウム塩)等の錯化剤とを含有する置換型の
無電解金めっき液を用いる無電解めっき法によりパラジ
ウム−リンめっき層7表面に形成される。
For the gold plating layer 8, for example, a substitution type electroless gold plating solution containing a conventionally known gold compound such as potassium potassium cyanide and a complexing agent such as ethylenediaminetetraacetic acid (sodium salt) is used. It is formed on the surface of the palladium-phosphorous plating layer 7 by an electroless plating method.

【0030】なお、この場合、パラジウム−ホウ素めっ
き層7が耐食性に優れることから、金を還元させるに必
要な量以上にパラジウム−ホウ素めっき層7が酸化して
しまうことはなく、金めっき層8をパラジウム−ホウ素
めっき層7上に強固に被着形成させることができる。
In this case, since the palladium-boron plating layer 7 has excellent corrosion resistance, the palladium-boron plating layer 7 is not oxidized more than the amount necessary for reducing gold, and the gold plating layer 8 is not oxidized. Can be firmly formed on the palladium-boron plating layer 7.

【0031】前記金めっき層8は、その厚みが0.05
μm未満の薄いものとなると、パラジウム−ホウ素めっ
き層7やニッケル−ホウ素めっき層6の酸化を防ぐこと
が困難となり、また0.8μmを超えて厚くすると、半
導体素子3の電極を配線層2に接続する半田ボール5と
の間で金−錫等の脆い金属間化合物が形成され、接続部
の長期信頼性を低いものとしてしまうおそれがある。従
って、前記金めっき層8は、その厚さを0.05μm乃
至0.3μmの範囲としておくことが好ましい。
The gold plating layer 8 has a thickness of 0.05
When the thickness is less than μm, it is difficult to prevent oxidation of the palladium-boron plating layer 7 and the nickel-boron plating layer 6, and when the thickness exceeds 0.8 μm, the electrodes of the semiconductor element 3 are attached to the wiring layer 2. A brittle intermetallic compound such as gold-tin may be formed between the solder ball 5 and the solder ball 5 to be connected, and the long-term reliability of the connection may be reduced. Therefore, it is preferable that the thickness of the gold plating layer 8 be in the range of 0.05 μm to 0.3 μm.

【0032】また一方、前記半導体素子3が搭載された
絶縁基体1は、その上面に蓋体9が樹脂、ガラス、ロウ
材等から成る封止材を介して接合され、この蓋体9と絶
縁基体1とによって半導体素子3を気密に封止するよう
になっている。
On the other hand, the insulating substrate 1 on which the semiconductor element 3 is mounted has a lid 9 joined to the upper surface thereof via a sealing material made of resin, glass, brazing material or the like. The semiconductor element 3 is hermetically sealed by the base 1.

【0033】前記蓋体9は酸化アルミニウム質焼結体や
ムライト質焼結体、窒化アルミニウム質焼結体等のセラ
ミックス材料、あるいは鉄−ニッケル−コバルト合金や
鉄−ニッケル合金等の金属材料から成り、例えば、酸化
アルミニウム質焼結体から成る場合には、酸化アルミニ
ウム、酸化珪素、酸化マグネシウム,酸化カルシウム等
の原料粉末を従来周知のプレス成形法を採用することに
よって椀状に成形するとともにこれを約1500℃の温
度で焼成することによって形成される。
The lid 9 is made of a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, or an aluminum nitride sintered body, or a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. For example, in the case of a sintered body made of aluminum oxide, a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide is formed into a bowl shape by employing a conventionally known press molding method, and then formed into a bowl shape. It is formed by firing at a temperature of about 1500 ° C.

【0034】かくして本発明の配線基板4によれば、絶
縁基体1上面の搭載部表面に露出した配線層2に半導体
素子3の電極を半田ボール5を介して電気的、機械的に
接続し、しかる後、絶縁基体1の上面に金属やセラミッ
クスから成る蓋体9をガラスや樹脂、ロウ材等の封止材
を介して接合させ、絶縁基体1と蓋体9とから成る容器
内部に半導体素子3を気密に収容することによって製品
としての半導体装置が完成する。
Thus, according to the wiring board 4 of the present invention, the electrodes of the semiconductor element 3 are electrically and mechanically connected to the wiring layers 2 exposed on the surface of the mounting portion on the upper surface of the insulating base 1 via the solder balls 5. Thereafter, a lid 9 made of metal or ceramics is bonded to the upper surface of the insulating base 1 via a sealing material such as glass, resin, brazing material or the like, and a semiconductor element is placed inside the container formed of the insulating base 1 and the lid 9. The semiconductor device as a product is completed by housing 3 in an airtight manner.

【0035】なお、本発明の配線基板は上述の実施例に
限定されるものではなく、本発明の要旨を逸脱しない範
囲であれば種々の変更は可能であり、例えば、上述の実
施例では本発明の配線基板を半導体素子を収容する半導
体素子収納用パッケージに適用したが、混成集積回路基
板等の他の用途に適用してもよい。
It should be noted that the wiring board of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Although the wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element, it may be applied to other uses such as a hybrid integrated circuit board.

【0036】また本発明における「半田」とは、一般的
な錫(Sn)と鉛(Pb)の合金に限らず錫(Sn)を
成分とする低融点の合金、例えば、「鉛フリー半田」と
称される錫−銀系等の合金をも含むものである。
The “solder” in the present invention is not limited to a general alloy of tin (Sn) and lead (Pb) but is a low-melting alloy containing tin (Sn) as a component, for example, “lead-free solder” And tin-silver based alloys.

【0037】[0037]

【発明の効果】本発明の配線基板によれば、配線層のう
ち少なくとも電子部品の電極が半田を介して接続される
領域の表面に、ニッケル−ホウ素めっき層、パラジウム
−ホウ素めっき層、金めっき層を順次被着させ、配線層
の表面に直接、触媒活性の強いホウ素を含有するニッケ
ル−ホウ素めっき層を被着させたことから配線層にニッ
ケル−ホウ素めっき層をピンホールやボイド等を生じる
ことなく表面を極めて平滑として均一厚みに、かつ強固
に被着させることができ、またニッケル−ホウ素めっき
層上に、該ニッケル−ホウ素めっき層及び金めっき層の
いずれとも密着性が良好であるパラジウム−ホウ素めっ
き層を被着させたことからニッケル−ホウ素めっき層上
に金めっき層を強固に被着させることができ、さらにパ
ラジウム−ホウ素めっき層上に耐蝕性に優れ、かつ半田
との濡れ性に優れる金めっき層を被着させたことからニ
ッケル−ホウ素めっき層及びパラジウム−ホウ素めっき
層が酸化腐蝕するのを有効に防止することができるとと
もに半田を強固に接合させることができ、その結果、配
線基板の配線層に斑点状のしみやフクレが発生するのを
有効に防止することができるとともに配線層に電子部品
の電極を半田を介して極めて強固に接続することができ
る。
According to the wiring board of the present invention, the nickel-boron plating layer, the palladium-boron plating layer, and the gold plating are formed on at least the surface of the region of the wiring layer where the electrodes of the electronic components are connected via solder. The layers are sequentially deposited, and the nickel-boron plating layer containing boron having a strong catalytic activity is directly deposited on the surface of the wiring layer, so that the nickel-boron plating layer causes pinholes and voids in the wiring layer. Palladium which can be adhered to a nickel-boron plating layer with good adhesion to both the nickel-boron plating layer and the gold plating layer. -Since the boron plating layer is deposited, the gold plating layer can be firmly deposited on the nickel-boron plating layer. The gold-plated layer, which has excellent corrosion resistance and solder wettability, is deposited on the plating layer, so that the nickel-boron plating layer and the palladium-boron plating layer are effectively prevented from being oxidized and corroded. And the solder can be firmly joined. As a result, spots and blisters can be effectively prevented from being generated on the wiring layer of the wiring board, and the electrodes of the electronic component can be soldered to the wiring layer. The connection can be very firmly connected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の一実施例を示す断面図であ
る。
FIG. 1 is a sectional view showing one embodiment of a wiring board of the present invention.

【図2】図1に示す配線基板の要部拡大図である。FIG. 2 is an enlarged view of a main part of the wiring board shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 2・・・・配線層 3・・・・半導体素子 4・・・・配線基板 5・・・・半田バンプ 6・・・・ニッケル−ホウ素めっき層 7・・・・パラジウム−ホウ素めっき層 8・・・・金めっき層 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Wiring layer 3 ... Semiconductor element 4 ... Wiring board 5 ... Solder bump 6 ... Nickel-boron plating layer 7 ... Palladium-boron plating layer 8 Gold plating layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/12 P ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 P

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】電子部品の電極が半田を介して接続される
配線層を有する配線基板であって、前記配線層のうち少
なくとも電子部品の電極が半田を介して接続される領域
の表面に、ニッケル−ホウ素めっき層、パラジウム−ホ
ウ素めっき層、金めっき層を順次被着させたことを特徴
とする配線基板。
1. A wiring board having a wiring layer to which electrodes of an electronic component are connected via solder, wherein at least a surface of a region of the wiring layer where electrodes of the electronic component are connected via solder, A wiring board comprising a nickel-boron plating layer, a palladium-boron plating layer, and a gold plating layer sequentially deposited thereon.
【請求項2】前記パラジウム−ホウ素めっき層の厚さが
0.05μm〜2μmであることを特徴とする請求項1
に記載の配線基板。
2. The palladium-boron plating layer has a thickness of 0.05 μm to 2 μm.
The wiring board according to claim 1.
【請求項3】前記ニッケル−ホウ素めっき層のホウ素含
有量が0.05重量%〜3重量%であることを特徴とす
る請求項1に記載の配線基板。
3. The wiring board according to claim 1, wherein the nickel-boron plating layer has a boron content of 0.05% by weight to 3% by weight.
【請求項4】前記パラジウム−ホウ素めっき層のホウ素
含有量が2重量%以下であることを特徴とする請求項1
に記載の配線基板。
4. The palladium-boron plating layer has a boron content of 2% by weight or less.
The wiring board according to claim 1.
JP2000253701A 2000-08-24 2000-08-24 Wiring board Pending JP2002076595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000253701A JP2002076595A (en) 2000-08-24 2000-08-24 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000253701A JP2002076595A (en) 2000-08-24 2000-08-24 Wiring board

Publications (1)

Publication Number Publication Date
JP2002076595A true JP2002076595A (en) 2002-03-15

Family

ID=18742753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000253701A Pending JP2002076595A (en) 2000-08-24 2000-08-24 Wiring board

Country Status (1)

Country Link
JP (1) JP2002076595A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10287994A (en) * 1997-04-14 1998-10-27 World Metal:Kk Plating structure of bonding part
JP2000129454A (en) * 1998-10-21 2000-05-09 Hitachi Chem Co Ltd Electroless palladium plating solution

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10287994A (en) * 1997-04-14 1998-10-27 World Metal:Kk Plating structure of bonding part
JP2000129454A (en) * 1998-10-21 2000-05-09 Hitachi Chem Co Ltd Electroless palladium plating solution

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