JP2001339015A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solver the problem that peeling-off occurs between a wiring layer and a copper plating layer or swelling is produced in the copper plating layer. SOLUTION: This wiring board is formed by adhering to an insulation substrate 1 a wiring layer 2 which is connected with an electrode of an electronic part 3 by means of a connecting member 5 made of low-melting-point brazing material. A copper-phosphorus plating layer 6, a copper plating layer 7, a metallic layer made of at least one element among palladium, platinum, rhodium, and ruthenium, and a gold plating layer 8 are adhered in sequence to the surface of an area which is connected with at least the electrode of the electronic part 3 in the wring layer 2 by means of the connecting member 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a package for housing a semiconductor element for housing a semiconductor element or a hybrid integrated circuit board.

[0002]

2. Description of the Related Art Conventionally, a wiring board used for a package for accommodating a semiconductor element or a hybrid integrated circuit board generally includes an insulating base made of an electrically insulating material such as an aluminum oxide sintered body or an aluminum nitride sintered body. And a wiring layer made of a metal material such as tungsten, molybdenum, or manganese adhered to the surface and inside of the insulating base, and electronic components such as semiconductor elements, capacitance elements, and resistors are formed on the surface of the insulating base. And the electrodes of the electronic component are electrically connected to the wiring layer via a low melting point brazing material such as tin-lead solder.

Such a wiring board is mounted on the external electric circuit board by connecting a predetermined portion of the wiring layer to a wiring conductor of the external electric circuit board via a low melting point brazing material such as tin-lead solder, and at the same time, is mounted on the wiring board. Each electrode of the electronic component mounted on the electronic device is also electrically connected to a predetermined external electric circuit.

In the wiring board, a copper plating layer and a gold plating layer are usually sequentially deposited on the exposed surface of the wiring layer. The copper plating layer lowers the electric resistance of the wiring layer and lowers the electric resistance of the wiring layer. The bonding of the melting point brazing material is good, and the oxidative corrosion of the wiring layer and the copper plating layer is effectively prevented by the gold plating layer.

[0005]

However, in the above-mentioned conventional wiring board, the average crystal grain size of the copper crystal grains forming the copper plating layer is generally about 1 μm, and metal such as tungsten, molybdenum, manganese or the like is used. It is larger than the unevenness diameter (recess: about 1 μm) of the surface of the wiring layer made of the material. Therefore, even when the copper plating layer is applied to the wiring layer surface, the copper plating layer does not sufficiently enter the recesses on the wiring layer surface, and a large number of voids are formed between the wiring layer surface and the copper plating layer, As a result, the adhesion strength between the copper plating layer and the wiring layer is weakened, and the copper plating layer is easily peeled off from the wiring layer by the application of an external force, or has entered a gap between the wiring layer surface and the copper plating layer. There is a disadvantage that the gas expands significantly due to heat or the like when connecting the electrodes of the electronic component to the wiring layer via the low melting point brazing material, and blisters and the like are generated on the copper plating layer.

When heat or the like is applied to the electrodes of the electronic component via the low melting point brazing material on the wiring layer, copper in the copper plating layer moves and diffuses to the surface of the gold plating layer to form a copper layer. There is also a problem that an oxide layer is formed, the wettability of the low melting point brazing material to the wiring layer is deteriorated, and the contact electric resistance is significantly increased.

The present invention has been devised in view of the above-mentioned conventional drawbacks, and has as its object to effectively prevent the occurrence of peeling between the wiring layer and the copper plating layer and the occurrence of blisters or the like in the copper plating layer. And a wiring board capable of firmly attaching and connecting electrodes of an electronic component to the wiring layer via a low melting point brazing material by firmly applying a copper plating layer and a gold plating layer to the wiring layer. It is in.

[0008]

A wiring board according to the present invention is a wiring board comprising an insulating substrate and a wiring layer formed by connecting electrodes of an electronic component through a low melting point brazing material. At least the surface of a region of the wiring layer where the electrodes of the electronic components are joined via the low melting point brazing material has a phosphorus content of 0.1%.
8% by weight or more of a copper-phosphorus plating layer, a copper plating layer, and at least one of palladium, platinum, rhodium, and ruthenium.
A seed metal layer and a gold plating layer are sequentially applied.

In the wiring board according to the present invention, the thickness of the copper-phosphorus plating layer is 0.03 μm or more.

Further, the present invention is characterized in that the average crystal grain size of the copper grains forming the copper-phosphorus plating layer is 0.02 μm or less.

According to the wiring substrate of the present invention, at least the surface of the wiring layer to which the electrodes of the electronic parts are connected via the low melting point brazing material has a phosphorus content of 0.8% by weight or more and a copper-phosphorus Since the copper-phosphorus plating layer having a crystal grain size of 0.3 μm or less is deposited, even if there are many irregularities on the surface of the wiring layer, the copper-phosphorus crystal can enter the recesses well. The wiring layer and the copper-phosphorous plating layer are firmly adhered without forming a gap therebetween, and the copper-phosphorous plating layer has a good adhesion to each of the copper plating layers and the palladium,
Since a metal layer made of at least one of platinum, rhodium and ruthenium and a gold plating layer are sequentially deposited, the copper plating layer and the gold plating layer can be firmly deposited on the wiring layer and the copper plating The electrical resistance of the wiring layer can be reduced by the layer, and the electrodes of the electronic components can be securely and firmly connected to the wiring layer through the low melting point brazing material while effectively preventing the oxidation corrosion of the wiring layer by the gold plating layer. It is possible to make an electrical connection.

At the same time, the diffusion of the copper of the copper plating layer to the surface of the gold plating layer by the metal layer made of at least one of palladium, platinum, rhodium and ruthenium formed between the copper plating layer and the gold plating layer. Effectively prevented, even if heat or the like when joining the electrodes of the electronic component to the wiring layer via the low melting point brazing material acts, the copper oxide layer is hardly formed on the surface of the gold plating layer In addition, it is possible to maintain good bonding property of the low melting point brazing material to the wiring layer.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view showing an embodiment in which the wiring board of the present invention is applied to a package for housing a semiconductor element, wherein 1 is an insulating base, and 2 is a wiring layer. The insulating substrate 1 and the wiring layer 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.

The insulating substrate 1 is made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body, and has a mounting portion for mounting the semiconductor element 3 on the upper surface thereof. The electrodes are connected via a connecting member 5 made of a low melting point brazing material such as solder.

When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder and a solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. The slurry is formed into a slurry-like ceramic slurry, and the ceramic slurry is formed into a sheet-like ceramic green sheet (ceramic green sheet) by using a sheet forming technique such as a doctor blade method or a calender roll method, which is well known in the art. The green sheet is cut and punched to obtain an appropriate shape, and a plurality of the green sheets are laminated. Finally, the laminated ceramic green sheets are fired at a temperature of about 1600 ° C. in a reducing atmosphere. Is done.

The insulating substrate 1 has a large number of wiring layers 2 formed thereon from the mounting portion on the upper surface to the lower surface thereof. Each electrode of the semiconductor element 3 is exposed at the portion exposed on the mounting portion of the wiring layer 2. Are electrically connected via a connecting member 5 made of a low melting point brazing material such as tin-lead solder, and a wiring conductor of an external electric circuit board is provided at a portion led out to the lower surface of the insulating base 1. It is electrically connected via a melting point brazing material or the like.

The wiring layer 2 includes a semiconductor element 3 to be connected.
No function of connecting the electrode of the present invention to an external electric circuit, for example, at least one of tungsten, molybdenum, and manganese such as tungsten, molybdenum, molybdenum / manganese, tungsten / copper, molybdenum / copper, and tungsten / molybdenum / copper. Formed of a metal material.

The wiring layer 2 is formed by applying a metal paste obtained by adding a suitable organic binder or solvent to a metal powder such as tungsten or the like to a ceramic green sheet serving as the insulating substrate 1 in a predetermined pattern by a conventionally known screen printing method. Is applied to a predetermined position of the insulating substrate 1.

As shown in FIG. 2, the wiring layer 2 has a copper-phosphorous plating layer 6 and a copper plating layer 7 at least in regions where electrodes of the semiconductor element 3 are connected via a connecting member 5 made of a low melting point brazing material. , A metal layer 8 made of at least one of palladium, platinum, rhodium and ruthenium, and a gold plating layer 9 are sequentially applied.

The copper-phosphorous plating layer 6 is an underlayer on which a copper plating layer 7, a metal layer 8 made of at least one of palladium, platinum, rhodium and ruthenium and a gold plating layer 9 are adhered to the wiring layer 2 with good adhesion. Acts as a metal layer.

The copper-phosphorous plating layer 6 is formed, for example, by activating palladium on the surface of the wiring layer 2,
Is immersed in a phosphorus-based electroless copper plating solution using a phosphorus-based compound such as hypophosphite as a reducing agent for a predetermined time, thereby to be adhered to the surface of the wiring layer 2 to a predetermined thickness. In this case, the copper-phosphorus plating layer 6 is eutectoidally deposited and the growth of crystal grains is effectively suppressed by the action of the phosphorus component contained. For example, 0.
As a result, even if there are many irregularities on the surface of the wiring layer 2, the copper-phosphorus crystals enter the recesses well and the wiring layer 2 and the copper-phosphorus plating layer 6 become It can be firmly adhered without forming a gap between them.

The copper-phosphorus plating layer 6 must have a phosphorus content of 0.8% by weight or more in order to reduce the average particle size of the copper-phosphorus crystal grains to 0.3 μm or less. By setting the phosphorus content to 0.8% by weight or more, the crystal grain size of copper-phosphorus becomes 0.3 μm or less, and even if the surface of the wiring layer 2 has irregularities, It penetrates and is firmly adhered to the wiring layer 2.

When the copper-phosphorus plating layer 6 has an average grain size of 0.02 μm or less, the copper-phosphorus plating layer 6 can be more firmly formed by the wiring layer 2 having an uneven surface. Can be applied. Therefore, the copper
The phosphorus plating layer 6 has an average grain size of copper-phosphorus crystal grains of 0.1.
It is preferable to set the thickness to 02 μm or less, and more preferable to set it to 0.01 μm or less.

The average particle size of the copper-phosphorus plating layer 6 is set to 0.1.
In order to adjust the phosphorus content in the copper-phosphorous plating layer 6 to be not more than 0.01 μm, the phosphorus content in the copper-phosphorous plating layer 6 should be about 1.3% by weight or more. The content is adjusted to about 1% by weight or more, and considering the properties such as electric conductivity, 1% by weight to 1% by weight.
It is preferred to be in the range of 0% by weight.

Further, when the copper-phosphorous plating layer 6 has a thickness of less than 0.03 μm, it is difficult to completely cover the entire surface of the wiring layer 2, and the copper plating layer 7, palladium, platinum, It tends to be difficult to firmly attach the metal layer 8 made of at least one of rhodium and ruthenium and the gold plating layer 9 to the wiring layer 2. Accordingly, the copper-phosphorus plating layer 6 has a thickness of 0.03.
It is preferable that the thickness be set to not less than μm.

Further, the surface of the copper-phosphorous plating layer 6 is adhered to any of the copper-phosphorous plating layer 6 and a metal layer 8 composed of at least one of palladium, platinum, rhodium, and ruthenium described later. Copper plating layer 7 with excellent properties
Are formed.

The copper plating layer 7 has a metal layer 8 made of at least one of palladium, platinum, rhodium and ruthenium firmly adhered to the wiring layer 2 and a low melting point brazing material such as solder for the wiring layer 2. And strongly reduces the electrical resistance of the wiring layer 2.

The copper plating layer 7 is formed, for example, by immersing the wiring layer 2 on which the copper-phosphorus plating layer 6 is applied in an electroless copper plating solution using formalin as a reducing agent for a predetermined time. A predetermined thickness is formed on the surface of the phosphor plating layer 6. In this case, when an electroless copper plating solution using formalin as a reducing agent is used, since the plating solution has an autocatalytic action, the surface of the copper-phosphorus plating layer 6 is not subjected to the activation treatment, and the copper plating layer 7 is formed. It is possible to adhere to the copper-phosphorous plating layer 6 with a predetermined thickness and a large bonding strength.

Since the copper plating layer 7 is formed using formalin or the like which does not contain an eutectoid component and has a high purity, the bonding property of the wiring layer 2 to a low melting point brazing material such as solder is greatly improved. At the same time, the electric resistance becomes an extremely small value, so that it is possible to effectively prevent the occurrence of attenuation in electric signals and the like propagating through the wiring layer 2.

The copper plating layer 7 has on its surface at least one of palladium, platinum, rhodium and ruthenium, which has excellent adhesion to both the copper plating layer 7 and a gold plating layer 9 described later. A seed metal layer 8 is applied.

The metal layer 8 made of at least one of palladium, platinum, rhodium and ruthenium acts when the electrode of the semiconductor element 3 is connected to the wiring layer 2 via a low melting point brazing material such as tin-lead solder. This serves to prevent the copper of the copper plating layer 7 from moving and diffusing to the surface of the gold plating layer 9 described later due to the generated heat.

The metal layer 8 containing at least one of palladium, platinum, rhodium and ruthenium as a main component can be formed by a thin film forming technique such as a plating method, a vapor deposition method, an ion plating method and a sputtering method. For example, in the case of palladium, the exposed surface of the wiring layer 2 (copper plating layer 7) is placed in an electroless palladium plating solution containing a palladium compound such as palladium chloride and a reducing agent such as trimethylamine borane, hydrazine and formic acid as main components. Is immersed for a predetermined time, thereby forming a coating with a predetermined thickness.

When the metal layer 8 made of at least one of palladium, platinum, rhodium and ruthenium has a thickness of less than 0.05 μm, the copper of the copper plating layer 7 moves and diffuses to the surface of the gold plating layer 9. If the thickness exceeds 3 μm, the residual internal stress generated during the formation may increase, and it may be difficult to firmly adhere to the copper plating layer 7. Therefore, it is preferable that the metal layer 8 made of at least one of palladium, platinum, rhodium, and ruthenium has a thickness in the range of 0.05 μm to 3 μm.

The palladium, platinum, rhodium,
A gold plating layer 9 is formed on the surface of the metal layer 8 made of at least one kind of ruthenium.

The gold plating layer 9 prevents the wiring layer 2, the copper-phosphorus plating layer 6 and the copper plating layer 7 from being oxidized and corroded, and improves the bonding property of the low melting point brazing material to the wiring layer 2. Works.

The gold plating layer 9 is formed, for example, by placing the above-mentioned palladium, platinum, rhodium, ruthenium in an electroless gold plating solution containing gold potassium cyanide as a gold compound and ethylenediaminetetraacetic acid as a complexing agent as main components. By immersing the wiring layer 2 on which the metal layer 8 made of at least one of the above is adhered for a predetermined time, the wiring layer 2 is adhered to the surface of the metal layer 8 to a predetermined thickness.

The gold plating layer 9 has a thickness of 0.05
If the thickness is less than μm, it may be difficult to effectively prevent oxidative corrosion of the copper-phosphorous plating layer 6 and the copper plating layer 7, and if the thickness exceeds 0.8 μm,
When the electrode of the semiconductor element 3 is connected to the wiring layer 2 via the connection member 5 made of a low melting point brazing material such as solder, a brittle intermetallic compound is generated between tin and gold of the low melting point brazing material 5, There is a risk that the reliability of the connection of the semiconductor element 3 to the wiring layer 2 will be significantly reduced. Therefore, the gold plating layer 8
It is preferable that the thickness be in the range of 0.05 μm to 0.8 μm.

On the other hand, the insulating substrate 1 on which the semiconductor element 3 is mounted has a lid 10 joined to the upper surface thereof via a sealing material made of resin, glass, brazing material or the like.
The semiconductor element 3 is hermetically sealed inside by the insulating base 1 and the insulating base 1.

The lid 10 is made of a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, or a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. For example, in the case of a sintered body made of aluminum oxide, a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide is formed into a bowl shape by adopting a conventionally known press molding method, and is formed into a bowl shape. It is formed by firing at a temperature of 1500 ° C.

Thus, according to the package for housing a semiconductor element to which the wiring board of the present invention is applied, the electrodes of the semiconductor element 3 are connected to the wiring layer 2 exposed on the surface of the mounting portion on the upper surface of the insulating base 1 by using a low melting point solder such as solder. The cover 10 is electrically and mechanically connected via a connection member 5 made of a material, and then the lid 10 is joined to the upper surface of the insulating base 1 via a sealing material made of resin, glass, brazing material, or the like. The semiconductor device 3 as a final product is completed by hermetically housing the semiconductor element 3 in a container including the base 1 and the lid 10.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. The present invention may be applied to a wiring board for a hybrid integrated circuit on which electronic components such as a capacitor and a resistor are mounted.

[0043]

According to the wiring board of the present invention, at least the surface of the wiring layer to which the electrodes of the electronic parts are connected via the low-melting brazing material has a phosphorus content of 0.8% by weight or more and a copper-containing material. Since the copper-phosphorus plating layer having a small crystal grain diameter of phosphorus of 0.3 μm or less is deposited, even if there are many irregularities on the surface of the wiring layer, the crystal of copper-phosphorus is well formed in the concave portion. The wiring layer and the copper-phosphorus plating layer are firmly adhered without forming a gap between the wiring layer and the copper-phosphorus plating layer, and a copper plating layer having good adhesion, palladium,
Since a metal layer made of at least one of platinum, rhodium and ruthenium and a gold plating layer are sequentially deposited, the copper plating layer and the gold plating layer can be firmly deposited on the wiring layer and the copper plating The electrical resistance of the wiring layer can be reduced by the layer, and the electrodes of the electronic components can be securely and firmly connected to the wiring layer through the low melting point brazing material while effectively preventing the oxidation corrosion of the wiring layer by the gold plating layer. It is possible to make an electrical connection.

At the same time, the diffusion of the copper of the copper plating layer to the surface of the gold plating layer by the metal layer formed of at least one of palladium, platinum, rhodium and ruthenium formed between the copper plating layer and the gold plating layer. Effectively prevented, even if heat or the like when joining the electrodes of the electronic component to the wiring layer via the low melting point brazing material acts, the copper oxide layer is hardly formed on the surface of the gold plating layer In addition, it is possible to maintain good bonding property of the low melting point brazing material to the wiring layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing one embodiment in which a wiring board of the present invention is applied to a package for housing a semiconductor element.

FIG. 2 is an enlarged view of a main part of the wiring board shown in FIG.

[Explanation of symbols]

1. Insulating base 2. Wiring layer 3. ... Semiconductor element 4 ... Wiring board 5 ... Connecting member 6 ... Copper-phosphorous plating layer 7 ... Copper plating layer 8 ... Palladium, platinum, rhodium, ruthenium Metal layer composed of at least one type 9 Gold plating layer 10 Lid

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H05K 3/34 501 H01L 23/14 M

Claims (3)

[Claims] A wiring board comprising an insulating substrate and a wiring layer to which electrodes of an electronic component are connected via a low melting point brazing material, wherein at least the electrode of the electronic component is low in the wiring layer. A copper-phosphorus plating layer having a phosphorus content of 0.8% by weight or more, a copper plating layer, and at least one of palladium, platinum, rhodium, and ruthenium on a surface of a region to be joined via the melting point brazing material. A wiring board, wherein a metal layer and a gold plating layer are sequentially applied. 2. The copper-phosphorus plating layer has a thickness of 0.03 μm.
2. The wiring board according to claim 1, wherein m is not less than m. 3. The wiring board according to claim 1, wherein the average crystal grain size of the copper crystal grains forming the copper-phosphorous plating layer is 0.02 μm or less.